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Author SHA1 Message Date
Akif Ejaz c1e3678797 Add QEMU based CI regression test infra for RV32 and RV64 (#526) 
Added a QEMU virt-machine BSP and CTest infrastructure to run the
ThreadX regression suite on both RISC-V 32-bit and 64-bit targets
in CI.

New components:
- BSP (entry, trap, PLIC, CLINT timer, UART, linker script) targeting
  QEMU virt machine for RV32 and RV64
- CMake build system with Ninja, supporting multiple build configs
- CI scripts: install_riscv.sh (toolchain + QEMU), build_tx_riscv.sh,
  test_tx_riscv.sh
- GitHub Actions workflow job for RISC-V regression gating

Port fixes:
- RV32 tx_thread_context_restore.S: set MPIE alongside MPP (0x1800 →
  0x1880) so mret re-enables interrupts
- RV32/RV64 tx_port.h: add TX_REGRESSION_TEST extension macros needed
  by the test harness
- RV32/RV64 example_build scripts: add compile and QEMU launch steps

Regression test portability fixes:
- Block memory tests: increase pool sizes (320 → 340) to accommodate
  larger RISC-V block-header alignment
- Byte memory test: replace hardcoded offsets with BYTE_POOL_OVERHEAD
  macro for portable pool-size computation
- Event flag timeout test: make counter tolerance unconditional,
  removing linux-only guard

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-05-19 11:03:23 -04:00
Christos Papadopoulos 0dd6d28afb Fixed MPIE being cleared leading to have interrupts being disable after an mret instruction (#522) 
* Fixed MPIE being cleared leading to have interrupts being disable when returning from machine mode

* Removed wrong register operand and replaced by immediate value
 2026-05-13 09:00:54 -04:00
An Dao 9ab0cf9683 Moved tx_initialize_low_level.S to example_build for Cortex-M33/M55/M85 GNU (#452) (#514) 
The Cortex-M33, M55, and M85 GNU ports incorrectly include tx_initialize_low_level.S as a library source in CMakeLists.txt. This file is board-specific initialization code that users must
customize for their hardware, and including it in the library causes linker conflicts when users provide their own implementation (e.g., via CMake FetchContent).

This change aligns these ports with the established pattern used by
Cortex-M0/M3/M4/M7 GNU ports:
- Move tx_initialize_low_level.S from src/ to example_build/
- Remove it from CMakeLists.txt target_sources
- Add sample_threadx.c to example_build/ for consistency

Signed-off-by: An Dao <webmaster@taktflow-systems.com>
 2026-05-13 08:56:25 -04:00
Francisco Manuel Merino Torres 42adda4457 Added a riscv32 for the OpenHW CVA6 (#511) 2026-05-13 07:46:54 -04:00
Frédéric Desbiens 3c4d20285f Corrected typos in two test filenames (#527) 2026-04-29 13:22:15 -04:00
Frédéric DesbiensandCopilot 33efad3fee Fixed race condition and message loss in Cortex-M ports (#523) 
* Fixed race condition and message loss in Cortex-M GNU, AC6, and IAR ports (#516)

- Added compiler memory barriers to BASEPRI management functions in tx_port.h.
- Added architectural barriers (DSB/ISB) to scheduler return paths in tx_port.h and tx_thread_system_return.S to prevent fall-through before context switch.
- These changes address spurious thread resumption and lost messages, especially when TX_NOT_INTERRUPTABLE is enabled.
- These changes ensure that pending interrupts (specifically PendSV) are recognised before subsequent instructions are executed, following Kairalite's feedback and ARM architectural guidelines.

 Assisted-by: Gemini (Gemini 2.0 Flash)

-----

* Added a comment in common/tx_queue_cleanup to document why the NI path omits revalidation guards

- In `TX_NOT_INTERRUPTABLE` mode, the caller keeps interrupts disabled across the entire cleanup call, so the race window that makes the guards necessary in the interruptable path cannot occur. Add a comment explaining this, and noting that all paths that resume a suspended thread clear tx_thread_suspend_cleanup before calling
_tx_thread_system_ni_resume, making double-cleanup impossible.

This prevents future false-positive suggestions (e.g. from AI tools) to add redundant checks to the NI path.

Relates to: eclipse-threadx/threadx#516

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
 2026-04-29 09:10:57 -04:00
Frédéric Desbiens d5c75fd38f Merge pull request #361 from howjmay/typo 
Fixed typos in several regression test files
 2026-04-15 11:38:51 -04:00
Frédéric Desbiens f81d1c9eb5 Merge branch 'dev' into typo 2026-04-15 11:36:53 -04:00
Frédéric Desbiens 454ab56fce Merge pull request #278 from Polarisru/master 
Fixed SysTick initialization problem in tx_initialize_low_level.s for Cortex-M0.
 2026-04-15 11:23:57 -04:00
Frédéric Desbiens 4f1b9bfdc1 Merge pull request #524 from fdesbiens/fix-pr-277 
Added conditional CMake support for ThreadX SMP
 2026-04-15 11:11:51 -04:00
Frédéric Desbiens 98e4754381 build: add conditional CMake support for ThreadX SMP 
- Introduce THREADX_SMP option in root CMakeLists.txt.
- Implement conditional source and port directory selection for SMP builds.
- Add CMake support for common_smp and Cortex-A9 SMP port.
- Fix linker flags in Cortex-A9 SMP sample build script.
- Remove duplicate invalidateCaches_IS declarations in v7.h headers.

Assisted-by: Gemini (Experimental)
 2026-04-15 10:52:14 -04:00
Frédéric Desbiens 9dcb05cb78 Merge pull request #273 from hodcarrier/master 
Fixed the link flag in the Cortex-A9 sample
 2026-04-15 09:42:41 -04:00
Frédéric Desbiens 12553eaf2c Merge pull request #270 from MrNetic/patch-1 
Removed extra spaces in tx_port.h.
 2026-04-15 09:38:15 -04:00
Frédéric Desbiens a0dc185f66 Merge pull request #508 from goodnorning/feature/rv64_rvv_support 
Added rv64 rvv support
 2026-04-14 09:26:33 -04:00
Frédéric Desbiens 57e317a7b5 Merge pull request #521 from jblanchard-jblopen/patch-2 
Fixed TX_TIMER_TICKS_PER_SECOND default value in tx_user_sample.h
 2026-04-14 09:12:31 -04:00
Jonathan Blanchard 2cdebde30a Fix default TX_TIMER_TICKS_PER_SECOND default value in tx_user_sample.h 
Changed default value to TX_16_ULONG.
 2026-04-12 10:17:10 -04:00
shuta.lst dfafc96149 RISC-V64 qemu_virt example support RVV Extension; 2026-04-07 14:03:24 +08:00
shuta.lst 2f1fc52918 RISC-V64 arch. port support RVV Extension; 2026-04-07 11:41:33 +08:00
Frédéric Desbiens 8c57362209 Merge pull request #512 from eclipse-threadx/master 
Merge pull request #510 from eclipse-threadx/dev
 2026-03-12 18:18:39 +01:00
Frédéric Desbiens 3726d7906b Merge pull request #510 from eclipse-threadx/dev
cortex_m / Cortex M0 build (push) Has been cancelled
cortex_m / Cortex M3 build (push) Has been cancelled
cortex_m / Cortex M4 build (push) Has been cancelled
cortex_m / Cortex M7 build (push) Has been cancelled
regression_test / tx (push) Has been cancelled
regression_test / smp (push) Has been cancelled
regression_test / deploy (push) Has been cancelled 
Merge changes ahead of the v6.5.0.202601 release
v6.5.0.202601_rel 		2026-03-06 19:27:49 +01:00
Frédéric Desbiens c3259a2160 Updated copyright headers and version number constants (#509) 
* Updated version number constants

* Removed revision history from all files

* Added Eclipse ThreadX contributors' copyright header
 2026-03-05 10:46:30 +01:00
Frédéric Desbiens 385d39f421 Merge pull request #502 from quintauris-tech/riscv32-clang-port 
Added a RV32 Clang port
v6.5.0.202601_pre 		2026-03-04 08:36:53 +01:00
Frédéric Desbiens b3e8a9aa20 Merge pull request #500 from goodnorning/feature/support_xuantie_e906 
Added support for the XuanTie E906 CPU.
 2026-03-04 08:34:59 +01:00
Frédéric Desbiens 0c92f48d50 Merge pull request #493 from mehmetteren/dev 
Fixed VFP build failure in Cortex-A tx_thread_schedule.S
 2026-03-02 11:41:53 -05:00
Frédéric Desbiens da5093f84b Proposed changes to the original PR 2026-03-02 14:24:07 +01:00
Frédéric Desbiens 5910de86d6 Merge pull request #506 from akifejaz/qemu-examples 
Updated the QEMU examples to match the new RV port format
 2026-03-01 13:02:32 -05:00
Akif Ejaz cd101d9ab4 update comments 
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-03-01 15:13:28 +05:00
Akif Ejaz ff287cce97 update qemu examples as per new rv port format 
- removed the REGBYTES, STORE/LOAD macros

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-03-01 14:14:19 +05:00
Frédéric Desbiens 33610aa190 Merge pull request #504 from fdesbiens/issue499 
Added ax attribute to ThreadX module example build preamble.S files
 2026-02-27 10:27:25 -05:00
Frédéric Desbiens f4051070db Added ax attribute to ThreadX module example build preamble.S files 2026-02-27 10:25:05 -05:00
Frédéric Desbiens 3bbc096d78 Merge pull request #503 from fdesbiens/issue499 
Added a missing symbol to tx_api.h for TX SMP.
 2026-02-26 17:28:26 -05:00
Frédéric Desbiens c62ed82b1a Added a missing symbol to tx_api.h for TX SMP. 2026-02-26 17:22:25 -05:00
Francisco Manuel Merino Torres 49439bfa9c Fixes to the RISC-V32 architecture port layer for Clang. 2026-02-26 11:54:26 +01:00
Francisco Manuel Merino Torres 888f7a42b0 Added a RISC-V32 architecture port layer for Clang. 2026-02-26 10:49:23 +01:00
Frédéric Desbiens 8f126ee414 Merge pull request #492 from akifejaz/qemu-virt-rv32 
Added a RISC-V32 QEMU-virt example
 2026-02-25 08:24:38 -05:00
Frédéric Desbiens 0a0615ada3 Merge pull request #501 from akifejaz/rv64-gnu-port 
Removed dead code from riscv64/gnu port
 2026-02-25 08:23:49 -05:00
shuta.lst 7bf83088b8 Support XuanTie E906 CPU 
- Place the E906 implementation in the ports/risc-v32/gnu directory;
 - Remove code unrelated to the xuantie_smartl_fpga demo;
 2026-02-25 11:23:09 +08:00
Akif Ejaz 1d796d5fde Add RISC-V32 arch. port layer 
This update adapts the ThreadX low-level kernel routines
for RV32, including:
  - startup and initialization logic
  - context save/restore implementations
  - interrupt control and scheduler entry
  - thread stack build and system return paths
  - timer interrupt handling
  - made it complient as per new risc-v64/gnu
      & threadx style
  - added reademe for risc-v32/gnu port

These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-02-25 09:06:02 +08:00
Frédéric Desbiens 4de9be75e5 Merge pull request #490 from akifejaz/rv32-port 
Added a RISC-V32 architecture port layer for GCC.
 2026-02-24 11:06:03 -05:00
Akif Ejaz 757db54d6d Add RISC-V32 arch. port layer 
This update adapts the ThreadX low-level kernel routines
for RV32, including:
  - startup and initialization logic
  - context save/restore implementations
  - interrupt control and scheduler entry
  - thread stack build and system return paths
  - timer interrupt handling
  - made it complient as per new risc-v64/gnu
      & threadx style
  - added reademe for risc-v32/gnu port

These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-02-16 17:15:13 +05:00
Akif Ejaz c1bff3ae34 removed dead code in riscv64/gnu port 
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-02-16 13:57:51 +05:00
shuta.lst ede5aa2867 Support XuanTie E906 CPU. 
- add ThreadX porting codes for XuanTie E906.
 - add example for XuanTie E906 running on QEMU smartl.
 2026-02-12 23:13:31 +08:00
Frédéric Desbiens 579246b4a2 Merge pull request #494 from spir6s/master 
Added missing ULONG64 definition for RX ports needed by USBX and NetX Duo
 2026-02-05 09:52:58 -05:00
Frédéric Desbiens 0b0f1d0911 Merge pull request #496 from akifejaz/rv64-gnu-port 
Improved RV64/GNU port robustness, portability, and CSR handling
 2026-02-05 09:50:08 -05:00
Akif Ejaz 21256bed51 Cleanup the macros in tx_port.h & comments in inc/*.S 
- removed the trailing whitespaces

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-02-05 16:16:59 +05:00
Akif Ejaz 99ed67df5a few cleanups 
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-01-26 16:08:51 +05:00
Akif Ejaz 6c25effb40 improve port robustness, portability, and CSR handling 
- removed tx_port.h dependency from .S files
- replaced tx_timer_interrupt.c with tx_timer_interrupt.S
-  made some cleanups, formatting to better readability
- removed macros (LOAD/STORE/REGBYTES)
  changed register nomenclature to use RISC-V ABI
  names (ra, sp, t0, etc.)
- added readme_threadx.txt

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
 2026-01-26 15:48:46 +05:00
Frédéric Desbiens 4b6e8100d9 Merge commit from fork
cortex_m / Cortex M0 build (push) Has been cancelled
cortex_m / Cortex M3 build (push) Has been cancelled
cortex_m / Cortex M4 build (push) Has been cancelled
cortex_m / Cortex M7 build (push) Has been cancelled
regression_test / tx (push) Has been cancelled
regression_test / smp (push) Has been cancelled
regression_test / deploy (push) Has been cancelled 
Fix: Return 0u when no counters available
v6.4.5.202504_rel 		2026-01-09 09:38:16 -05:00
Frédéric Desbiens a9b31c3102 Merge pull request #495 from eclipse-threadx/dev 
Merge changes ahead of the v6.4.5.202504 release
 2026-01-09 09:36:27 -05:00
Frédéric Desbiens 5c58767c5d Updated the version number 2026-01-09 09:33:14 -05:00