mirror of
https://github.com/eclipse-threadx/threadx.git
synced 2026-10-06 06:59:08 +08:00
Add RISC-V32 arch. port layer
This update adapts the ThreadX low-level kernel routines
for RV32, including:
- startup and initialization logic
- context save/restore implementations
- interrupt control and scheduler entry
- thread stack build and system return paths
- timer interrupt handling
- made it complient as per new risc-v64/gnu
& threadx style
- added reademe for risc-v32/gnu port
These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
This commit is contained in:
Akif Ejaz
shuta.lst
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# Toolchain settings
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set(CMAKE_C_COMPILER riscv32-unknown-elf-gcc)
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set(CMAKE_CXX_COMPILER riscv32-unknown-elf-g++)
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set(AS riscv32-unknown-elf-as)
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set(AR riscv32-unknown-elf-ar)
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set(OBJCOPY riscv32-unknown-elf-objcopy)
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set(OBJDUMP riscv32-unknown-elf-objdump)
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set(SIZE riscv32-unknown-elf-size)
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set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
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set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
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set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
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set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
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# this makes the test compiles use static library option so that we don't need to pre-set linker flags and scripts
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set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
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set(CMAKE_C_FLAGS "${CFLAGS}" CACHE INTERNAL "c compiler flags")
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set(CMAKE_CXX_FLAGS "${CXXFLAGS}" CACHE INTERNAL "cxx compiler flags")
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set(CMAKE_ASM_FLAGS "${ASFLAGS} -D__ASSEMBLER__ -D__riscv_float_abi_single" CACHE INTERNAL "asm compiler flags")
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set(CMAKE_EXE_LINKER_FLAGS "${LDFLAGS}" CACHE INTERNAL "exe link flags")
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SET(CMAKE_C_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "c debug compiler flags")
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SET(CMAKE_CXX_FLAGS_DEBUG "-Og -g -ggdb3" CACHE INTERNAL "cxx debug compiler flags")
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SET(CMAKE_ASM_FLAGS_DEBUG "-g -ggdb3" CACHE INTERNAL "asm debug compiler flags")
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SET(CMAKE_C_FLAGS_RELEASE "-O3" CACHE INTERNAL "c release compiler flags")
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SET(CMAKE_CXX_FLAGS_RELEASE "-O3" CACHE INTERNAL "cxx release compiler flags")
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SET(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm release compiler flags")
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@@ -0,0 +1,12 @@
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# Name of the target
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set(CMAKE_SYSTEM_NAME Generic)
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set(CMAKE_SYSTEM_PROCESSOR risc-v32)
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set(THREADX_ARCH "risc-v32")
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set(THREADX_TOOLCHAIN "gnu")
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set(ARCH_FLAGS "-g -march=rv32gc -mabi=ilp32d -mcmodel=medany")
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set(CFLAGS "${ARCH_FLAGS}")
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set(ASFLAGS "${ARCH_FLAGS}")
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set(LDFLAGS "${ARCH_FLAGS}")
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include(${CMAKE_CURRENT_LIST_DIR}/riscv32-unknown-elf.cmake)
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@@ -0,0 +1,19 @@
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target_sources(${PROJECT_NAME}
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PRIVATE
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# {{BEGIN_TARGET_SOURCES}}
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${CMAKE_CURRENT_LIST_DIR}/src/tx_initialize_low_level.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_restore.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context_save.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_stack_build.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
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${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.S
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# {{END_TARGET_SOURCES}}
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)
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target_include_directories(${PROJECT_NAME}
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PUBLIC
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${CMAKE_CURRENT_LIST_DIR}/inc
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)
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/***************************************************************************
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* Copyright (c) 2025 10xEngineers
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Initialize */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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.section .data
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.global __tx_free_memory_start
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__tx_free_memory_start:
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.section .text
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_initialize_low_level RISC-V32/GNU */
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/* 6.4.x */
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/* AUTHOR */
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/* */
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/* Akif Ejaz, 10xEngineers */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function is responsible for any low-level processor */
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/* initialization, including setting up interrupt vectors, setting */
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/* up a periodic timer interrupt source, saving the system stack */
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/* pointer for use in ISR processing later, and finding the first */
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/* available RAM memory address for tx_application_define. */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* _tx_initialize_kernel_enter ThreadX entry function */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */
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/* */
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/**************************************************************************/
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/* VOID _tx_initialize_low_level(VOID)
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{ */
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.global _tx_initialize_low_level
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.weak _tx_initialize_low_level
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_tx_initialize_low_level:
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/* Save the system stack pointer. */
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/* _tx_thread_system_stack_ptr = sp; */
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la t0, _tx_thread_system_stack_ptr // Pickup address of system stack ptr
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sw sp, 0(t0) // Save system stack pointer
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/* Pickup first free address. */
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/* _tx_initialize_unused_memory(__tx_free_memory_start); */
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la t0, __tx_free_memory_start // Pickup first free address
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la t1, _tx_initialize_unused_memory // Pickup address of unused memory
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sw t0, 0(t1) // Save unused memory address
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/* Initialize floating point control/status register if floating point is enabled. */
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#ifdef __riscv_flen
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li t0, 0
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csrw fcsr, t0 // Clear FP control/status register
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#endif
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ret
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/* Timer Interrupt Handler Note:
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Platform-specific implementations must provide their own timer ISR.
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The timer interrupt handler should follow this execution flow:
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1. Disable interrupts (if not done by hardware exception entry)
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2. Allocate interrupt stack frame (65*4 bytes with FP, 32*4 bytes without)
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3. Save RA (x1) on the stack at offset 28*4
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4. Call _tx_thread_context_save to save thread context
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5. Call _tx_timer_interrupt to process the timer tick
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6. Call _tx_thread_context_restore to resume execution (does not return)
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Example (for CLINT timer):
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_tx_timer_interrupt_handler:
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addi sp, sp, -32*4
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sw ra, 28*4(sp)
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call _tx_thread_context_save
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call _tx_timer_interrupt
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j _tx_thread_context_restore
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The port assumes Machine mode (M-mode) execution.
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For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
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See the RISC-V Privileged Specification for more details. */
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/***************************************************************************
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* Copyright (c) 2025 10xEngineers
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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.section .text
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_thread_interrupt_control RISC-V32/GNU */
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/* 6.4.x */
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/* AUTHOR */
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/* */
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/* Akif Ejaz, 10xEngineers */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function is responsible for changing the interrupt lockout */
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/* posture of the system. */
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/* */
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/* INPUT */
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/* */
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/* new_posture New interrupt lockout posture */
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/* */
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/* OUTPUT */
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/* */
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/* old_posture Old interrupt lockout posture */
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/* */
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/* CALLS */
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/* */
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/* None */
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/* */
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/* CALLED BY */
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/* */
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/* Application Code */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */
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/* */
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/**************************************************************************/
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/* UINT _tx_thread_interrupt_control(UINT new_posture)
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{ */
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.global _tx_thread_interrupt_control
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_tx_thread_interrupt_control:
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/* Pickup current interrupt posture. */
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csrr a1, mstatus // Pickup mstatus
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andi a1, a1, 0x08 // Mask out all but MIE
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/* Check for the new posture. */
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beqz a0, _tx_thread_interrupt_disable // If 0, disable interrupts
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/* Enable interrupts. */
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csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3)
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j _tx_thread_interrupt_control_exit // Return to caller
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_tx_thread_interrupt_disable:
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/* Disable interrupts. */
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csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
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_tx_thread_interrupt_control_exit:
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/* Return the old interrupt posture. */
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mv a0, a1 // Setup return value
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ret // Return to caller
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/* } */
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File diff suppressed because it is too large
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Load Diff
@@ -0,0 +1,174 @@
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/***************************************************************************
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* Copyright (c) 2025 10xEngineers
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*
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* This program and the accompanying materials are made available under the
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* terms of the MIT License which is available at
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* https://opensource.org/licenses/MIT.
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*
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* SPDX-License-Identifier: MIT
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**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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.section .text
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/**************************************************************************/
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/* */
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/* FUNCTION RELEASE */
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/* */
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/* _tx_thread_system_return RISC-V32/GNU */
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/* 6.4.x */
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/* AUTHOR */
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/* */
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/* Akif Ejaz, 10xEngineers */
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/* */
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/* DESCRIPTION */
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/* */
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/* This function is target processor specific. It is used to transfer */
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/* control from a thread back to the system. Only a minimal context */
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/* is saved since the compiler assumes temp registers are going to get */
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/* slicked by a function call anyway. */
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/* */
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/* INPUT */
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/* */
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/* None */
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/* */
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/* OUTPUT */
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/* */
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/* None */
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/* */
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/* CALLS */
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/* */
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/* _tx_thread_schedule Thread scheduling loop */
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/* */
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/* CALLED BY */
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/* */
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/* ThreadX components */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 23-12-2025 Akif Ejaz Initial Version 6.4.x */
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/* */
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/**************************************************************************/
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/* VOID _tx_thread_system_return(VOID)
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{ */
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.global _tx_thread_system_return
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_tx_thread_system_return:
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/* Save minimal context on the stack. */
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/* sp -= sizeof(stack_frame); */
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#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
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addi sp, sp, -29*4 // Allocate space on the stack - with floating point enabled
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#else
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addi sp, sp, -16*4 // Allocate space on the stack - without floating point enabled
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#endif
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/* Store floating point preserved registers. */
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#if defined(__riscv_float_abi_single)
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fsw f8, 15*4(sp) // Store fs0
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fsw f9, 16*4(sp) // Store fs1
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fsw f18, 17*4(sp) // Store fs2
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fsw f19, 18*4(sp) // Store fs3
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fsw f20, 19*4(sp) // Store fs4
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fsw f21, 20*4(sp) // Store fs5
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fsw f22, 21*4(sp) // Store fs6
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fsw f23, 22*4(sp) // Store fs7
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fsw f24, 23*4(sp) // Store fs8
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fsw f25, 24*4(sp) // Store fs9
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fsw f26, 25*4(sp) // Store fs10
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fsw f27, 26*4(sp) // Store fs11
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csrr t0, fcsr
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sw t0, 27*4(sp) // Store fcsr
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#elif defined(__riscv_float_abi_double)
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fsd f8, 15*4(sp) // Store fs0
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fsd f9, 16*4(sp) // Store fs1
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fsd f18, 17*4(sp) // Store fs2
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fsd f19, 18*4(sp) // Store fs3
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fsd f20, 19*4(sp) // Store fs4
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fsd f21, 20*4(sp) // Store fs5
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fsd f22, 21*4(sp) // Store fs6
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fsd f23, 22*4(sp) // Store fs7
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fsd f24, 23*4(sp) // Store fs8
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fsd f25, 24*4(sp) // Store fs9
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fsd f26, 25*4(sp) // Store fs10
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fsd f27, 26*4(sp) // Store fs11
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csrr t0, fcsr
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sw t0, 27*4(sp) // Store fcsr
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#endif
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sw zero, 0(sp) // Solicited stack type
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sw ra, 13*4(sp) // Save return address
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sw s0, 12*4(sp) // Save s0
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sw s1, 11*4(sp) // Save s1
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sw s2, 10*4(sp) // Save s2
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sw s3, 9*4(sp) // Save s3
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sw s4, 8*4(sp) // Save s4
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sw s5, 7*4(sp) // Save s5
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sw s6, 6*4(sp) // Save s6
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sw s7, 5*4(sp) // Save s7
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sw s8, 4*4(sp) // Save s8
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sw s9, 3*4(sp) // Save s9
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sw s10, 2*4(sp) // Save s10
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sw s11, 1*4(sp) // Save s11
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csrr t0, mstatus // Pickup mstatus
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sw t0, 14*4(sp) // Save mstatus
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/* Lockout interrupts. will be enabled in _tx_thread_schedule */
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csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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call _tx_execution_thread_exit // Call the thread execution exit function
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#endif
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la t0, _tx_thread_current_ptr // Pickup address of pointer
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lw t1, 0(t0) // Pickup current thread pointer
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la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address
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/* Save current stack and switch to system stack. */
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/* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
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SP = _tx_thread_system_stack_ptr; */
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sw sp, 8(t1) // Save stack pointer
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lw sp, 0(t2) // Switch to system stack
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/* Determine if the time-slice is active. */
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/* if (_tx_timer_time_slice)
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{ */
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la t4, _tx_timer_time_slice // Pickup time slice variable addr
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lw t3, 0(t4) // Pickup time slice value
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la t2, _tx_thread_schedule // Pickup address of scheduling loop
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beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it
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/* Save time-slice for the thread and clear the current time-slice. */
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/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
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_tx_timer_time_slice = 0; */
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sw t3, 24(t1) // Save current time-slice for thread
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sw zero, 0(t4) // Clear time-slice variable
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/* } */
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_tx_thread_dont_save_ts:
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/* Clear the current thread pointer. */
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/* _tx_thread_current_ptr = TX_NULL; */
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sw x0, 0(t0) // Clear current thread pointer
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jr t2 // Return to thread scheduler
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/* } */
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File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user