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Cleanup the macros in tx_port.h & comments in inc/*.S

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- removed the trailing whitespaces

Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
This commit is contained in:
Akif Ejaz
2026-02-05 16:16:59 +05:00
parent 99ed67df5a
commit 21256bed51
9 changed files with 677 additions and 668 deletions
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ports/risc-v64/gnu/inc/tx_port.h
+14 -5
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -236,8 +236,17 @@ UINT _tx_thread_interrupt_control(UIN
#define TX_INTERRUPT_SAVE_AREA register UINT interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
#define TX_RESTORE _tx_thread_interrupt_control(interrupt_save);
#define TX_DISABLE __asm__ volatile("csrrci %0, mstatus, 8" : "=r" (interrupt_save) :: "memory");
#define TX_RESTORE { \
unsigned long _temp_mstatus; \
__asm__ volatile( \
"csrc mstatus, 8\n" \
"andi %0, %1, 8\n" \
"csrs mstatus, %0" \
: "=&r" (_temp_mstatus) \
: "r" (interrupt_save) \
: "memory"); \
}
#else
ports/risc-v64/gnu/src/tx_initialize_low_level.S
+14 -14
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -74,18 +74,18 @@ _tx_initialize_low_level:
/* Save the system stack pointer. */
/* _tx_thread_system_stack_ptr = sp; */
la t0, _tx_thread_system_stack_ptr
sd sp, 0(t0) /* Save system stack pointer */
sd sp, 0(t0) // Save system stack pointer
/* Pickup first free address. */
/* _tx_initialize_unused_memory(__tx_free_memory_start); */
la t0, __tx_free_memory_start /* Pickup first free address */
la t0, __tx_free_memory_start // Pickup first free address
la t1, _tx_initialize_unused_memory
sd t0, 0(t1) /* Save unused memory address */
sd t0, 0(t1) // Save unused memory address
/* Initialize floating point control/status register if floating point is enabled. */
#ifdef __riscv_flen
li t0, 0
csrw fcsr, t0 /* Clear FP control/status register */
csrw fcsr, t0 // Clear FP control/status register
#endif
ret
@@ -93,23 +93,23 @@ _tx_initialize_low_level:
/* Timer Interrupt Handler Note:
Platform-specific implementations must provide their own timer ISR.
The timer interrupt handler should follow this execution flow:
1. Disable interrupts (if not done by hardware exception entry)
2. Allocate interrupt stack frame (65*8 bytes with FP, 32*8 bytes without)
3. Save RA (x1) on the stack at offset 28*8
4. Call _tx_thread_context_save to save thread context
5. Call _tx_timer_interrupt to process the timer tick
6. Call _tx_thread_context_restore to resume execution (does not return)
Example (for CLINT timer):
_tx_timer_interrupt_handler:
addi sp, sp, -32*8
sd ra, 28*8(sp)
addi sp, sp, -32*8
sd ra, 28*8(sp)
call _tx_thread_context_save
call _tx_timer_interrupt
j _tx_thread_context_restore
j _tx_thread_context_restore
The port assumes Machine mode (M-mode) execution.
For Supervisor mode (S-mode), use sstatus and SIE/SPIE instead of mstatus.
See the RISC-V Privileged Specification for more details. */
ports/risc-v64/gnu/src/tx_thread_context_restore.S
+170 -170
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -68,21 +68,21 @@ _tx_thread_context_restore:
/* Lockout interrupts. */
csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_exit /* Call the ISR execution exit function */
call _tx_execution_isr_exit // Call the ISR execution exit function
#endif
/* Determine if interrupts are nested. */
/* if (--_tx_thread_system_state)
{ */
la t0, _tx_thread_system_state /* Pickup addr of nested interrupt count */
ld t1, 0(t0) /* Pickup nested interrupt count */
addi t1, t1, -1 /* Decrement the nested interrupt counter */
sd t1, 0(t0) /* Store new nested count */
beqz t1, _tx_thread_not_nested_restore /* If 0, not nested restore */
la t0, _tx_thread_system_state // Pickup addr of nested interrupt count
ld t1, 0(t0) // Pickup nested interrupt count
addi t1, t1, -1 // Decrement the nested interrupt counter
sd t1, 0(t0) // Store new nested count
beqz t1, _tx_thread_not_nested_restore // If 0, not nested restore
/* Interrupts are nested. */
@@ -91,51 +91,51 @@ _tx_thread_context_restore:
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f0, 31*8(sp) /* Recover ft0 */
flw f1, 32*8(sp) /* Recover ft1 */
flw f2, 33*8(sp) /* Recover ft2 */
flw f3, 34*8(sp) /* Recover ft3 */
flw f4, 35*8(sp) /* Recover ft4 */
flw f5, 36*8(sp) /* Recover ft5 */
flw f6, 37*8(sp) /* Recover ft6 */
flw f7, 38*8(sp) /* Recover ft7 */
flw f10,41*8(sp) /* Recover fa0 */
flw f11,42*8(sp) /* Recover fa1 */
flw f12,43*8(sp) /* Recover fa2 */
flw f13,44*8(sp) /* Recover fa3 */
flw f14,45*8(sp) /* Recover fa4 */
flw f15,46*8(sp) /* Recover fa5 */
flw f16,47*8(sp) /* Recover fa6 */
flw f17,48*8(sp) /* Recover fa7 */
flw f28,59*8(sp) /* Recover ft8 */
flw f29,60*8(sp) /* Recover ft9 */
flw f30,61*8(sp) /* Recover ft10 */
flw f31,62*8(sp) /* Recover ft11 */
ld t0, 63*8(sp) /* Recover fcsr */
csrw fcsr, t0 /* Restore fcsr */
flw f0, 31*8(sp) // Recover ft0
flw f1, 32*8(sp) // Recover ft1
flw f2, 33*8(sp) // Recover ft2
flw f3, 34*8(sp) // Recover ft3
flw f4, 35*8(sp) // Recover ft4
flw f5, 36*8(sp) // Recover ft5
flw f6, 37*8(sp) // Recover ft6
flw f7, 38*8(sp) // Recover ft7
flw f10,41*8(sp) // Recover fa0
flw f11,42*8(sp) // Recover fa1
flw f12,43*8(sp) // Recover fa2
flw f13,44*8(sp) // Recover fa3
flw f14,45*8(sp) // Recover fa4
flw f15,46*8(sp) // Recover fa5
flw f16,47*8(sp) // Recover fa6
flw f17,48*8(sp) // Recover fa7
flw f28,59*8(sp) // Recover ft8
flw f29,60*8(sp) // Recover ft9
flw f30,61*8(sp) // Recover ft10
flw f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*8(sp) /* Recover ft0 */
fld f1, 32*8(sp) /* Recover ft1 */
fld f2, 33*8(sp) /* Recover ft2 */
fld f3, 34*8(sp) /* Recover ft3 */
fld f4, 35*8(sp) /* Recover ft4 */
fld f5, 36*8(sp) /* Recover ft5 */
fld f6, 37*8(sp) /* Recover ft6 */
fld f7, 38*8(sp) /* Recover ft7 */
fld f10,41*8(sp) /* Recover fa0 */
fld f11,42*8(sp) /* Recover fa1 */
fld f12,43*8(sp) /* Recover fa2 */
fld f13,44*8(sp) /* Recover fa3 */
fld f14,45*8(sp) /* Recover fa4 */
fld f15,46*8(sp) /* Recover fa5 */
fld f16,47*8(sp) /* Recover fa6 */
fld f17,48*8(sp) /* Recover fa7 */
fld f28,59*8(sp) /* Recover ft8 */
fld f29,60*8(sp) /* Recover ft9 */
fld f30,61*8(sp) /* Recover ft10 */
fld f31,62*8(sp) /* Recover ft11 */
ld t0, 63*8(sp) /* Recover fcsr */
csrw fcsr, t0
fld f0, 31*8(sp) // Recover ft0
fld f1, 32*8(sp) // Recover ft1
fld f2, 33*8(sp) // Recover ft2
fld f3, 34*8(sp) // Recover ft3
fld f4, 35*8(sp) // Recover ft4
fld f5, 36*8(sp) // Recover ft5
fld f6, 37*8(sp) // Recover ft6
fld f7, 38*8(sp) // Recover ft7
fld f10,41*8(sp) // Recover fa0
fld f11,42*8(sp) // Recover fa1
fld f12,43*8(sp) // Recover fa2
fld f13,44*8(sp) // Recover fa3
fld f14,45*8(sp) // Recover fa4
fld f15,46*8(sp) // Recover fa5
fld f16,47*8(sp) // Recover fa6
fld f17,48*8(sp) // Recover fa7
fld f28,59*8(sp) // Recover ft8
fld f29,60*8(sp) // Recover ft9
fld f30,61*8(sp) // Recover ft10
fld f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0
#endif
/* Recover standard registers. */
@@ -145,56 +145,56 @@ _tx_thread_context_restore:
Also skip the saved registers since they have been restored by any function we called,
except s0 since we use it ourselves. */
ld t0, 30*8(sp) /* Recover mepc */
csrw mepc, t0 /* Setup mepc */
ld t0, 30*8(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits.
Set MPIE and restore MPP to Machine, preserve other fields. */
csrr t1, mstatus
/* Clear MPP/MPIE/MIE bits in t1 then set desired values. */
li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */
li t3, 0x1800 /* Set MPP to Machine mode (bits 12:11) */
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1800 // Set MPP to Machine mode (bits 12:11)
/* Construct new mstatus in t1: clear mask bits, set MPP/MPIE and optionally FP bit,
preserve everything except the bits we will modify. */
li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 /* Set FS bits (bits 14:13 to 01) for FP state */
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 /* Update mstatus safely */
csrw mstatus, t1 // Update mstatus safely
ld ra, 28*8(sp) /* Recover return address */
ld t0, 19*8(sp) /* Recover t0 */
ld t1, 18*8(sp) /* Recover t1 */
ld t2, 17*8(sp) /* Recover t2 */
ld s0, 12*8(sp) /* Recover s0 */
ld a0, 27*8(sp) /* Recover a0 */
ld a1, 26*8(sp) /* Recover a1 */
ld a2, 25*8(sp) /* Recover a2 */
ld a3, 24*8(sp) /* Recover a3 */
ld a4, 23*8(sp) /* Recover a4 */
ld a5, 22*8(sp) /* Recover a5 */
ld a6, 21*8(sp) /* Recover a6 */
ld a7, 20*8(sp) /* Recover a7 */
ld t3, 16*8(sp) /* Recover t3 */
ld t4, 15*8(sp) /* Recover t4 */
ld t5, 14*8(sp) /* Recover t5 */
ld t6, 13*8(sp) /* Recover t6 */
ld ra, 28*8(sp) // Recover return address
ld t0, 19*8(sp) // Recover t0
ld t1, 18*8(sp) // Recover t1
ld t2, 17*8(sp) // Recover t2
ld s0, 12*8(sp) // Recover s0
ld a0, 27*8(sp) // Recover a0
ld a1, 26*8(sp) // Recover a1
ld a2, 25*8(sp) // Recover a2
ld a3, 24*8(sp) // Recover a3
ld a4, 23*8(sp) // Recover a4
ld a5, 22*8(sp) // Recover a5
ld a6, 21*8(sp) // Recover a6
ld a7, 20*8(sp) // Recover a7
ld t3, 16*8(sp) // Recover t3
ld t4, 15*8(sp) // Recover t4
ld t5, 14*8(sp) // Recover t5
ld t6, 13*8(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */
addi sp, sp, 65*8 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
#endif
mret /* Return to point of interrupt */
mret // Return to point of interrupt
/* } */
_tx_thread_not_nested_restore:
@@ -203,17 +203,17 @@ _tx_thread_not_nested_restore:
|| (_tx_thread_preempt_disable))
{ */
la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */
ld t1, 0(t0) /* Pickup current thread pointer */
beqz t1, _tx_thread_idle_system_restore /* If NULL, idle system restore */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
ld t1, 0(t0) // Pickup current thread pointer
beqz t1, _tx_thread_idle_system_restore // If NULL, idle system restore
la t0, _tx_thread_preempt_disable /* Pickup preempt disable flag address */
lw t2, 0(t0) /* Pickup preempt disable flag (UINT) */
bgtz t2, _tx_thread_no_preempt_restore /* If set, restore interrupted thread */
la t0, _tx_thread_preempt_disable // Pickup preempt disable flag address
lw t2, 0(t0) // Pickup preempt disable flag (UINT)
bgtz t2, _tx_thread_no_preempt_restore // If set, restore interrupted thread
la t0, _tx_thread_execute_ptr /* Pickup thread execute pointer address */
ld t2, 0(t0) /* Pickup thread execute pointer */
bne t1, t2, _tx_thread_preempt_restore /* If higher-priority thread is ready, preempt */
la t0, _tx_thread_execute_ptr // Pickup thread execute pointer address
ld t2, 0(t0) // Pickup thread execute pointer
bne t1, t2, _tx_thread_preempt_restore // If higher-priority thread is ready, preempt
_tx_thread_no_preempt_restore:
@@ -222,55 +222,55 @@ _tx_thread_no_preempt_restore:
/* Pickup the saved stack pointer. */
/* sp = _tx_thread_current_ptr -> tx_thread_stack_ptr; */
ld sp, 16(t1) /* Switch back to thread's stack */
ld sp, 16(t1) // Switch back to thread's stack
/* Recover floating point registers. */
#if defined(__riscv_float_abi_single)
flw f0, 31*8(sp) /* Recover ft0 */
flw f1, 32*8(sp) /* Recover ft1 */
flw f2, 33*8(sp) /* Recover ft2 */
flw f3, 34*8(sp) /* Recover ft3 */
flw f4, 35*8(sp) /* Recover ft4 */
flw f5, 36*8(sp) /* Recover ft5 */
flw f6, 37*8(sp) /* Recover ft6 */
flw f7, 38*8(sp) /* Recover ft7 */
flw f10,41*8(sp) /* Recover fa0 */
flw f11,42*8(sp) /* Recover fa1 */
flw f12,43*8(sp) /* Recover fa2 */
flw f13,44*8(sp) /* Recover fa3 */
flw f14,45*8(sp) /* Recover fa4 */
flw f15,46*8(sp) /* Recover fa5 */
flw f16,47*8(sp) /* Recover fa6 */
flw f17,48*8(sp) /* Recover fa7 */
flw f28,59*8(sp) /* Recover ft8 */
flw f29,60*8(sp) /* Recover ft9 */
flw f30,61*8(sp) /* Recover ft10 */
flw f31,62*8(sp) /* Recover ft11 */
ld t0, 63*8(sp) /* Recover fcsr */
csrw fcsr, t0 /* Restore fcsr */
flw f0, 31*8(sp) // Recover ft0
flw f1, 32*8(sp) // Recover ft1
flw f2, 33*8(sp) // Recover ft2
flw f3, 34*8(sp) // Recover ft3
flw f4, 35*8(sp) // Recover ft4
flw f5, 36*8(sp) // Recover ft5
flw f6, 37*8(sp) // Recover ft6
flw f7, 38*8(sp) // Recover ft7
flw f10,41*8(sp) // Recover fa0
flw f11,42*8(sp) // Recover fa1
flw f12,43*8(sp) // Recover fa2
flw f13,44*8(sp) // Recover fa3
flw f14,45*8(sp) // Recover fa4
flw f15,46*8(sp) // Recover fa5
flw f16,47*8(sp) // Recover fa6
flw f17,48*8(sp) // Recover fa7
flw f28,59*8(sp) // Recover ft8
flw f29,60*8(sp) // Recover ft9
flw f30,61*8(sp) // Recover ft10
flw f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*8(sp) /* Recover ft0 */
fld f1, 32*8(sp) /* Recover ft1 */
fld f2, 33*8(sp) /* Recover ft2 */
fld f3, 34*8(sp) /* Recover ft3 */
fld f4, 35*8(sp) /* Recover ft4 */
fld f5, 36*8(sp) /* Recover ft5 */
fld f6, 37*8(sp) /* Recover ft6 */
fld f7, 38*8(sp) /* Recover ft7 */
fld f10,41*8(sp) /* Recover fa0 */
fld f11,42*8(sp) /* Recover fa1 */
fld f12,43*8(sp) /* Recover fa2 */
fld f13,44*8(sp) /* Recover fa3 */
fld f14,45*8(sp) /* Recover fa4 */
fld f15,46*8(sp) /* Recover fa5 */
fld f16,47*8(sp) /* Recover fa6 */
fld f17,48*8(sp) /* Recover fa7 */
fld f28,59*8(sp) /* Recover ft8 */
fld f29,60*8(sp) /* Recover ft9 */
fld f30,61*8(sp) /* Recover ft10 */
fld f31,62*8(sp) /* Recover ft11 */
ld t0, 63*8(sp) /* Recover fcsr */
csrw fcsr, t0 /* Restore fcsr */
fld f0, 31*8(sp) // Recover ft0
fld f1, 32*8(sp) // Recover ft1
fld f2, 33*8(sp) // Recover ft2
fld f3, 34*8(sp) // Recover ft3
fld f4, 35*8(sp) // Recover ft4
fld f5, 36*8(sp) // Recover ft5
fld f6, 37*8(sp) // Recover ft6
fld f7, 38*8(sp) // Recover ft7
fld f10,41*8(sp) // Recover fa0
fld f11,42*8(sp) // Recover fa1
fld f12,43*8(sp) // Recover fa2
fld f13,44*8(sp) // Recover fa3
fld f14,45*8(sp) // Recover fa4
fld f15,46*8(sp) // Recover fa5
fld f16,47*8(sp) // Recover fa6
fld f17,48*8(sp) // Recover fa7
fld f28,59*8(sp) // Recover ft8
fld f29,60*8(sp) // Recover ft9
fld f30,61*8(sp) // Recover ft10
fld f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover the saved context and return to the point of interrupt. */
@@ -279,48 +279,48 @@ _tx_thread_no_preempt_restore:
/* Restore registers,
Skip global pointer because that does not change */
ld t0, 30*8(sp) /* Recover mepc */
csrw mepc, t0 /* Setup mepc */
ld t0, 30*8(sp) // Recover mepc
csrw mepc, t0 // Setup mepc
/* Compose mstatus via read/modify/write to avoid clobbering unrelated bits. */
csrr t1, mstatus
li t2, 0x1888 /* MPP(0x1800) | MPIE(0x80) | MIE(0x08) */
li t3, 0x1800 /* Set MPP to Machine mode */
li t4, ~0x1888 /* Clear mask for MPP/MPIE/MIE */
li t2, 0x1888 // MPP(0x1800) | MPIE(0x80) | MIE(0x08)
li t3, 0x1800 // Set MPP to Machine mode
li t4, ~0x1888 // Clear mask for MPP/MPIE/MIE
and t1, t1, t4
or t1, t1, t3
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t0, 0x2000 /* Set FS bits for FP state */
li t0, 0x2000 // Set FS bits for FP state
or t1, t1, t0
#endif
csrw mstatus, t1 /* Update mstatus safely */
csrw mstatus, t1 // Update mstatus safely
ld ra, 28*8(sp) /* Recover return address */
ld t0, 19*8(sp) /* Recover t0 */
ld t1, 18*8(sp) /* Recover t1 */
ld t2, 17*8(sp) /* Recover t2 */
ld s0, 12*8(sp) /* Recover s0 */
ld a0, 27*8(sp) /* Recover a0 */
ld a1, 26*8(sp) /* Recover a1 */
ld a2, 25*8(sp) /* Recover a2 */
ld a3, 24*8(sp) /* Recover a3 */
ld a4, 23*8(sp) /* Recover a4 */
ld a5, 22*8(sp) /* Recover a5 */
ld a6, 21*8(sp) /* Recover a6 */
ld a7, 20*8(sp) /* Recover a7 */
ld t3, 16*8(sp) /* Recover t3 */
ld t4, 15*8(sp) /* Recover t4 */
ld t5, 14*8(sp) /* Recover t5 */
ld t6, 13*8(sp) /* Recover t6 */
ld ra, 28*8(sp) // Recover return address
ld t0, 19*8(sp) // Recover t0
ld t1, 18*8(sp) // Recover t1
ld t2, 17*8(sp) // Recover t2
ld s0, 12*8(sp) // Recover s0
ld a0, 27*8(sp) // Recover a0
ld a1, 26*8(sp) // Recover a1
ld a2, 25*8(sp) // Recover a2
ld a3, 24*8(sp) // Recover a3
ld a4, 23*8(sp) // Recover a4
ld a5, 22*8(sp) // Recover a5
ld a6, 21*8(sp) // Recover a6
ld a7, 20*8(sp) // Recover a7
ld t3, 16*8(sp) // Recover t3
ld t4, 15*8(sp) // Recover t4
ld t5, 14*8(sp) // Recover t5
ld t6, 13*8(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*8 /* Recover stack frame - with floating point enabled */
addi sp, sp, 65*8 // Recover stack frame - with floating point enabled
#else
addi sp, sp, 32*8 /* Recover stack frame - without floating point enabled */
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
#endif
mret /* Return to point of interrupt */
mret // Return to point of interrupt
/* }
else
@@ -329,15 +329,15 @@ _tx_thread_preempt_restore:
/* Instead of directly activating the thread again, ensure we save the
entire stack frame by saving the remaining registers. */
ld t0, 16(t1) /* Pickup thread's stack pointer */
ori t3, zero, 1 /* Build interrupt stack type */
sd t3, 0(t0) /* Store stack type */
ld t0, 16(t1) // Pickup thread's stack pointer
ori t3, zero, 1 // Build interrupt stack type
sd t3, 0(t0) // Store stack type
/* Store floating point preserved registers. */
#ifdef __riscv_float_abi_single
fsw f8, 39*8(t0) /* Store fs0 */
fsw f9, 40*8(t0) /* Store fs1 */
fsw f18, 49*8(t0) /* Store fs2 */
fsw f8, 39*8(t0) // Store fs0
fsw f9, 40*8(t0) // Store fs1
fsw f18, 49*8(t0) // Store fs2
fsw f19, 50*8(t0) // Store fs3
fsw f20, 51*8(t0) // Store fs4
fsw f21, 52*8(t0) // Store fs5
ports/risc-v64/gnu/src/tx_thread_context_save.S
+139 -139
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -68,94 +68,94 @@ _tx_thread_context_save:
out and the interrupt stack frame has been allocated and ra has
been saved on the stack. */
sd t0, 19*8(sp) /* First store t0 and t1 */
sd t0, 19*8(sp) // First store t0 and t1
sd t1, 18*8(sp)
la t0, _tx_thread_system_state /* Pickup address of system state */
ld t1, 0(t0) /* Pickup system state */
la t0, _tx_thread_system_state // Pickup address of system state
ld t1, 0(t0) // Pickup system state
/* Check for a nested interrupt condition. */
/* if (_tx_thread_system_state++)
{ */
beqz t1, _tx_thread_not_nested_save /* If 0, first interrupt condition */
addi t1, t1, 1 /* Increment the interrupt counter */
sd t1, 0(t0) /* Store the interrupt counter */
beqz t1, _tx_thread_not_nested_save // If 0, first interrupt condition
addi t1, t1, 1 // Increment the interrupt counter
sd t1, 0(t0) // Store the interrupt counter
/* Nested interrupt condition.
Save the rest of the scratch registers on the stack and return to the
calling ISR. */
sd t2, 17*8(sp) /* Store t2 */
sd s0, 12*8(sp) /* Store s0 */
sd a0, 27*8(sp) /* Store a0 */
sd a1, 26*8(sp) /* Store a1 */
sd a2, 25*8(sp) /* Store a2 */
sd a3, 24*8(sp) /* Store a3 */
sd a4, 23*8(sp) /* Store a4 */
sd a5, 22*8(sp) /* Store a5 */
sd a6, 21*8(sp) /* Store a6 */
sd a7, 20*8(sp) /* Store a7 */
sd t3, 16*8(sp) /* Store t3 */
sd t4, 15*8(sp) /* Store t4 */
sd t5, 14*8(sp) /* Store t5 */
sd t6, 13*8(sp) /* Store t6 */
csrr t0, mepc /* Load exception program counter */
sd t0, 30*8(sp) /* Save it on the stack */
sd t2, 17*8(sp) // Store t2
sd s0, 12*8(sp) // Store s0
sd a0, 27*8(sp) // Store a0
sd a1, 26*8(sp) // Store a1
sd a2, 25*8(sp) // Store a2
sd a3, 24*8(sp) // Store a3
sd a4, 23*8(sp) // Store a4
sd a5, 22*8(sp) // Store a5
sd a6, 21*8(sp) // Store a6
sd a7, 20*8(sp) // Store a7
sd t3, 16*8(sp) // Store t3
sd t4, 15*8(sp) // Store t4
sd t5, 14*8(sp) // Store t5
sd t6, 13*8(sp) // Store t6
csrr t0, mepc // Load exception program counter
sd t0, 30*8(sp) // Save it on the stack
/* Save floating point scratch registers if floating point is enabled. */
#ifdef __riscv_float_abi_single
fsw f0, 31*8(sp) /* Store ft0 */
fsw f1, 32*8(sp) /* Store ft1 */
fsw f2, 33*8(sp) /* Store ft2 */
fsw f3, 34*8(sp) /* Store ft3 */
fsw f4, 35*8(sp) /* Store ft4 */
fsw f5, 36*8(sp) /* Store ft5 */
fsw f6, 37*8(sp) /* Store ft6 */
fsw f7, 38*8(sp) /* Store ft7 */
fsw f10,41*8(sp) /* Store fa0 */
fsw f11,42*8(sp) /* Store fa1 */
fsw f12,43*8(sp) /* Store fa2 */
fsw f13,44*8(sp) /* Store fa3 */
fsw f14,45*8(sp) /* Store fa4 */
fsw f15,46*8(sp) /* Store fa5 */
fsw f16,47*8(sp) /* Store fa6 */
fsw f17,48*8(sp) /* Store fa7 */
fsw f28,59*8(sp) /* Store ft8 */
fsw f29,60*8(sp) /* Store ft9 */
fsw f30,61*8(sp) /* Store ft10 */
fsw f31,62*8(sp) /* Store ft11 */
fsw f0, 31*8(sp) // Store ft0
fsw f1, 32*8(sp) // Store ft1
fsw f2, 33*8(sp) // Store ft2
fsw f3, 34*8(sp) // Store ft3
fsw f4, 35*8(sp) // Store ft4
fsw f5, 36*8(sp) // Store ft5
fsw f6, 37*8(sp) // Store ft6
fsw f7, 38*8(sp) // Store ft7
fsw f10,41*8(sp) // Store fa0
fsw f11,42*8(sp) // Store fa1
fsw f12,43*8(sp) // Store fa2
fsw f13,44*8(sp) // Store fa3
fsw f14,45*8(sp) // Store fa4
fsw f15,46*8(sp) // Store fa5
fsw f16,47*8(sp) // Store fa6
fsw f17,48*8(sp) // Store fa7
fsw f28,59*8(sp) // Store ft8
fsw f29,60*8(sp) // Store ft9
fsw f30,61*8(sp) // Store ft10
fsw f31,62*8(sp) // Store ft11
csrr t0, fcsr
sd t0, 63*8(sp) /* Store fcsr */
sd t0, 63*8(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f0, 31*8(sp) /* Store ft0 */
fsd f1, 32*8(sp) /* Store ft1 */
fsd f2, 33*8(sp) /* Store ft2 */
fsd f3, 34*8(sp) /* Store ft3 */
fsd f4, 35*8(sp) /* Store ft4 */
fsd f5, 36*8(sp) /* Store ft5 */
fsd f6, 37*8(sp) /* Store ft6 */
fsd f7, 38*8(sp) /* Store ft7 */
fsd f10,41*8(sp) /* Store fa0 */
fsd f11,42*8(sp) /* Store fa1 */
fsd f12,43*8(sp) /* Store fa2 */
fsd f13,44*8(sp) /* Store fa3 */
fsd f14,45*8(sp) /* Store fa4 */
fsd f15,46*8(sp) /* Store fa5 */
fsd f16,47*8(sp) /* Store fa6 */
fsd f17,48*8(sp) /* Store fa7 */
fsd f28,59*8(sp) /* Store ft8 */
fsd f29,60*8(sp) /* Store ft9 */
fsd f30,61*8(sp) /* Store ft10 */
fsd f31,62*8(sp) /* Store ft11 */
fsd f0, 31*8(sp) // Store ft0
fsd f1, 32*8(sp) // Store ft1
fsd f2, 33*8(sp) // Store ft2
fsd f3, 34*8(sp) // Store ft3
fsd f4, 35*8(sp) // Store ft4
fsd f5, 36*8(sp) // Store ft5
fsd f6, 37*8(sp) // Store ft6
fsd f7, 38*8(sp) // Store ft7
fsd f10,41*8(sp) // Store fa0
fsd f11,42*8(sp) // Store fa1
fsd f12,43*8(sp) // Store fa2
fsd f13,44*8(sp) // Store fa3
fsd f14,45*8(sp) // Store fa4
fsd f15,46*8(sp) // Store fa5
fsd f16,47*8(sp) // Store fa6
fsd f17,48*8(sp) // Store fa7
fsd f28,59*8(sp) // Store ft8
fsd f29,60*8(sp) // Store ft9
fsd f30,61*8(sp) // Store ft10
fsd f31,62*8(sp) // Store ft11
csrr t0, fcsr
sd t0, 63*8(sp) /* Store fcsr */
sd t0, 63*8(sp) // Store fcsr
#endif
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_isr_enter /* Call the ISR execution enter function */
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
ret /* Return to calling ISR */
ret // Return to calling ISR
_tx_thread_not_nested_save:
/* } */
@@ -163,82 +163,82 @@ _tx_thread_not_nested_save:
/* Otherwise, not nested, check to see if a thread was running. */
/* else if (_tx_thread_current_ptr)
{ */
addi t1, t1, 1 /* Increment the interrupt counter */
sd t1, 0(t0) /* Store the interrupt counter */
addi t1, t1, 1 // Increment the interrupt counter
sd t1, 0(t0) // Store the interrupt counter
/* Not nested: Find the user thread that was running and load our SP */
la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */
ld t0, 0(t0) /* Pickup current thread pointer */
beqz t0, _tx_thread_idle_system_save /* If NULL, idle system was interrupted */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
ld t0, 0(t0) // Pickup current thread pointer
beqz t0, _tx_thread_idle_system_save // If NULL, idle system was interrupted
/* Save the standard scratch registers. */
sd t2, 17*8(sp) /* Store t2 */
sd s0, 12*8(sp) /* Store s0 */
sd a0, 27*8(sp) /* Store a0 */
sd a1, 26*8(sp) /* Store a1 */
sd a2, 25*8(sp) /* Store a2 */
sd a3, 24*8(sp) /* Store a3 */
sd a4, 23*8(sp) /* Store a4 */
sd a5, 22*8(sp) /* Store a5 */
sd a6, 21*8(sp) /* Store a6 */
sd a7, 20*8(sp) /* Store a7 */
sd t3, 16*8(sp) /* Store t3 */
sd t4, 15*8(sp) /* Store t4 */
sd t5, 14*8(sp) /* Store t5 */
sd t6, 13*8(sp) /* Store t6 */
sd t2, 17*8(sp) // Store t2
sd s0, 12*8(sp) // Store s0
sd a0, 27*8(sp) // Store a0
sd a1, 26*8(sp) // Store a1
sd a2, 25*8(sp) // Store a2
sd a3, 24*8(sp) // Store a3
sd a4, 23*8(sp) // Store a4
sd a5, 22*8(sp) // Store a5
sd a6, 21*8(sp) // Store a6
sd a7, 20*8(sp) // Store a7
sd t3, 16*8(sp) // Store t3
sd t4, 15*8(sp) // Store t4
sd t5, 14*8(sp) // Store t5
sd t6, 13*8(sp) // Store t6
csrr t1, mepc /* Load exception program counter */
sd t1, 30*8(sp) /* Save it on the stack */
csrr t1, mepc // Load exception program counter
sd t1, 30*8(sp) // Save it on the stack
/* Save floating point scratch registers if floating point is enabled. */
#ifdef __riscv_float_abi_single
fsw f0, 31*8(sp) /* Store ft0 */
fsw f1, 32*8(sp) /* Store ft1 */
fsw f2, 33*8(sp) /* Store ft2 */
fsw f3, 34*8(sp) /* Store ft3 */
fsw f4, 35*8(sp) /* Store ft4 */
fsw f5, 36*8(sp) /* Store ft5 */
fsw f6, 37*8(sp) /* Store ft6 */
fsw f7, 38*8(sp) /* Store ft7 */
fsw f10,41*8(sp) /* Store fa0 */
fsw f11,42*8(sp) /* Store fa1 */
fsw f12,43*8(sp) /* Store fa2 */
fsw f13,44*8(sp) /* Store fa3 */
fsw f14,45*8(sp) /* Store fa4 */
fsw f15,46*8(sp) /* Store fa5 */
fsw f16,47*8(sp) /* Store fa6 */
fsw f17,48*8(sp) /* Store fa7 */
fsw f28,59*8(sp) /* Store ft8 */
fsw f29,60*8(sp) /* Store ft9 */
fsw f30,61*8(sp) /* Store ft10 */
fsw f31,62*8(sp) /* Store ft11 */
fsw f0, 31*8(sp) // Store ft0
fsw f1, 32*8(sp) // Store ft1
fsw f2, 33*8(sp) // Store ft2
fsw f3, 34*8(sp) // Store ft3
fsw f4, 35*8(sp) // Store ft4
fsw f5, 36*8(sp) // Store ft5
fsw f6, 37*8(sp) // Store ft6
fsw f7, 38*8(sp) // Store ft7
fsw f10,41*8(sp) // Store fa0
fsw f11,42*8(sp) // Store fa1
fsw f12,43*8(sp) // Store fa2
fsw f13,44*8(sp) // Store fa3
fsw f14,45*8(sp) // Store fa4
fsw f15,46*8(sp) // Store fa5
fsw f16,47*8(sp) // Store fa6
fsw f17,48*8(sp) // Store fa7
fsw f28,59*8(sp) // Store ft8
fsw f29,60*8(sp) // Store ft9
fsw f30,61*8(sp) // Store ft10
fsw f31,62*8(sp) // Store ft11
csrr t0, fcsr
sd t0, 63*8(sp) /* Store fcsr */
sd t0, 63*8(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f0, 31*8(sp) /* Store ft0 */
fsd f1, 32*8(sp) /* Store ft1 */
fsd f2, 33*8(sp) /* Store ft2 */
fsd f3, 34*8(sp) /* Store ft3 */
fsd f4, 35*8(sp) /* Store ft4 */
fsd f5, 36*8(sp) /* Store ft5 */
fsd f6, 37*8(sp) /* Store ft6 */
fsd f7, 38*8(sp) /* Store ft7 */
fsd f10,41*8(sp) /* Store fa0 */
fsd f11,42*8(sp) /* Store fa1 */
fsd f12,43*8(sp) /* Store fa2 */
fsd f13,44*8(sp) /* Store fa3 */
fsd f14,45*8(sp) /* Store fa4 */
fsd f15,46*8(sp) /* Store fa5 */
fsd f16,47*8(sp) /* Store fa6 */
fsd f17,48*8(sp) /* Store fa7 */
fsd f28,59*8(sp) /* Store ft8 */
fsd f29,60*8(sp) /* Store ft9 */
fsd f30,61*8(sp) /* Store ft10 */
fsd f31,62*8(sp) /* Store ft11 */
fsd f0, 31*8(sp) // Store ft0
fsd f1, 32*8(sp) // Store ft1
fsd f2, 33*8(sp) // Store ft2
fsd f3, 34*8(sp) // Store ft3
fsd f4, 35*8(sp) // Store ft4
fsd f5, 36*8(sp) // Store ft5
fsd f6, 37*8(sp) // Store ft6
fsd f7, 38*8(sp) // Store ft7
fsd f10,41*8(sp) // Store fa0
fsd f11,42*8(sp) // Store fa1
fsd f12,43*8(sp) // Store fa2
fsd f13,44*8(sp) // Store fa3
fsd f14,45*8(sp) // Store fa4
fsd f15,46*8(sp) // Store fa5
fsd f16,47*8(sp) // Store fa6
fsd f17,48*8(sp) // Store fa7
fsd f28,59*8(sp) // Store ft8
fsd f29,60*8(sp) // Store ft9
fsd f30,61*8(sp) // Store ft10
fsd f31,62*8(sp) // Store ft11
csrr t0, fcsr
sd t0, 63*8(sp) /* Store fcsr */
sd t0, 63*8(sp) // Store fcsr
#endif
/* Save the current stack pointer in the thread's control block. */
@@ -247,18 +247,18 @@ _tx_thread_not_nested_save:
/* Switch to the system stack. */
/* sp = _tx_thread_system_stack_ptr; */
la t1, _tx_thread_current_ptr /* Pickup current thread pointer address */
ld t1, 0(t1) /* Pickup current thread pointer */
sd sp, 16(t1) /* Save stack pointer */
la t1, _tx_thread_current_ptr // Pickup current thread pointer address
ld t1, 0(t1) // Pickup current thread pointer
sd sp, 16(t1) // Save stack pointer
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
/* _tx_execution_isr_enter is called with thread stack pointer */
call _tx_execution_isr_enter /* Call the ISR execution enter function */
call _tx_execution_isr_enter // Call the ISR execution enter function
#endif
la t0, _tx_thread_system_stack_ptr /* Pickup system stack pointer address */
ld sp, 0(t0) /* Switch to system stack */
ret /* Return to calling ISR */
la t0, _tx_thread_system_stack_ptr // Pickup system stack pointer address
ld sp, 0(t0) // Switch to system stack
ret // Return to calling ISR
sd x17, 20*8(sp) // Store a7
sd x28, 16*8(sp) // Store t3
ports/risc-v64/gnu/src/tx_thread_interrupt_control.S
+10 -10
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -67,17 +67,17 @@ _tx_thread_interrupt_control:
/* old_mstatus = mstatus; */
csrr t0, mstatus
mv t1, t0 /* Save original mstatus for return */
mv t1, t0 // Save original mstatus for return
/* Apply the new interrupt posture while preserving unrelated mstatus bits. */
/* Only modify the MIE bit (bit 3) */
/* mstatus = (mstatus & ~MIE) | (new_posture & MIE); */
li t2, ~0x08 /* Build mask to clear MIE */
and t0, t0, t2 /* Clear MIE bit */
and a0, a0, 0x08 /* Mask incoming to only MIE bit */
or t0, t0, a0 /* Set requested MIE state */
li t2, ~0x08 // Build mask to clear MIE
and t0, t0, t2 // Clear MIE bit
and a0, a0, 0x08 // Mask incoming to only MIE bit
or t0, t0, a0 // Set requested MIE state
csrw mstatus, t0
andi a0, t1, 0x08 /* Return original MIE bit */
andi a0, t1, 0x08 // Return original MIE bit
ret
/* } */
ports/risc-v64/gnu/src/tx_thread_schedule.S
+105 -105
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -67,16 +67,16 @@
_tx_thread_schedule:
/* Enable interrupts. */
csrsi mstatus, 0x08 /* Enable interrupts (MIE bit 3) */
csrsi mstatus, 0x08 // Enable interrupts (MIE bit 3)
/* Wait for a thread to execute. */
/* do
{ */
la t0, _tx_thread_execute_ptr /* Pickup address of execute ptr */
la t0, _tx_thread_execute_ptr // Pickup address of execute ptr
_tx_thread_schedule_loop:
ld t1, 0(t0) /* Pickup next thread to execute */
ld t1, 0(t0) // Pickup next thread to execute
/* TX_USE_WFI_IDLE Configuration:
When defined, the scheduler enters WFI (Wait-For-Interrupt) mode when
no threads are ready, reducing power consumption. The core will wake
@@ -89,9 +89,9 @@ _tx_thread_schedule_loop:
1: wfi
j _tx_thread_schedule_loop
2:
beqz t1, _tx_thread_schedule_loop /* Fallback: If still NULL, loop */
beqz t1, _tx_thread_schedule_loop // Fallback: If still NULL, loop
#else
beqz t1, _tx_thread_schedule_loop /* If NULL, wait for thread to execute */
beqz t1, _tx_thread_schedule_loop // If NULL, wait for thread to execute
#endif
/* }
@@ -99,81 +99,81 @@ _tx_thread_schedule_loop:
/* Yes! We have a thread to execute. Lockout interrupts and
transfer control to it. */
csrci mstatus, 0x08 /* Lockout interrupts */
csrci mstatus, 0x08 // Lockout interrupts
/* Setup the current thread pointer. */
/* _tx_thread_current_ptr = _tx_thread_execute_ptr; */
la t0, _tx_thread_current_ptr /* Pickup current thread pointer address */
sd t1, 0(t0) /* Set current thread pointer */
la t0, _tx_thread_current_ptr // Pickup current thread pointer address
sd t1, 0(t0) // Set current thread pointer
/* Increment the run count for this thread. */
/* _tx_thread_current_ptr -> tx_thread_run_count++; */
ld t2, 8(t1) /* Pickup run count */
ld t3, 48(t1) /* Pickup time slice value */
addi t2, t2, 1 /* Increment run count */
sd t2, 8(t1) /* Store new run count */
ld t2, 8(t1) // Pickup run count
ld t3, 48(t1) // Pickup time slice value
addi t2, t2, 1 // Increment run count
sd t2, 8(t1) // Store new run count
/* Setup time-slice, if present. */
/* _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice; */
la t2, _tx_timer_time_slice /* Pickup time-slice variable address */
la t2, _tx_timer_time_slice // Pickup time-slice variable address
/* Switch to the thread's stack. */
/* SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr; */
ld sp, 16(t1) /* Switch to thread's stack */
sd t3, 0(t2) /* Store new time-slice*/
ld sp, 16(t1) // Switch to thread's stack
sd t3, 0(t2) // Store new time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_thread_enter /* Call the thread execution enter function */
call _tx_execution_thread_enter // Call the thread execution enter function
#endif
/* Determine if an interrupt frame or a synchronous task suspension frame
is present. */
ld t2, 0(sp) /* Pickup stack type */
beqz t2, _tx_thread_synch_return /* If 0, solicited thread return */
ld t2, 0(sp) // Pickup stack type
beqz t2, _tx_thread_synch_return // If 0, solicited thread return
/* Determine if floating point registers need to be recovered. */
#if defined(__riscv_float_abi_single)
flw f0, 31*8(sp) /* Recover ft0 */
flw f1, 32*8(sp) /* Recover ft1 */
flw f2, 33*8(sp) /* Recover ft2 */
flw f3, 34*8(sp) /* Recover ft3 */
flw f4, 35*8(sp) /* Recover ft4 */
flw f5, 36*8(sp) /* Recover ft5 */
flw f6, 37*8(sp) /* Recover ft6 */
flw f7, 38*8(sp) /* Recover ft7 */
flw f8, 39*8(sp) /* Recover fs0 */
flw f9, 40*8(sp) /* Recover fs1 */
flw f10,41*8(sp) /* Recover fa0 */
flw f11,42*8(sp) /* Recover fa1 */
flw f12,43*8(sp) /* Recover fa2 */
flw f13,44*8(sp) /* Recover fa3 */
flw f14,45*8(sp) /* Recover fa4 */
flw f15,46*8(sp) /* Recover fa5 */
flw f16,47*8(sp) /* Recover fa6 */
flw f17,48*8(sp) /* Recover fa7 */
flw f18,49*8(sp) /* Recover fs2 */
flw f19,50*8(sp) /* Recover fs3 */
flw f20,51*8(sp) /* Recover fs4 */
flw f21,52*8(sp) /* Recover fs5 */
flw f22,53*8(sp) /* Recover fs6 */
flw f23,54*8(sp) /* Recover fs7 */
flw f24,55*8(sp) /* Recover fs8 */
flw f25,56*8(sp) /* Recover fs9 */
flw f26,57*8(sp) /* Recover fs10 */
flw f27,58*8(sp) /* Recover fs11 */
flw f28,59*8(sp) /* Recover ft8 */
flw f29,60*8(sp) /* Recover ft9 */
flw f30,61*8(sp) /* Recover ft10 */
flw f31,62*8(sp) /* Recover ft11 */
ld t0, 63*8(sp) /* Recover fcsr */
csrw fcsr, t0 /* Restore fcsr */
flw f0, 31*8(sp) // Recover ft0
flw f1, 32*8(sp) // Recover ft1
flw f2, 33*8(sp) // Recover ft2
flw f3, 34*8(sp) // Recover ft3
flw f4, 35*8(sp) // Recover ft4
flw f5, 36*8(sp) // Recover ft5
flw f6, 37*8(sp) // Recover ft6
flw f7, 38*8(sp) // Recover ft7
flw f8, 39*8(sp) // Recover fs0
flw f9, 40*8(sp) // Recover fs1
flw f10,41*8(sp) // Recover fa0
flw f11,42*8(sp) // Recover fa1
flw f12,43*8(sp) // Recover fa2
flw f13,44*8(sp) // Recover fa3
flw f14,45*8(sp) // Recover fa4
flw f15,46*8(sp) // Recover fa5
flw f16,47*8(sp) // Recover fa6
flw f17,48*8(sp) // Recover fa7
flw f18,49*8(sp) // Recover fs2
flw f19,50*8(sp) // Recover fs3
flw f20,51*8(sp) // Recover fs4
flw f21,52*8(sp) // Recover fs5
flw f22,53*8(sp) // Recover fs6
flw f23,54*8(sp) // Recover fs7
flw f24,55*8(sp) // Recover fs8
flw f25,56*8(sp) // Recover fs9
flw f26,57*8(sp) // Recover fs10
flw f27,58*8(sp) // Recover fs11
flw f28,59*8(sp) // Recover ft8
flw f29,60*8(sp) // Recover ft9
flw f30,61*8(sp) // Recover ft10
flw f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0 // Restore fcsr
#elif defined(__riscv_float_abi_double)
fld f0, 31*8(sp) // Recover ft0
fld f1, 32*8(sp) // Recover ft1
@@ -208,48 +208,48 @@ _tx_thread_schedule_loop:
fld f30,61*8(sp) // Recover ft10
fld f31,62*8(sp) // Recover ft11
ld t0, 63*8(sp) // Recover fcsr
csrw fcsr, t0 //
csrw fcsr, t0 // Restore fcsr
#endif
/* Recover standard registers. */
ld t0, 30*8(sp) /* Recover mepc */
csrw mepc, t0 /* Store mepc */
li t0, 0x1880 /* Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80) */
ld t0, 30*8(sp) // Recover mepc
csrw mepc, t0 // Store mepc
li t0, 0x1880 // Prepare mstatus: MPP=Machine(0x1800) | MPIE(0x80)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
li t1, 0x2000 /* Set FS bits for FP state */
li t1, 0x2000 // Set FS bits for FP state
or t0, t0, t1
#endif
csrw mstatus, t0 /* Set mstatus */
csrw mstatus, t0 // Set mstatus
ld ra, 28*8(sp) /* Recover return address */
ld t0, 19*8(sp) /* Recover t0 */
ld t1, 18*8(sp) /* Recover t1 */
ld t2, 17*8(sp) /* Recover t2 */
ld s0, 12*8(sp) /* Recover s0 */
ld s1, 11*8(sp) /* Recover s1 */
ld a0, 27*8(sp) /* Recover a0 */
ld a1, 26*8(sp) /* Recover a1 */
ld a2, 25*8(sp) /* Recover a2 */
ld a3, 24*8(sp) /* Recover a3 */
ld a4, 23*8(sp) /* Recover a4 */
ld a5, 22*8(sp) /* Recover a5 */
ld a6, 21*8(sp) /* Recover a6 */
ld a7, 20*8(sp) /* Recover a7 */
ld s2, 10*8(sp) /* Recover s2 */
ld s3, 9*8(sp) /* Recover s3 */
ld s4, 8*8(sp) /* Recover s4 */
ld s5, 7*8(sp) /* Recover s5 */
ld s6, 6*8(sp) /* Recover s6 */
ld s7, 5*8(sp) /* Recover s7 */
ld s8, 4*8(sp) /* Recover s8 */
ld s9, 3*8(sp) /* Recover s9 */
ld s10, 2*8(sp) /* Recover s10 */
ld s11, 1*8(sp) /* Recover s11 */
ld t3, 16*8(sp) /* Recover t3 */
ld t4, 15*8(sp) /* Recover t4 */
ld t5, 14*8(sp) /* Recover t5 */
ld t6, 13*8(sp) /* Recover t6 */
ld ra, 28*8(sp) // Recover return address
ld t0, 19*8(sp) // Recover t0
ld t1, 18*8(sp) // Recover t1
ld t2, 17*8(sp) // Recover t2
ld s0, 12*8(sp) // Recover s0
ld s1, 11*8(sp) // Recover s1
ld a0, 27*8(sp) // Recover a0
ld a1, 26*8(sp) // Recover a1
ld a2, 25*8(sp) // Recover a2
ld a3, 24*8(sp) // Recover a3
ld a4, 23*8(sp) // Recover a4
ld a5, 22*8(sp) // Recover a5
ld a6, 21*8(sp) // Recover a6
ld a7, 20*8(sp) // Recover a7
ld s2, 10*8(sp) // Recover s2
ld s3, 9*8(sp) // Recover s3
ld s4, 8*8(sp) // Recover s4
ld s5, 7*8(sp) // Recover s5
ld s6, 6*8(sp) // Recover s6
ld s7, 5*8(sp) // Recover s7
ld s8, 4*8(sp) // Recover s8
ld s9, 3*8(sp) // Recover s9
ld s10, 2*8(sp) // Recover s10
ld s11, 1*8(sp) // Recover s11
ld t3, 16*8(sp) // Recover t3
ld t4, 15*8(sp) // Recover t4
ld t5, 14*8(sp) // Recover t5
ld t6, 13*8(sp) // Recover t6
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 65*8 // Recover stack frame - with floating point registers
@@ -295,21 +295,21 @@ _tx_thread_synch_return:
/* Recover standard preserved registers. */
/* Recover standard registers. */
ld ra, 13*8(sp) /* Recover RA */
ld s0, 12*8(sp) /* Recover s0 */
ld s1, 11*8(sp) /* Recover s1 */
ld s2, 10*8(sp) /* Recover s2 */
ld s3, 9*8(sp) /* Recover s3 */
ld s4, 8*8(sp) /* Recover s4 */
ld s5, 7*8(sp) /* Recover s5 */
ld s6, 6*8(sp) /* Recover s6 */
ld s7, 5*8(sp) /* Recover s7 */
ld s8, 4*8(sp) /* Recover s8 */
ld s9, 3*8(sp) /* Recover s9 */
ld s10, 2*8(sp) /* Recover s10 */
ld s11, 1*8(sp) /* Recover s11 */
ld t0, 14*8(sp) /* Recover mstatus */
csrw mstatus, t0 /* Store mstatus, enables interrupt */
ld ra, 13*8(sp) // Recover RA
ld s0, 12*8(sp) // Recover s0
ld s1, 11*8(sp) // Recover s1
ld s2, 10*8(sp) // Recover s2
ld s3, 9*8(sp) // Recover s3
ld s4, 8*8(sp) // Recover s4
ld s5, 7*8(sp) // Recover s5
ld s6, 6*8(sp) // Recover s6
ld s7, 5*8(sp) // Recover s7
ld s8, 4*8(sp) // Recover s8
ld s9, 3*8(sp) // Recover s9
ld s10, 2*8(sp) // Recover s10
ld s11, 1*8(sp) // Recover s11
ld t0, 14*8(sp) // Recover mstatus
csrw mstatus, t0 // Store mstatus, enables interrupt
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, 29*8 // Recover stack frame
#else
ports/risc-v64/gnu/src/tx_thread_stack_build.S
+76 -76
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -136,91 +136,91 @@ If floating point support:
Stack Bottom: (higher memory address) */
ld t0, 32(a0) /* Pickup end of stack area */
li t1, ~15 /* Build 16-byte alignment mask */
and t0, t0, t1 /* Make sure 16-byte alignment */
ld t0, 32(a0) // Pickup end of stack area
li t1, ~15 // Build 16-byte alignment mask
and t0, t0, t1 // Make sure 16-byte alignment
/* Actually build the stack frame. */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi t0, t0, -65*8
#else
addi t0, t0, -32*8 /* Allocate space for the stack frame */
addi t0, t0, -32*8 // Allocate space for the stack frame
#endif
li t1, 1 /* Build stack type */
sd t1, 0*8(t0) /* Place stack type on the top */
sd zero, 1*8(t0) /* Initial s11 */
sd zero, 2*8(t0) /* Initial s10 */
sd zero, 3*8(t0) /* Initial s9 */
sd zero, 4*8(t0) /* Initial s8 */
sd zero, 5*8(t0) /* Initial s7 */
sd zero, 6*8(t0) /* Initial s6 */
sd zero, 7*8(t0) /* Initial s5 */
sd zero, 8*8(t0) /* Initial s4 */
sd zero, 9*8(t0) /* Initial s3 */
sd zero, 10*8(t0) /* Initial s2 */
sd zero, 11*8(t0) /* Initial s1 */
sd zero, 12*8(t0) /* Initial s0 */
sd zero, 13*8(t0) /* Initial t6 */
sd zero, 14*8(t0) /* Initial t5 */
sd zero, 15*8(t0) /* Initial t4 */
sd zero, 16*8(t0) /* Initial t3 */
sd zero, 17*8(t0) /* Initial t2 */
sd zero, 18*8(t0) /* Initial t1 */
sd zero, 19*8(t0) /* Initial t0 */
sd zero, 20*8(t0) /* Initial a7 */
sd zero, 21*8(t0) /* Initial a6 */
sd zero, 22*8(t0) /* Initial a5 */
sd zero, 23*8(t0) /* Initial a4 */
sd zero, 24*8(t0) /* Initial a3 */
sd zero, 25*8(t0) /* Initial a2 */
sd zero, 26*8(t0) /* Initial a1 */
sd zero, 27*8(t0) /* Initial a0 */
sd zero, 28*8(t0) /* Initial ra */
sd a1, 30*8(t0) /* Initial mepc (thread entry point) */
li t1, 1 // Build stack type
sd t1, 0*8(t0) // Place stack type on the top
sd zero, 1*8(t0) // Initial s11
sd zero, 2*8(t0) // Initial s10
sd zero, 3*8(t0) // Initial s9
sd zero, 4*8(t0) // Initial s8
sd zero, 5*8(t0) // Initial s7
sd zero, 6*8(t0) // Initial s6
sd zero, 7*8(t0) // Initial s5
sd zero, 8*8(t0) // Initial s4
sd zero, 9*8(t0) // Initial s3
sd zero, 10*8(t0) // Initial s2
sd zero, 11*8(t0) // Initial s1
sd zero, 12*8(t0) // Initial s0
sd zero, 13*8(t0) // Initial t6
sd zero, 14*8(t0) // Initial t5
sd zero, 15*8(t0) // Initial t4
sd zero, 16*8(t0) // Initial t3
sd zero, 17*8(t0) // Initial t2
sd zero, 18*8(t0) // Initial t1
sd zero, 19*8(t0) // Initial t0
sd zero, 20*8(t0) // Initial a7
sd zero, 21*8(t0) // Initial a6
sd zero, 22*8(t0) // Initial a5
sd zero, 23*8(t0) // Initial a4
sd zero, 24*8(t0) // Initial a3
sd zero, 25*8(t0) // Initial a2
sd zero, 26*8(t0) // Initial a1
sd zero, 27*8(t0) // Initial a0
sd zero, 28*8(t0) // Initial ra
sd a1, 30*8(t0) // Initial mepc (thread entry point)
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
sd zero, 31*8(t0) /* Initial ft0 */
sd zero, 32*8(t0) /* Initial ft1 */
sd zero, 33*8(t0) /* Initial ft2 */
sd zero, 34*8(t0) /* Initial ft3 */
sd zero, 35*8(t0) /* Initial ft4 */
sd zero, 36*8(t0) /* Initial ft5 */
sd zero, 37*8(t0) /* Initial ft6 */
sd zero, 38*8(t0) /* Initial ft7 */
sd zero, 39*8(t0) /* Initial fs0 */
sd zero, 40*8(t0) /* Initial fs1 */
sd zero, 41*8(t0) /* Initial fa0 */
sd zero, 42*8(t0) /* Initial fa1 */
sd zero, 43*8(t0) /* Initial fa2 */
sd zero, 44*8(t0) /* Initial fa3 */
sd zero, 45*8(t0) /* Initial fa4 */
sd zero, 46*8(t0) /* Initial fa5 */
sd zero, 47*8(t0) /* Initial fa6 */
sd zero, 48*8(t0) /* Initial fa7 */
sd zero, 49*8(t0) /* Initial fs2 */
sd zero, 50*8(t0) /* Initial fs3 */
sd zero, 51*8(t0) /* Initial fs4 */
sd zero, 52*8(t0) /* Initial fs5 */
sd zero, 53*8(t0) /* Initial fs6 */
sd zero, 54*8(t0) /* Initial fs7 */
sd zero, 55*8(t0) /* Initial fs8 */
sd zero, 56*8(t0) /* Initial fs9 */
sd zero, 57*8(t0) /* Initial fs10 */
sd zero, 58*8(t0) /* Initial fs11 */
sd zero, 59*8(t0) /* Initial ft8 */
sd zero, 60*8(t0) /* Initial ft9 */
sd zero, 61*8(t0) /* Initial ft10 */
sd zero, 62*8(t0) /* Initial ft11 */
csrr a1, fcsr /* Read fcsr for initial value */
sd a1, 63*8(t0) /* Initial fcsr */
sd zero, 64*8(t0) /* Reserved word (0) */
sd zero, 31*8(t0) // Initial ft0
sd zero, 32*8(t0) // Initial ft1
sd zero, 33*8(t0) // Initial ft2
sd zero, 34*8(t0) // Initial ft3
sd zero, 35*8(t0) // Initial ft4
sd zero, 36*8(t0) // Initial ft5
sd zero, 37*8(t0) // Initial ft6
sd zero, 38*8(t0) // Initial ft7
sd zero, 39*8(t0) // Initial fs0
sd zero, 40*8(t0) // Initial fs1
sd zero, 41*8(t0) // Initial fa0
sd zero, 42*8(t0) // Initial fa1
sd zero, 43*8(t0) // Initial fa2
sd zero, 44*8(t0) // Initial fa3
sd zero, 45*8(t0) // Initial fa4
sd zero, 46*8(t0) // Initial fa5
sd zero, 47*8(t0) // Initial fa6
sd zero, 48*8(t0) // Initial fa7
sd zero, 49*8(t0) // Initial fs2
sd zero, 50*8(t0) // Initial fs3
sd zero, 51*8(t0) // Initial fs4
sd zero, 52*8(t0) // Initial fs5
sd zero, 53*8(t0) // Initial fs6
sd zero, 54*8(t0) // Initial fs7
sd zero, 55*8(t0) // Initial fs8
sd zero, 56*8(t0) // Initial fs9
sd zero, 57*8(t0) // Initial fs10
sd zero, 58*8(t0) // Initial fs11
sd zero, 59*8(t0) // Initial ft8
sd zero, 60*8(t0) // Initial ft9
sd zero, 61*8(t0) // Initial ft10
sd zero, 62*8(t0) // Initial ft11
csrr a1, fcsr // Read fcsr for initial value
sd a1, 63*8(t0) // Initial fcsr
sd zero, 64*8(t0) // Reserved word (0)
#else
sd zero, 31*8(t0) /* Reserved word (0) */
sd zero, 31*8(t0) // Reserved word (0)
#endif
/* Setup stack pointer. */
/* thread_ptr -> tx_thread_stack_ptr = t0; */
sd t0, 16(a0) /* Save stack pointer in thread's */
ret /* control block and return */
sd t0, 16(a0) // Save stack pointer in thread's
ret // control block and return
/* } */
ports/risc-v64/gnu/src/tx_thread_system_return.S
+60 -60
View File
@@ -1,10 +1,10 @@
/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
@@ -69,97 +69,97 @@ _tx_thread_system_return:
/* sp -= sizeof(stack_frame); */
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
addi sp, sp, -29*8 /* Allocate space on the stack - with floating point enabled */
addi sp, sp, -29*8 // Allocate space on the stack - with floating point enabled
#else
addi sp, sp, -16*8 /* Allocate space on the stack - without floating point enabled */
addi sp, sp, -16*8 // Allocate space on the stack - without floating point enabled
#endif
/* Store floating point preserved registers. */
#if defined(__riscv_float_abi_single)
fsw f8, 15*8(sp) /* Store fs0 */
fsw f9, 16*8(sp) /* Store fs1 */
fsw f18, 17*8(sp) /* Store fs2 */
fsw f19, 18*8(sp) /* Store fs3 */
fsw f20, 19*8(sp) /* Store fs4 */
fsw f21, 20*8(sp) /* Store fs5 */
fsw f22, 21*8(sp) /* Store fs6 */
fsw f23, 22*8(sp) /* Store fs7 */
fsw f24, 23*8(sp) /* Store fs8 */
fsw f25, 24*8(sp) /* Store fs9 */
fsw f26, 25*8(sp) /* Store fs10 */
fsw f27, 26*8(sp) /* Store fs11 */
fsw f8, 15*8(sp) // Store fs0
fsw f9, 16*8(sp) // Store fs1
fsw f18, 17*8(sp) // Store fs2
fsw f19, 18*8(sp) // Store fs3
fsw f20, 19*8(sp) // Store fs4
fsw f21, 20*8(sp) // Store fs5
fsw f22, 21*8(sp) // Store fs6
fsw f23, 22*8(sp) // Store fs7
fsw f24, 23*8(sp) // Store fs8
fsw f25, 24*8(sp) // Store fs9
fsw f26, 25*8(sp) // Store fs10
fsw f27, 26*8(sp) // Store fs11
csrr t0, fcsr
sd t0, 27*8(sp) /* Store fcsr */
sd t0, 27*8(sp) // Store fcsr
#elif defined(__riscv_float_abi_double)
fsd f8, 15*8(sp) /* Store fs0 */
fsd f9, 16*8(sp) /* Store fs1 */
fsd f18, 17*8(sp) /* Store fs2 */
fsd f19, 18*8(sp) /* Store fs3 */
fsd f20, 19*8(sp) /* Store fs4 */
fsd f21, 20*8(sp) /* Store fs5 */
fsd f22, 21*8(sp) /* Store fs6 */
fsd f23, 22*8(sp) /* Store fs7 */
fsd f24, 23*8(sp) /* Store fs8 */
fsd f25, 24*8(sp) /* Store fs9 */
fsd f26, 25*8(sp) /* Store fs10 */
fsd f27, 26*8(sp) /* Store fs11 */
fsd f8, 15*8(sp) // Store fs0
fsd f9, 16*8(sp) // Store fs1
fsd f18, 17*8(sp) // Store fs2
fsd f19, 18*8(sp) // Store fs3
fsd f20, 19*8(sp) // Store fs4
fsd f21, 20*8(sp) // Store fs5
fsd f22, 21*8(sp) // Store fs6
fsd f23, 22*8(sp) // Store fs7
fsd f24, 23*8(sp) // Store fs8
fsd f25, 24*8(sp) // Store fs9
fsd f26, 25*8(sp) // Store fs10
fsd f27, 26*8(sp) // Store fs11
csrr t0, fcsr
sd t0, 27*8(sp) /* Store fcsr */
sd t0, 27*8(sp) // Store fcsr
#endif
sd zero, 0(sp) /* Solicited stack type */
sd ra, 13*8(sp) /* Save return address */
sd s0, 12*8(sp) /* Save s0 */
sd s1, 11*8(sp) /* Save s1 */
sd s2, 10*8(sp) /* Save s2 */
sd s3, 9*8(sp) /* Save s3 */
sd s4, 8*8(sp) /* Save s4 */
sd s5, 7*8(sp) /* Save s5 */
sd s6, 6*8(sp) /* Save s6 */
sd s7, 5*8(sp) /* Save s7 */
sd s8, 4*8(sp) /* Save s8 */
sd s9, 3*8(sp) /* Save s9 */
sd s10, 2*8(sp) /* Save s10 */
sd s11, 1*8(sp) /* Save s11 */
csrr t0, mstatus /* Pickup mstatus */
sd t0, 14*8(sp) /* Save mstatus */
sd zero, 0(sp) // Solicited stack type
sd ra, 13*8(sp) // Save return address
sd s0, 12*8(sp) // Save s0
sd s1, 11*8(sp) // Save s1
sd s2, 10*8(sp) // Save s2
sd s3, 9*8(sp) // Save s3
sd s4, 8*8(sp) // Save s4
sd s5, 7*8(sp) // Save s5
sd s6, 6*8(sp) // Save s6
sd s7, 5*8(sp) // Save s7
sd s8, 4*8(sp) // Save s8
sd s9, 3*8(sp) // Save s9
sd s10, 2*8(sp) // Save s10
sd s11, 1*8(sp) // Save s11
csrr t0, mstatus // Pickup mstatus
sd t0, 14*8(sp) // Save mstatus
/* Lockout interrupts. will be enabled in _tx_thread_schedule */
csrci mstatus, 0x08 /* Disable interrupts (MIE bit 3) */
csrci mstatus, 0x08 // Disable interrupts (MIE bit 3)
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
call _tx_execution_thread_exit /* Call the thread execution exit function */
call _tx_execution_thread_exit // Call the thread execution exit function
#endif
la t0, _tx_thread_current_ptr /* Pickup address of pointer */
ld t1, 0(t0) /* Pickup current thread pointer */
la t2, _tx_thread_system_stack_ptr /* Pickup stack pointer address */
la t0, _tx_thread_current_ptr // Pickup address of pointer
ld t1, 0(t0) // Pickup current thread pointer
la t2, _tx_thread_system_stack_ptr // Pickup stack pointer address
/* Save current stack and switch to system stack. */
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = SP;
SP = _tx_thread_system_stack_ptr; */
sd sp, 16(t1) /* Save stack pointer */
ld sp, 0(t2) /* Switch to system stack */
sd sp, 16(t1) // Save stack pointer
ld sp, 0(t2) // Switch to system stack
/* Determine if the time-slice is active. */
/* if (_tx_timer_time_slice)
{ */
la t4, _tx_timer_time_slice /* Pickup time slice variable addr */
ld t3, 0(t4) /* Pickup time slice value */
la t2, _tx_thread_schedule /* Pickup address of scheduling loop */
beqz t3, _tx_thread_dont_save_ts /* If no time-slice, don't save it */
la t4, _tx_timer_time_slice // Pickup time slice variable addr
ld t3, 0(t4) // Pickup time slice value
la t2, _tx_thread_schedule // Pickup address of scheduling loop
beqz t3, _tx_thread_dont_save_ts // If no time-slice, don't save it
/* Save time-slice for the thread and clear the current time-slice. */
/* _tx_thread_current_ptr -> tx_thread_time_slice = _tx_timer_time_slice;
_tx_timer_time_slice = 0; */
sd t3, 48(t1) /* Save current time-slice for thread */
sd zero, 0(t4) /* Clear time-slice variable */
sd t3, 48(t1) // Save current time-slice for thread
sd zero, 0(t4) // Clear time-slice variable
/* } */
_tx_thread_dont_save_ts:
ports/risc-v64/gnu/src/tx_timer_interrupt.S
+89 -89
View File
@@ -1,18 +1,18 @@
/***************************************************************************
* Copyright (c) 2026 10xEngineers
*
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
@@ -21,48 +21,48 @@
.section .text
.align 4
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt RISC-V64/GNU */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Akif Ejaz, 10xEngineers */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */
/* */
/**************************************************************************/
/* AUTHOR */
/* */
/* Akif Ejaz, 10xEngineers */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 01-20-2023 Akif Ejaz Initial Version 6.2.1 */
/* */
/**************************************************************************/
/* VOID _tx_timer_interrupt(VOID)
{ */
.global _tx_timer_interrupt
@@ -71,38 +71,38 @@ _tx_timer_interrupt:
/* Increment the system clock. */
/* _tx_timer_system_clock++; */
la t0, _tx_timer_system_clock /* Pickup address of system clock */
ld t1, 0(t0) /* Pickup system clock */
la t2, _tx_timer_time_slice /* Pickup address of time slice */
ld t3, 0(t2) /* Pickup time slice */
addi t1, t1, 1 /* Increment system clock */
sd t1, 0(t0) /* Store new system clock */
li t6, 0 /* Clear local expired flag */
la t0, _tx_timer_system_clock // Pickup address of system clock
ld t1, 0(t0) // Pickup system clock
la t2, _tx_timer_time_slice // Pickup address of time slice
ld t3, 0(t2) // Pickup time slice
addi t1, t1, 1 // Increment system clock
sd t1, 0(t0) // Store new system clock
li t6, 0 // Clear local expired flag
/* Test for time-slice expiration. */
/* if (_tx_timer_time_slice)
{ */
beqz t3, _tx_timer_no_time_slice /* If 0, skip time slice processing */
addi t3, t3, -1 /* Decrement the time slice */
beqz t3, _tx_timer_no_time_slice // If 0, skip time slice processing
addi t3, t3, -1 // Decrement the time slice
/* Decrement the time_slice. */
/* _tx_timer_time_slice--; */
sd t3, 0(t2) /* Store new time slice */
sd t3, 0(t2) // Store new time slice
/* Check for expiration. */
/* if (_tx_timer_time_slice == 0) */
bgtz t3, _tx_timer_no_time_slice /* If not 0, has not expired yet */
li t1, 1 /* Build expired flag */
bgtz t3, _tx_timer_no_time_slice // If not 0, has not expired yet
li t1, 1 // Build expired flag
/* Set the time-slice expired flag. */
/* _tx_timer_expired_time_slice = TX_TRUE; */
la t4, _tx_timer_expired_time_slice /* Get address of expired flag */
sw t1, 0(t4) /* Set expired flag (UINT) */
ori t6, t6, 1 /* Set local expired flag */
la t4, _tx_timer_expired_time_slice // Get address of expired flag
sw t1, 0(t4) // Set expired flag (UINT)
ori t6, t6, 1 // Set local expired flag
/* } */
@@ -112,19 +112,19 @@ _tx_timer_no_time_slice:
/* if (*_tx_timer_current_ptr)
{ */
la t0, _tx_timer_current_ptr /* Pickup address of current ptr */
ld t1, 0(t0) /* Pickup current pointer (double word) */
ld t3, 0(t1) /* Pickup the current timer entry (double word) */
la t2, _tx_timer_expired /* Pickup address of timer expired flag */
li t4, 1 /* Build TX_TRUE flag */
beqz t3, _tx_timer_no_timer /* If NULL, no timer has expired */
la t0, _tx_timer_current_ptr // Pickup address of current ptr
ld t1, 0(t0) // Pickup current pointer (double word)
ld t3, 0(t1) // Pickup the current timer entry (double word)
la t2, _tx_timer_expired // Pickup address of timer expired flag
li t4, 1 // Build TX_TRUE flag
beqz t3, _tx_timer_no_timer // If NULL, no timer has expired
/* Set expiration flag. */
/* _tx_timer_expired = TX_TRUE; */
ori t6, t6, 2 /* Set local expired flag */
sw t4, 0(t2) /* Set expired flag in memory (UINT) */
j _tx_timer_done /* Finished timer processing */
ori t6, t6, 2 // Set local expired flag
sw t4, 0(t2) // Set expired flag in memory (UINT)
j _tx_timer_done // Finished timer processing
/* }
@@ -138,18 +138,18 @@ _tx_timer_no_timer:
/* Check for wrap-around. */
/* if (_tx_timer_current_ptr == _tx_timer_list_end) */
la t2, _tx_timer_list_end /* Pickup address of list end pointer */
ld t3, 0(t2) /* Pickup actual list end */
addi t1, t1, 8 /* Point to next timer entry */
sd t1, 0(t0) /* Store new timer pointer */
bne t1, t3, _tx_timer_skip_wrap /* If not same, good pointer */
la t2, _tx_timer_list_end // Pickup address of list end pointer
ld t3, 0(t2) // Pickup actual list end
addi t1, t1, 8 // Point to next timer entry
sd t1, 0(t0) // Store new timer pointer
bne t1, t3, _tx_timer_skip_wrap // If not same, good pointer
/* Wrap to beginning of list. */
/* _tx_timer_current_ptr = _tx_timer_list_start; */
la t2, _tx_timer_list_start /* Pickup address of list start pointer */
ld t4, 0(t2) /* Pickup start of the list */
sd t4, 0(t0) /* Store new timer pointer */
la t2, _tx_timer_list_start // Pickup address of list start pointer
ld t4, 0(t2) // Pickup start of the list
sd t4, 0(t0) // Store new timer pointer
_tx_timer_skip_wrap:
@@ -162,23 +162,23 @@ _tx_timer_done:
/* if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
{ */
beqz t6, _tx_timer_nothing_expired /* If nothing expired skip the rest */
addi sp, sp, -16 /* Allocate some storage on the stack */
sd t6, 0(sp) /* Save local expired flag */
sd ra, 8(sp) /* Save ra (8-byte aligned) */
beqz t6, _tx_timer_nothing_expired // If nothing expired skip the rest
addi sp, sp, -16 // Allocate some storage on the stack
sd t6, 0(sp) // Save local expired flag
sd ra, 8(sp) // Save ra (8-byte aligned)
/* Did a timer expire? */
/* if (_tx_timer_expired)
{ */
andi t2, t6, 2 /* Isolate the timer expired bit */
beqz t2, _tx_timer_dont_activate /* No, timer not expired */
andi t2, t6, 2 // Isolate the timer expired bit
beqz t2, _tx_timer_dont_activate // No, timer not expired
/* Call the timer expiration processing. */
/* _tx_timer_expiration_process(void); */
call _tx_timer_expiration_process /* Call _tx_timer_expiration_process */
ld t6, 0(sp) /* Recover local expired flag */
call _tx_timer_expiration_process // Call _tx_timer_expiration_process
ld t6, 0(sp) // Recover local expired flag
/* } */
_tx_timer_dont_activate:
@@ -187,20 +187,20 @@ _tx_timer_dont_activate:
/* if (_tx_timer_expired_time_slice)
{ */
andi t2, t6, 1 /* Is the timer expired bit set? */
beqz t2, _tx_timer_not_ts_expiration /* If not, skip time slice processing */
andi t2, t6, 1 // Is the timer expired bit set?
beqz t2, _tx_timer_not_ts_expiration // If not, skip time slice processing
/* Time slice interrupted thread. */
/* _tx_thread_time_slice(); */
call _tx_thread_time_slice /* Call time slice */
call _tx_thread_time_slice // Call time slice
/* } */
_tx_timer_not_ts_expiration:
ld ra, 8(sp) /* Recover ra */
addi sp, sp, 16 /* Recover stack space */
ld ra, 8(sp) // Recover ra
addi sp, sp, 16 // Recover stack space
/* } */
_tx_timer_nothing_expired: