Support XuanTie E906 CPU.

- add ThreadX porting codes for XuanTie E906. - add example for XuanTie E906 running on QEMU smartl.
2026-10-06 06:59:08 +08:00 · 2026-02-12 23:13:31 +08:00
parent 579246b4a2
commit ede5aa2867
135 changed files with 54259 additions and 0 deletions
@@ -0,0 +1,17 @@
+
+target_sources(${PROJECT_NAME}
+    PRIVATE
+    # {{BEGIN_TARGET_SOURCES}}
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_port.c
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_context.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_interrupt_control.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_schedule.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_thread_system_return.S
+	${CMAKE_CURRENT_LIST_DIR}/src/tx_timer_interrupt.c
+    # {{END_TARGET_SOURCES}}
+)
+
+target_include_directories(${PROJECT_NAME}
+    PUBLIC
+    ${CMAKE_CURRENT_LIST_DIR}/inc
+)
@@ -0,0 +1,78 @@
+cmake_minimum_required(VERSION 3.15 FATAL_ERROR)
+
+project(demo_threadx
+    LANGUAGES C ASM
+)
+
+set(SRCS
+    ${CMAKE_CURRENT_LIST_DIR}/demo_threadx.c
+    ${CMAKE_CURRENT_LIST_DIR}/pre_main.c
+    ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/uart/board_uart.c
+    ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/src/board_init.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_misc.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/src/csi_ringbuf.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/mini_printf.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/newlib_stub.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/startup.S
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/vectors.S
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/system.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/arch/e906fdp/trap_c.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/drivers/dw_uart_ll.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/drivers/uart.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/devices.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/feature.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/irq_port.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/irq.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/pre_main.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/sys_clk.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/target_get.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/tick.c
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/src/sys/weak.c
+)
+
+include_directories(
+    ${CMAKE_CURRENT_LIST_DIR}/../../../../../../common/inc
+    ${CMAKE_CURRENT_LIST_DIR}/../../inc
+    ${CMAKE_CURRENT_LIST_DIR}
+    ${CMAKE_CURRENT_LIST_DIR}/boards/board_riscv_dummy/include
+    ${CMAKE_CURRENT_LIST_DIR}/components/csi/csi2/include
+    ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/include
+    ${CMAKE_CURRENT_LIST_DIR}/components/libc_threadx/compilers/gcc
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/include
+    ${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/include/asm
+)
+
+add_compile_options(
+    -Os -g -Wno-main
+    -Wpointer-arith -Wno-undef -ffunction-sections -fdata-sections -fno-inline-functions -fno-builtin -fno-strict-aliasing
+    -DCONFIG_SUPPORT_TSPEND=1
+    -DCONFIG_ARCH_MAINSTACK=4096
+    -DCONFIG_ARCH_INTERRUPTSTACK=4096
+    -DCONFIG_SUPPORT_IRQ_NESTED=1
+    -DCONFIG_INTC_CLIC=1
+    -DCONFIG_INTC_CLINT=1
+    -DCONFIG_XIP=1
+    -DCONFIG_LIBC_MINI_PRINTF_SUPPORT=1
+    -DCONFIG_SYSTICK_HZ=100
+    -DCONFIG_BOARD_SMARTL_EVB=1
+    -DCONFIG_CPU_XUANTIE_E906FDP=1
+    -DCONFIG_KERNEL_THREADX=1
+    -DTX_INCLUDE_USER_DEFINE_FILE
+)
+
+add_link_options(
+    -nostartfiles -Wl,--gc-sections
+    -T${CMAKE_CURRENT_LIST_DIR}/components/chip_riscv_dummy/gcc_flash_smartl.ld
+    -Wl,-zmax-page-size=1024
+    -Wl,-Map=${PROJECT_NAME}.map
+)
+
+link_directories(${CMAKE_CURRENT_LIST_DIR}/../../../../../../build)
+add_executable(${PROJECT_NAME} ${SRCS})
+set_target_properties(${PROJECT_NAME} PROPERTIES OUTPUT_NAME "${PROJECT_NAME}.elf")
+target_link_libraries(${PROJECT_NAME} PRIVATE threadx)
+
+add_custom_command(TARGET ${PROJECT_NAME} POST_BUILD
+    COMMAND ${OBJDUMP} -d $<TARGET_FILE:${PROJECT_NAME}> > ${PROJECT_NAME}.asm
+    COMMENT "Generating ASM disassembly files"
+)
@@ -0,0 +1,26 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CSI_CONFIG_H__
+#define __CSI_CONFIG_H__
+
+
+
+
+
+#endif /* __CSI_CONFIG_H__ */
@@ -0,0 +1,83 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <board.h>
+
+void board_init(void)
+{
+    /* some board preconfig */
+    // board_xxx();
+
+#if defined(BOARD_GPIO_PIN_NUM) && BOARD_GPIO_PIN_NUM > 0
+    board_gpio_pin_init();
+#endif
+
+#if defined(BOARD_UART_NUM) && BOARD_UART_NUM > 0
+#if !defined(RT_DEBUG_INIT) || !RT_DEBUG_INIT
+    board_uart_init();
+#endif
+#endif
+
+#if defined(BOARD_PWM_NUM) && BOARD_PWM_NUM > 0
+    board_pwm_init();
+#endif
+
+#if defined(BOARD_ADC_NUM) && BOARD_ADC_NUM > 0
+    board_adc_init();
+#endif
+
+#if defined(BOARD_BUTTON_NUM) && BOARD_BUTTON_NUM > 0
+    board_button_init();
+#endif
+
+#if defined(BOARD_LED_NUM) && BOARD_LED_NUM > 0
+    board_led_init();
+#endif
+
+#if defined(BOARD_WIFI_SUPPORT) && BOARD_WIFI_SUPPORT > 0
+    board_wifi_init();
+#endif
+
+#if defined(BOARD_BT_SUPPORT) && BOARD_BT_SUPPORT > 0
+    board_bt_init();
+#endif
+
+#if defined(BOARD_AUDIO_SUPPORT) && BOARD_AUDIO_SUPPORT > 0
+    board_audio_init();
+#endif
+}
+
+#ifdef CONFIG_KERNEL_THREADX
+#include <tx_api.h>
+
+extern unsigned long g_heap_start;
+extern unsigned long g_heap_end;
+
+TX_BYTE_POOL tx_byte_pool_0;
+UCHAR *tx_memory_area;
+
+void tx_mem_pool_init(void)
+{
+    ULONG pool_size = g_heap_end - g_heap_start;
+    tx_memory_area = (UCHAR *)g_heap_start;
+
+    tx_byte_pool_create(&tx_byte_pool_0, "byte pool sys 0", tx_memory_area, pool_size);
+}
+#endif
@@ -0,0 +1,45 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <board.h>
+#if CONFIG_DEVICES_RVM_HAL
+#include <devices/devicelist.h>
+#else
+#include <drv/uart.h>
+#endif
+
+#if CONFIG_DEVICES_RVM_HAL
+void board_uart_init(void)
+{
+    rvm_uart_drv_register(0);
+}
+#else
+__attribute__((weak)) csi_uart_t g_console_handle;
+
+void board_uart_init(void)
+{
+    /* init the console */
+    csi_uart_init(&g_console_handle, CONSOLE_UART_IDX);
+
+    /* config the UART */
+    csi_uart_baud(&g_console_handle, CONFIG_CLI_USART_BAUD);
+    csi_uart_format(&g_console_handle, UART_DATA_BITS_8, UART_PARITY_NONE, UART_STOP_BITS_1);
+}
+#endif
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+pushd ../../../../../../
+rm -rf build
+cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=ports/xuantie/e906/gnu/example_build/smartl_fpga/xuantie_e906_gnu.cmake .
+cmake --build ./build/
+popd
@@ -0,0 +1,7 @@
+#!/bin/bash
+
+bash build_libthreadx.sh
+
+rm -rf build
+cmake -Bbuild -GNinja -DCMAKE_TOOLCHAIN_FILE=xuantie_e906_gnu.cmake .
+cmake --build ./build/
@@ -0,0 +1,177 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     gcc_csky.ld
+ * @brief    csky linker file
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+MEMORY
+{
+    ISRAM : ORIGIN = 0x00000000 , LENGTH = 0x30000   /* ISRAM 192KB*/
+    DSRAM : ORIGIN = 0x20000000 , LENGTH = 0xC0000   /* DSRAM 768KB*/
+    SRAM :  ORIGIN = 0x60000000 , LENGTH = 0x20000   /* SRAM 128KB, no cacheable*/
+}
+
+__min_heap_size = 0x200;
+PROVIDE (__ram_end  = 0x200C0000);
+PROVIDE (__heap_end = __ram_end);
+
+REGION_ALIAS("REGION_TEXT",    ISRAM);
+REGION_ALIAS("REGION_RODATA",  ISRAM);
+REGION_ALIAS("REGION_DATA",    DSRAM);
+REGION_ALIAS("REGION_BSS",     DSRAM);
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+ .text : {
+  . = ALIGN(0x4) ;
+  __stext = . ;
+  KEEP(*startup.o(*.text))
+  KEEP(*startup.o(*.vectors))
+  KEEP(*vectors.o(*.text))
+  KEEP(*whetstone.o(*.text))
+  KEEP(*startup.S.obj(*.text))  
+  KEEP(*startup.S.obj(*.vectors))
+  KEEP(*vectors.S.obj(*.text))
+  KEEP(*whetstone.c.obj(*.text))
+  KEEP(*(.text.entry))
+  *(.text*)
+  *(.gnu.warning)
+  *(.stub)
+  *(.gnu.linkonce.t*)
+  *(.glue_7t)
+  *(.glue_7)
+  *(.jcr)
+  KEEP (*(.init))
+  KEEP (*(.fini))
+  . = ALIGN (0x4) ;
+  PROVIDE(__ctbp = .);
+  *(.call_table_data)
+  *(.call_table_text)
+  . = ALIGN(0x10) ;
+  __etext = . ;
+ } > REGION_TEXT
+ .eh_frame_hdr : {
+  *(.eh_frame_hdr)
+ } > REGION_TEXT
+ .eh_frame : ONLY_IF_RO {
+  KEEP (*(.eh_frame))
+ } > REGION_TEXT
+ .rodata : {
+  . = ALIGN(0x4) ;
+  __srodata = .;
+  *(.rdata)
+  *(.rdata*)
+  *(.rdata1)
+  *(.rdata.*)
+  *(.rodata*)
+  *(.srodata*)
+  . = ALIGN(0x4) ;
+  __init_array_start = .;
+  __ctors_start__ = .;
+  KEEP (*(SORT(.init_array.*)))
+  KEEP (*(.init_array))
+  __init_array_end = .;
+  __ctors_end__ = .;
+
+  __fini_array_start = .;
+  __dtors_start__ = .;
+  KEEP (*(SORT(.fini_array.*)))
+  KEEP (*(.fini_array))
+  __fini_array_end = .;
+  __dtors_end__ = .;
+  . = ALIGN(0x4) ;
+
+  __ctor_start__ = .;
+  KEEP (*(SORT(.ctors.*)))
+  KEEP (*(.ctors))
+  __ctor_end__ = .;
+  KEEP (*(SORT(.dtors.*)))
+  KEEP (*(.dtors))
+  __dtor_end__ = .;
+  . = ALIGN(0x4) ;
+  __erodata = .;
+  __rodata_end__ = .;
+ } > REGION_RODATA
+ .data : {
+  . = ALIGN(0x4) ;
+  __sdata = . ;
+  __data_start__ = . ;
+  data_start = . ;
+  *(.got.plt)
+  *(.got)
+  *(.gnu.linkonce.r*)
+  *(.data*)
+  *(.gnu.linkonce.d*)
+  *(.gcc_except_table*)
+  __start_init_call = .;
+  *(.initcall.init)
+  __stop_init_call = .;
+  __start_cmd = .;
+  *(.bootloaddata.cmd)
+  . = ALIGN(0x4) ;
+  __stop_cmd = .;
+  __global_pointer$ = .;
+  *(.sdata)
+  *(.sdata.*)
+  *(.sdata2.*)
+  *(.gnu.linkonce.s.*)
+  *(__libc_atexit)
+  *(__libc_subinit)
+  *(__libc_subfreeres)
+  *(.note.ABI-tag)
+  . = ALIGN(0x4) ;
+  __edata = .;
+  __data_end__ = .;
+ } > REGION_DATA AT > REGION_RODATA
+ ._ram_code : {
+  . = ALIGN(0x4) ;
+  __ram_code_start__ = .;
+  *(.ram.code*)
+  . = ALIGN(0x4) ;
+  __ram_code_end__ = .;
+ } > REGION_DATA AT > REGION_RODATA
+ .bss : ALIGN(0x20) {
+  __sbss = . ;
+  __bss_start__ = . ;
+  KEEP(*linpack.o(*.bss*))
+  *(.dynsbss)
+  *(.sbss)
+  *(.sbss.*)
+  *(.scommon)
+  *(.dynbss)
+  *(.bss*)
+  *(COMMON)
+  . = ALIGN(0x4) ;
+  __ebss = . ;
+  __bss_end__ = .;
+  __end = . ;
+  end = . ;
+ } > REGION_BSS AT > REGION_BSS
+ ._user_heap (NOLOAD): {
+  . = ALIGN(0x4) ;
+  *(.stack*)
+  . = ALIGN(0x4) ;
+  __heap_start = .;
+  . += __min_heap_size;
+  . = ALIGN(0x4) ;
+ } > REGION_BSS AT > REGION_BSS
+}
@@ -0,0 +1,191 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * attention: don't modify this file as a suggest
+ * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer
+ * please contact xuantie-rtos os team if have question 
+ */
+
+#ifndef __RISCV_CSR_H__
+#define __RISCV_CSR_H__
+
+#if __riscv_xlen == 64
+	#define store_x       sd
+	#define load_x        ld
+	#define portWORD_SIZE 8
+#elif __riscv_xlen == 32
+	#define store_x       sw
+	#define load_x        lw
+	#define portWORD_SIZE 4
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+#if __riscv_flen == 64
+	#define fstore_x      fsd
+	#define fload_x       fld
+	#define portFPU_REG_SIZE 8
+#elif __riscv_flen == 32
+	#define fstore_x      fsw
+	#define fload_x       flw
+	#define portFPU_REG_SIZE 4
+#endif
+
+#if CONFIG_RISCV_SMODE
+#define MODE_PREFIX(suffix) s##suffix
+#else
+#define MODE_PREFIX(suffix) m##suffix
+#endif
+
+/* Status register flags */
+#define SR_SIE      0x00000002UL        /*  Supervisor Interrupt Enable */
+#define SR_MIE      0x00000008UL        /*  Machine Interrupt Enable */
+#define SR_SPIE     0x00000020UL        /*  Previous Supervisor IE */
+#define SR_MPIE     0x00000080UL        /*  Previous Machine IE */
+#define SR_SPP_U    0x00000000UL        /*  Previously User mode */
+#define SR_SPP_S    0x00000100UL        /*  Previously Supervisor mode */
+#define SR_MPP_U    0x00000000UL        /*  Previously User mode */
+#define SR_MPP_S    0x00000800UL        /*  Previously Supervisor mode */
+#define SR_MPP_M    0x00001800UL        /*  Previously Machine mode */
+#define SR_SUM      0x00040000UL        /*  Supervisor User Memory Access */
+
+#define SR_FS           0x00006000UL    /*  Floating-point Status */
+#define SR_FS_OFF       0x00000000UL
+#define SR_FS_INITIAL   0x00002000UL
+#define SR_FS_CLEAN     0x00004000UL
+#define SR_FS_DIRTY     0x00006000UL
+
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+	|| CONFIG_CPU_XUANTIE_R920 \
+	|| CONFIG_CPU_XUANTIE_C920
+#define SR_VS          0x01800000
+#define SR_VS_OFF      0x00000000
+#define SR_VS_INITIAL  0x00800000
+#define SR_VS_CLEAN    0x01000000
+#define SR_VS_DIRTY    0x01800000
+#else
+#define SR_VS          0x00000600
+#define SR_VS_OFF      0x00000000
+#define SR_VS_INITIAL  0x00000200
+#define SR_VS_CLEAN    0x00000400
+#define SR_VS_DIRTY    0x00000600
+#endif
+
+#if __riscv_matrix || __riscv_xtheadmatrix
+#define SR_MS          0x06000000
+#define SR_MS_OFF      0x00000000
+#define SR_MS_INITIAL  0x02000000
+#define SR_MS_CLEAN    0x04000000
+#define SR_MS_DIRTY    0x06000000
+#endif
+
+/* Interrupt-enable Registers */
+#define IE_MTIE         0x00000080UL
+#define IE_MEIE         0x00000800UL
+
+/*  ===== Trap/Exception Causes ===== */
+#define CAUSE_MISALIGNED_FETCH          0x0
+#define CAUSE_FETCH_ACCESS              0x1
+#define CAUSE_ILLEGAL_INSTRUCTION       0x2
+#define CAUSE_BREAKPOINT                0x3
+#define CAUSE_MISALIGNED_LOAD           0x4
+#define CAUSE_LOAD_ACCESS               0x5
+#define CAUSE_MISALIGNED_STORE          0x6
+#define CAUSE_STORE_ACCESS              0x7
+#define CAUSE_USER_ECALL                0x8
+#define CAUSE_SUPERVISOR_ECALL          0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL  0xa
+#define CAUSE_MACHINE_ECALL             0xb
+#define CAUSE_FETCH_PAGE_FAULT          0xc
+#define CAUSE_LOAD_PAGE_FAULT           0xd
+#define CAUSE_STORE_PAGE_FAULT          0xf
+
+#define PRV_U                           0
+#define PRV_S                           1
+#define PRV_M                           3
+
+
+#define MSTATUS_SIE                     0x00000002
+#define MSTATUS_MIE                     0x00000008
+#define MSTATUS_SPIE_SHIFT              5
+#define MSTATUS_SPIE                    (1 << MSTATUS_SPIE_SHIFT)
+#define MSTATUS_UBE                     0x00000040
+#define MSTATUS_MPIE                    0x00000080
+#define MSTATUS_SPP_SHIFT               8
+#define MSTATUS_SPP                     (1 << MSTATUS_SPP_SHIFT)
+#define MSTATUS_MPP_SHIFT               11
+#define MSTATUS_MPP                     (3 << MSTATUS_MPP_SHIFT)
+
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+	|| CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+	|| CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920
+#define MSTATUS_VS_SHIFT                23
+#else
+#define MSTATUS_VS_SHIFT                9
+#endif
+#define MSTATUS_FS_SHIFT                13
+#define MSTATUS_MS_SHIFT                25
+
+#define INSERT_FIELD(val, which, fieldval)	(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+
+#if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV \
+	|| CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V || CONFIG_CPU_XUANTIE_C908I \
+	|| CONFIG_CPU_XUANTIE_C908_V2 || CONFIG_CPU_XUANTIE_C908V_V2 || CONFIG_CPU_XUANTIE_C908I_V2 \
+	|| CONFIG_CPU_XUANTIE_C908_CP_V2 || CONFIG_CPU_XUANTIE_C908V_CP_V2 || CONFIG_CPU_XUANTIE_C908I_CP_V2 \
+	|| CONFIG_CPU_XUANTIE_C908_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908V_CP_XT_V2 || CONFIG_CPU_XUANTIE_C908I_CP_XT_V2 \
+	|| CONFIG_CPU_XUANTIE_C908VK_CP_V2 || CONFIG_CPU_XUANTIE_C908VK_CP_XT_V2 \
+	|| CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920 \
+	|| CONFIG_CPU_XUANTIE_C910 || CONFIG_CPU_XUANTIE_C920 \
+	|| CONFIG_CPU_XUANTIE_XT_C930_CP || CONFIG_CPU_XUANTIE_XT_C930V_CP
+#define ATTR_SO                 (1ull << 4)
+#define ATTR_CA                 (1ull << 3)
+#define ATTR_BU                 (1ull << 2)
+#define ATTR_SH                 (1ull << 1)
+#define ATTR_SE                 (1ull << 0)
+
+#define UPPER_ATTRS_SHIFT       (59)
+#define UPPER_ATTRS(x)          (((x) & 0x1f) << UPPER_ATTRS_SHIFT)
+#else
+#if __riscv_xlen == 32
+#define PTE_PBMT_SHIFT          (30)
+#else
+#define PTE_PBMT_SHIFT          (61)
+#endif /* end __riscv_xlen */
+#define SVPBMT_PMA              ((unsigned long)0x0 << PTE_PBMT_SHIFT)
+#define SVPBMT_NC               ((unsigned long)0x1 << PTE_PBMT_SHIFT)
+#define SVPBMT_IO               ((unsigned long)0x2 << PTE_PBMT_SHIFT)
+#define SVPBMT_MASK             ((unsigned long)0x3 << PTE_PBMT_SHIFT)
+
+#endif
+
+#define DIRTY_FLAG              (1 << 6)
+#define ACCESS_FLAG             (1 << 5)
+#define GLOBAL_FLAG             (1 << 4)
+#define AP_UNPRIV               (1 << 3)
+#define AP_X                    (1 << 2)
+#define AP_W                    (1 << 1)
+#define AP_R                    (1 << 0)
+
+#define LOWER_ATTRS_SHIFT               1
+#define LOWER_ATTRS(x)                  (((x) & 0x1ff) << LOWER_ATTRS_SHIFT)
+
+
+
+#endif /* __RISCV_CSR_H__ */
+
@@ -0,0 +1,104 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/dev_tag.h
+ * @brief    Header File for DEV TAG Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_DEV_TAG_H_
+#define _DRV_DEV_TAG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include <drv/list.h>
+#include <csi_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    DEV_BLANK_TAG = 0U,
+    DEV_DW_UART_TAG,
+    DEV_DW_AHB_DMA_TAG,
+    DEV_DW_AXI_DMA_TAG,
+    DEV_DW_GPIO_TAG,
+    DEV_DW_IIC_TAG,
+    DEV_DW_QSPI_TAG,
+    DEV_DW_SDMMC_TAG,
+    DEV_DW_SDHCI_TAG,
+    DEV_DW_SPI_TAG,
+    DEV_DW_TIMER_TAG,
+    DEV_DW_WDT_TAG,
+    DEV_WJ_ADC_TAG,
+    DEV_WJ_AES_TAG,
+    DEV_WJ_CODEC_TAG,
+    DEV_WJ_CRC_TAG,
+    DEV_WJ_DMA_TAG,
+    DEV_WJ_EFLASH_TAG,
+    DEV_WJ_EFUSE_TAG,
+    DEV_WJ_ETB_TAG,
+    DEV_WJ_FFT_TAG,
+    DEV_WJ_I2S_TAG,
+    DEV_WJ_MBOX_TAG,
+    DEV_WJ_PADREG_TAG,
+    DEV_WJ_PDM_TAG,
+    DEV_WJ_PINMUX_TAG,
+    DEV_WJ_PMU_TAG,
+    DEV_WJ_PWM_TAG,
+    DEV_WJ_RNG_TAG,
+    DEV_WJ_ROM_TAG,
+    DEV_WJ_RSA_TAG,
+    DEV_WJ_RTC_TAG,
+    DEV_WJ_SASC_TAG,
+    DEV_WJ_SHA_TAG,
+    DEV_WJ_SPDIF_TAG,
+    DEV_WJ_SPIDF_TAG,
+    DEV_WJ_TDM_TAG,
+    DEV_WJ_TIPC_TAG,
+    DEV_WJ_USB_TAG,
+    DEV_WJ_USI_TAG,
+    DEV_WJ_VAD_TAG,
+    DEV_CD_QSPI_TAG,
+    DEV_DCD_ISO7816_TAG,
+    DEV_OSR_RNG_TAG,
+    DEV_QX_RTC_TAG,
+    DEV_RCHBAND_CODEC_TAG,
+    DEV_CMSDK_UART_TAG,
+    DEV_RAMBUS_150B_PKA_TAG,
+    DEV_RAMBUS_150B_TRNG_TAG,
+    DEV_RAMBUS_120SI_TAG,
+    DEV_RAMBUS_120SII_TAG,
+    DEV_RAMBUS_120SIII_TAG,
+    DEV_WJ_AVFS_TAG,
+    DEV_WJ_BMU_TAG,
+    DEV_XT_IOPMP_TAG,
+} csi_dev_tag_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TAG_H_ */
+
@@ -0,0 +1,167 @@
+/*
+ *	Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ */
+
+/*******************************************************
+ * @file 	dw_timer_ll.h
+ * @brief	header file for timer ll driver
+ * @version V1.0
+ * @date	9. April 2020
+ * ******************************************************/
+
+#ifndef _DW_TIMER_LL_H_
+#define _DW_TIMER_LL_H_
+
+#include <stdio.h>
+#include <soc.h>
+#include <csi_core.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*! Timer1 Control Reg, 	offset: 0x08 */
+#define DW_TIMER_CTL_ENABLE_SEL_Pos                                    (0U)
+#define DW_TIMER_CTL_ENABLE_SEL_Msk                                    (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
+#define DW_TIMER_CTL_ENABLE_SEL_EN                                     DW_TIMER_CTL_ENABLE_SEL_Msk
+
+#define DW_TIMER_CTL_MODE_SEL_Pos                                      (1U)
+#define DW_TIMER_CTL_MODE_SEL_Msk                                      (0x1U << DW_TIMER_CTL_MODE_SEL_Pos)
+#define DW_TIMER_CTL_MODE_SEL_EN                                       DW_TIMER_CTL_MODE_SEL_Msk
+
+#define DW_TIMER_CTL_INT_MASK_Pos                                      (2U)
+#define DW_TIMER_CTL_INT_MASK_Msk                                      (0x1U << DW_TIMER_CTL_INT_MASK_Pos)
+#define DW_TIMER_CTL_INT_MAKS_EN                                       DW_TIMER_CTL_INT_MASK_Msk
+
+#define DW_TIMER_CTL_HARD_TRIG_Pos                                     (4U)
+#define DW_TIMER_CTL_HARD_TRIG_Msk                                     (0x1U << DW_TIMER_CTL_HARD_TRIG_Pos)
+#define DW_TIMER_CTL_HARD_TRIG_EN                                      DW_TIMER_CTL_HARD_TRIG_Msk
+
+/*! Timer EOI,            offset: 0x0c */
+#define DW_TIMER_EOI_REG_Pos                                           (0U)
+#define DW_TIMER_EOI_REG_Msk                                           (0x1U << DW_TIMER_EOI_REG_Pos)
+#define DW_TIMER_EOI_REG_EN                                            DW_TIMER_EOI_REG_Msk
+
+/*! Timer Int Status,     offset: 0x10 */
+#define DW_TIMER_INT_STATUS_Pos                                        (0U)
+#define DW_TIMER_INT_STATUS_Msk                                        (0x1U << DW_TIMER_INT_STATUS_Pos)
+#define DW_TIMER_INT_STATUS_EN                                         DW_TIMER_INT_STATUS_Msk
+
+/*! Timers Int Status,    offset: 0xa0 */
+#define DW_TIMERS_INT_STATUS_Pos                                       (0U)
+#define DW_TIMERS_INT_STATUS_Msk                                       (0x2U << DW_TIMERS_INT_STATUS_Pos)
+#define DW_TIMERS_INT_STATUS_EN                                        DW_TIMERS_INT_STATUS_Msk
+
+/*! Timers EOI,           offset: 0xa4 */
+#define DW_TIMERS_EOI_REG_Pos                                          (0U)
+#define DW_TIMERS_EOI_REG_Msk                                          (0x2U << DW_TIMERS_EOI_REG_Pos)
+#define DW_TIMERS_EOI_REG_EN                                           DW_TIMERS_EOI_REG_Msk
+
+/*! Timers Raw Int Status,offset: 0xa8 */
+#define DW_TIMERS_RAW_INT_STA_Pos                                      (0U)
+#define DW_TIMERS_RAW_INT_STA_Msk                                      (0x2U << DW_TIMERS_RAW_INT_STA_Pos)
+#define DW_TIMERS_RAW_INT_STA_EN                                       DW_TIMERS_RAW_INT_STA_Msk
+
+typedef struct {
+    __IOM uint32_t TLC;                                                /* Offset: 0x000 (R/W) TimerLoadCount */
+    __IM  uint32_t TCV;                                                /* Offset: 0x004 (R/ ) TimerCurrentValue */
+    __IOM uint32_t TCR;                                                /* Offset: 0x008 (R/W) TimerControlReg */
+    __IM  uint32_t TEOI;                                               /* Offset: 0x00c (R/ ) TimerEOI */
+    __IM  uint32_t TIS;                                                /* Offset: 0x010 (R/ ) TimerIntStatus */
+} dw_timer_regs_t;
+
+typedef struct {
+    dw_timer_regs_t timer[8];
+    __IM  uint32_t TSIS;                                               /* Offset: 0x0a0 (R/ ) TimersIntStatus */
+    __IM  uint32_t TSEOI;                                              /* Offset: 0x0a4 (R/ ) TimersEOI */
+    __IM  uint32_t TSRIS;                                              /* Offset: 0x0a8 (R/ ) TimersRawIntStatus */
+} dw_timer_general_regs_t;
+
+static inline uint32_t dw_timer_read_load(dw_timer_regs_t *timer_base)
+{
+    return (timer_base->TLC);
+}
+static inline void dw_timer_write_load(dw_timer_regs_t *timer_base, uint32_t value)
+{
+    timer_base->TLC = value;
+}
+static inline uint32_t dw_timer_get_current(dw_timer_regs_t *timer_base)
+{
+    return (timer_base->TCV);
+}
+static inline void dw_timer_set_enable(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR |= (DW_TIMER_CTL_ENABLE_SEL_EN);
+}
+static inline void dw_timer_set_disable(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR &= ~(DW_TIMER_CTL_ENABLE_SEL_EN);
+}
+static inline uint32_t dw_timer_get_enable(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TCR) & DW_TIMER_CTL_ENABLE_SEL_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline void dw_timer_set_mode_free(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR &= ~(DW_TIMER_CTL_MODE_SEL_EN);
+}
+static inline void dw_timer_set_mode_load(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR |= (DW_TIMER_CTL_MODE_SEL_EN);
+}
+static inline uint32_t dw_timer_get_model(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TCR) & DW_TIMER_CTL_MODE_SEL_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline void dw_timer_set_mask(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR |= (DW_TIMER_CTL_INT_MAKS_EN);
+}
+static inline void dw_timer_set_unmask(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR &= ~(DW_TIMER_CTL_INT_MAKS_EN);
+}
+static inline uint32_t dw_timer_get_mask(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TCR) & DW_TIMER_CTL_INT_MAKS_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline void dw_timer_set_hardtrigger_en(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR |= (DW_TIMER_CTL_HARD_TRIG_EN);
+}
+static inline void dw_timer_set_hardtrigger_dis(dw_timer_regs_t *timer_base)
+{
+    timer_base->TCR &= ~(DW_TIMER_CTL_HARD_TRIG_EN);
+}
+static inline uint32_t dw_timer_get_hardtrigger(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TCR) & DW_TIMER_CTL_HARD_TRIG_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline uint32_t dw_timer_clear_irq(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TEOI) & DW_TIMER_EOI_REG_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline uint32_t dw_timer_get_int_status(dw_timer_regs_t *timer_base)
+{
+    return (((timer_base->TIS) & DW_TIMER_INT_STATUS_EN) ? (uint32_t)1 : (uint32_t)0);
+}
+static inline uint32_t dw_timer_general_active_after_mask(dw_timer_general_regs_t *timer_base)
+{
+    return ((timer_base->TSIS) & DW_TIMERS_INT_STATUS_EN);
+}
+static inline uint32_t dw_timer_general_clear_irq(dw_timer_general_regs_t *timer_base)
+{
+    return ((timer_base->TSEOI) & DW_TIMERS_EOI_REG_EN);
+}
+static inline uint32_t dw_timer_general_active_prior_mask(dw_timer_general_regs_t *timer_base)
+{
+    return ((timer_base->TSRIS) & DW_TIMERS_RAW_INT_STA_EN);
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DW_TIMER_LL_H_ */
@@ -0,0 +1,117 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     sys_clk.h
+ * @brief    header file for setting system frequency.
+ * @version  V1.0
+ * @date     9. April 2020
+ ******************************************************************************/
+#ifndef _SYS_CLK_H_
+#define _SYS_CLK_H_
+
+#include <stdint.h>
+#include <soc.h>
+#include <drv/clk.h>
+#include <drv/porting.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PMU_REG_BASE            (wj_pmu_reg_t *)WJ_PMU_BASE
+
+typedef enum {
+    IHS_CLK       = 0U,        /* internal high speed clock */
+    EHS_CLK,                   /* external high speed clock */
+    ILS_CLK,                   /* internal low  speed clock */
+    ELS_CLK,                   /* external low  speed clock */
+    PLL_CLK                    /* PLL clock */
+} clk_src_t;
+
+typedef enum {
+    CPU_24MHZ     = 24000000U
+} sys_freq_t;
+
+
+/* pllclkout : ( pllclkin / 2)*( FN + Frac/4096 ) */
+typedef struct {
+
+    uint32_t pll_is_used;          /* pll is used */
+
+    uint32_t pll_source;           /* select pll input source clock */
+
+    uint32_t pll_src_clk_divider;  /* ratio between pll_srcclk clock and pll_clkin clock */
+
+    uint32_t fn;                   /* integer value of frequency division */
+
+    uint32_t frac;                 /* decimal value of frequency division */
+
+} pll_config_t;
+
+
+typedef struct {
+    uint32_t system_clk;            /* system clock */
+
+    pll_config_t pll_config;        /* pll config struct */
+
+    uint32_t sys_clk_source;        /* select sysclk source clock */
+
+    uint32_t rtc_clk_source;        /* select rtcclk source clock */
+
+    uint32_t mclk_divider;          /* ratio between fs_mclk clock and mclk clock */
+
+    uint32_t apb0_clk_divider;      /* ratio between mclk clock and apb0 clock */
+
+    uint32_t apb1_clk_divider;      /* ratio between mclk clock and apb1 clock */
+
+} system_clk_config_t;
+
+typedef enum {
+    CLK_DIV1 = 0U,
+} apb_div_t;
+
+typedef enum {
+    PLL_FN_18 = 0U,
+} pll_fn_t;
+
+typedef enum {
+    UART0_CLK,
+} clk_module_t;
+
+
+/**
+  \brief       Set the system clock according to the parameter
+  \param[in]   config    system clock config.
+  \return      error code
+*/
+csi_error_t soc_sysclk_config(system_clk_config_t *config);
+
+/**
+  \brief       Set iic reset
+  \param[in]   idx    iic idx.
+  \return      Null
+*/
+void soc_reset_iic(uint32_t idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS_CLK_H_ */
+
@@ -0,0 +1,121 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <csi_config.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <drv/irq.h>
+#include <drv/dma.h>
+#include <drv/tick.h>
+#include <drv/etb.h>
+#include <drv/spiflash.h>
+#include "riscv_csr.h"
+
+#if (defined(CONFIG_KERNEL_RHINO) || defined(CONFIG_KERNEL_FREERTOS) || defined(CONFIG_KERNEL_RTTHREAD)) && defined(CONFIG_KERNEL_NONE)
+#error "Please check the current system is baremetal or not!!!"
+#endif
+
+extern void section_data_copy(void);
+extern void section_ram_code_copy(void);
+extern void section_bss_clear(void);
+
+static void cache_init(void)
+{
+    csi_dcache_enable();
+    csi_icache_enable();
+}
+
+static void section_init(void)
+{
+#if CONFIG_XIP
+    section_data_copy();
+    section_ram_code_copy();
+    csi_dcache_clean();
+    csi_icache_invalid();
+#endif
+    section_bss_clear();
+}
+
+static void clic_init(void)
+{
+    int i;
+
+    /* get interrupt level from info */
+    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+    for (i = 0; i < 64; i++) {
+        CLIC->CLICINT[i].IP = 0;
+#if !CONFIG_SUPPORT_NON_VECTOR_IRQ
+        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+#else
+        CLIC->CLICINT[i].ATTR = 0; /* use non-vector interrupt */
+#endif
+        csi_vic_set_prio(i, 3);
+    }
+    /* tspend use vector&positive interrupt */
+    CLIC->CLICINT[Machine_Software_IRQn].ATTR = 0x3;
+    csi_vic_set_prio(Machine_Software_IRQn, 1);
+    csi_irq_enable(Machine_Software_IRQn);
+}
+
+static void interrupt_init(void)
+{
+    clic_init();
+#ifdef CONFIG_KERNEL_NONE
+    __enable_excp_irq();
+#endif
+}
+
+/**
+  * @brief  initialize the system
+  *         Initialize the psr and vbr.
+  * @param  None
+  * @return None
+  */
+void SystemInit(void)
+{
+    extern int cpu_features_init(void);
+    cpu_features_init();
+
+    /* enable theadisaee & MM */
+    uint32_t status = __get_MXSTATUS();
+    status |= (1 << 22 | 1 << 15);
+    __set_MXSTATUS(status);
+
+#if __riscv_flen
+    /* enable float ISA */
+    status = __get_MSTATUS();
+    status |= (1 << MSTATUS_FS_SHIFT);
+    __set_MSTATUS(status);
+#endif
+     /* enable mexstatus SPUSHEN and disable SPSWAPEN */
+#if CONFIG_CPU_XUANTIE_E906 || CONFIG_CPU_XUANTIE_E906F || CONFIG_CPU_XUANTIE_E906FD || CONFIG_CPU_XUANTIE_E906P || CONFIG_CPU_XUANTIE_E906FP || CONFIG_CPU_XUANTIE_E906FDP \
+    || CONFIG_CPU_XUANTIE_E907 || CONFIG_CPU_XUANTIE_E907F || CONFIG_CPU_XUANTIE_E907FD || CONFIG_CPU_XUANTIE_E907P || CONFIG_CPU_XUANTIE_E907FP || CONFIG_CPU_XUANTIE_E907FDP
+    status = __get_MEXSTATUS();
+    status |= (0x1 << 16);
+    status &= ~(0x2 << 16);
+    __set_MEXSTATUS(status);
+#endif
+
+    cache_init();
+    section_init();
+    interrupt_init();
+    soc_set_sys_freq(20000000);
+    csi_tick_init();
+}
+
@@ -0,0 +1,64 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <csi_core.h>
+#if defined(AOS_COMP_DEBUG) && (AOS_COMP_DEBUG > 0)
+#include <debug/dbg.h>
+#else
+#define printk printf
+#endif
+
+void (*trap_c_callback)(void);
+
+void trap_c(uintptr_t *regs)
+{
+    int i;
+    unsigned long vec = 0;
+
+    vec = __get_MCAUSE();
+
+    printk("CPU Exception(mcause);: NO.0x%lx", vec);
+    printk("\n");
+
+    for (i = 0; i < 31; i++) {
+        printk("x%d: %p\t", i + 1, (void *)regs[i]);
+
+        if ((i % 4) == 3) {
+            printk("\n");
+        }
+    }
+
+    printk("\n");
+    printk("mepc   : %p\n", (void *)regs[31]);
+    printk("mstatus: %p\n", (void *)regs[32]);
+
+    if (trap_c_callback) {
+        trap_c_callback();
+    }
+
+    while (1);
+}
+
+__attribute__((weak)) void exceptionHandler(void *context)
+{
+    trap_c((uintptr_t *)context);
+}
+
@@ -0,0 +1,164 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     dw_uart_ll.c
+ * @brief    dw uart ll driver
+ * @version  V1.0
+ * @date     18. December 2024
+ ******************************************************************************/
+#include <dw_uart_ll.h>
+
+int32_t dw_uart_wait_idle(dw_uart_regs_t *uart_base)
+{
+    uint32_t timecount = 0U;
+    int32_t ret = 0;
+
+    while ((uart_base->USR & DW_UART_USR_BUSY_SET) && (timecount < UART_BUSY_TIMEOUT)) {
+        timecount++;
+    }
+
+    if (timecount >= UART_BUSY_TIMEOUT) {
+        ret = -1;
+    }
+
+    return ret;
+}
+
+int32_t  dw_uart_wait_timeout(dw_uart_regs_t *uart_base)
+{
+    uint32_t timecount = 0U;
+    int32_t ret = 0;
+
+    while ((uart_base->LSR & 0x81U) || (uart_base->USR & 0x1U)) {
+        uart_base->LSR;
+        uart_base->RBR;
+        timecount++;
+
+        if (timecount >= UART_BUSY_TIMEOUT) {
+            ret = -1;
+            break;
+        }
+    }
+
+    if (ret == 0) {
+        ret = dw_uart_wait_idle(uart_base);
+    }
+
+    return ret;
+}
+
+int32_t dw_uart_config_baudrate(dw_uart_regs_t *uart_base, uint32_t baud, uint32_t uart_freq)
+{
+    uint32_t divisor;
+    int32_t ret = 0;
+    ret = dw_uart_wait_timeout(uart_base);
+
+    if (ret == 0) {
+        if ((uart_freq / 16) % baud >= (baud / 2))
+            divisor = (uart_freq / 16) / baud + 1;
+        else
+            divisor = (uart_freq / 16) / baud;
+
+        uart_base->LCR |= DW_UART_LCR_DLAB_EN;
+
+        /* DLL and DLH is lower 8-bits and higher 8-bits of divisor.*/
+        uart_base->DLH = (divisor >> 8U) & 0xFFU;
+        uart_base->DLL = divisor & 0xFFU;
+        /*
+         * The DLAB must be cleared after the baudrate is setted
+         * to access other registers.
+         */
+        uart_base->LCR &= (~DW_UART_LCR_DLAB_EN);
+    }
+
+    return ret;
+}
+
+int32_t  dw_uart_config_stop_bits(dw_uart_regs_t *uart_base, uint32_t stop_bits)
+{
+    int32_t ret;
+    ret = dw_uart_wait_timeout(uart_base);
+
+    if (ret == 0) {
+
+        //when data length is 5 bits, use dw_uart_config_stop_bits_2 will be 1.5 stop bits
+        if (stop_bits == 1U) {
+            dw_uart_config_stop_bits_1(uart_base);
+        } else if (stop_bits == 2U) {
+            dw_uart_config_stop_bits_2(uart_base);
+        }
+    }
+
+    //FIXME: no console output sometimes
+    mdelay(1);
+
+    return ret;
+}
+
+int32_t dw_uart_config_parity_none(dw_uart_regs_t *uart_base)
+{
+    int32_t ret;
+    ret = dw_uart_wait_timeout(uart_base);
+
+    if (ret == 0) {
+        uart_base->LCR &= (~DW_UART_LCR_PEN_EN);
+    }
+
+    return ret;
+}
+
+int32_t dw_uart_config_parity_odd(dw_uart_regs_t *uart_base)
+{
+    int32_t ret;
+
+    ret = dw_uart_wait_timeout(uart_base);
+
+    if (ret == 0) {
+        uart_base->LCR |= DW_UART_LCR_PEN_EN;
+        uart_base->LCR &= ~(DW_UART_LCR_EPS_EN);
+    }
+
+    return ret;
+}
+
+int32_t dw_uart_config_parity_even(dw_uart_regs_t *uart_base)
+{
+    int32_t ret;
+
+    ret = dw_uart_wait_timeout(uart_base);
+
+    if (ret == 0) {
+        uart_base->LCR |= DW_UART_LCR_PEN_EN;
+        uart_base->LCR |= DW_UART_LCR_EPS_EN;
+    }
+
+    return ret;
+}
+
+int32_t dw_uart_config_data_bits(dw_uart_regs_t *uart_base, uint32_t data_bits)
+{
+    int32_t ret;
+
+    ret = dw_uart_wait_timeout(uart_base);
+
+    uart_base->LCR &= 0xFCU;
+    uart_base->LCR |= (data_bits - 5U);
+
+    return ret;
+}
@@ -0,0 +1,87 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdio.h>
+#include <csi_config.h>
+#include <soc.h>
+#include <drv/uart.h>
+#include <drv/timer.h>
+#include <drv/dma.h>
+#include <drv/iic.h>
+#include <drv/rtc.h>
+#include <drv/spi.h>
+#include <drv/adc.h>
+#include <drv/gpio.h>
+#include <drv/irq.h>
+#include <drv/pin.h>
+
+const csi_perip_info_t g_soc_info[] = {
+    {DW_UART0_BASE,            DW_UART0_IRQn,            0,    DEV_DW_UART_TAG},
+    {DW_TIMER0_BASE,           TIM0_IRQn,                0,    DEV_DW_TIMER_TAG},
+    {DW_TIMER1_BASE,           TIM1_IRQn,                1,    DEV_DW_TIMER_TAG},
+    {DW_TIMER2_BASE,           TIM2_IRQn,                2,    DEV_DW_TIMER_TAG},
+    {DW_TIMER3_BASE,           TIM3_IRQn,                3,    DEV_DW_TIMER_TAG},
+#if CONFIG_SUPPORT_NMI_DEMO
+    {DW_TIMER4_BASE,           FAKE_IRQ_TIMER4,          4,    DEV_DW_TIMER_TAG},
+#endif
+#if defined(DW_DMA0_BASE)
+    {DW_DMA0_BASE,             DW_DMA0_IRQn,             0,    DEV_DW_AHB_DMA_TAG},
+    {DW_DMA0_BASE,             DW_DMA0_IRQn,             0,    DEV_DW_AXI_DMA_TAG},
+#endif
+#if defined(XT_IOPMP0_BASE)
+    {XT_IOPMP0_BASE,           IOPMP0_IRQn,              0,    DEV_XT_IOPMP_TAG},
+#endif
+    {0, 0, 0, 0}
+};
+
+const csi_dma_ch_info_t g_dma_chnum[] = {
+    {0, 8},
+    {DEV_IDX_INVALID, 0},
+};
+
+const uint16_t uart_tx_hs_num[1] = {};
+const uint16_t uart_rx_hs_num[1] = {};
+
+const csi_dma_ch_desc_t uart0_dma_ch_list[] = {
+    {0xff, 0xff}
+};
+
+const csi_dma_ch_spt_list_t dma_spt_list[] = {
+    {0xFFFFU,         0xFFU,         NULL},
+};
+
+const csi_pinmap_t gpio_pinmap[] = {
+    {0xFFFFFFFFU,   0xFFU, 0xFFU,       0xFFFFFFFFU   },
+};
+
+const csi_pinmap_t uart_pinmap[] = {
+    {0xFFFFFFFFU, 0xFFU, 0xFFU,      0xFFFFFFFFU  },
+};
+
+const csi_clkmap_t clk_map[] = {
+    {0xFFFFFFFFU, 0xFFFFU,          0xFFU}
+};
+
+const csi_dma_handshake_ctrl_t xs0_dma0_handshake_ctrl_list[] = {
+     {DEV_IDX_INVALID,    DEV_BLANK_TAG, 0xFFU, 0xFFU},
+};
+
+const csi_dma_handshake_list_t  g_handshake_list[] = {
+     {0, xs0_dma0_handshake_ctrl_list},
+     {DEV_IDX_INVALID, NULL},
+};
@@ -0,0 +1,147 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <csi_config.h>
+#include <stdbool.h>
+#include <csi_core.h>
+#include <soc.h>
+
+void soc_irq_enable(uint32_t irq_num)
+{
+    csi_vic_enable_irq((int32_t)irq_num);
+}
+
+void soc_irq_disable(uint32_t irq_num)
+{
+    csi_vic_disable_irq((int32_t)irq_num);
+}
+
+bool soc_irq_is_enabled(uint32_t irq_num)
+{
+    bool ret;
+
+    if (csi_vic_get_enabled_irq((int32_t)irq_num)) {
+        ret = true;
+    } else {
+        ret = false;
+    }
+
+    return ret;
+}
+
+void soc_irq_priority(uint32_t irq_num, uint32_t priority)
+{
+    csi_vic_set_prio((int32_t)irq_num, priority);
+}
+
+/**
+ * @brief get irq vector num
+ * @return irq no
+ */
+uint32_t soc_irq_get_irq_num(void)
+{
+    int hartid = csi_get_cpu_id();
+#if CONFIG_INTC_CLIC
+    (void) hartid;
+#if CONFIG_RISCV_SMODE
+    return (__get_SCAUSE() & 0x3FFU);
+#else
+    return (__get_MCAUSE() & 0x3FFU);
+#endif /* CONFIG_RISCV_SMODE */
+#endif /* CONFIG_INTC_CLIC */
+
+#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC
+    uint32_t num;
+#if CONFIG_RISCV_SMODE
+    uint32_t irqn = __get_SCAUSE() & 0x3FFU;
+#else
+    uint32_t irqn = __get_MCAUSE() & 0x3FFU;
+#endif /* CONFIG_RISCV_SMODE */
+    if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) {
+#if CONFIG_RISCV_SMODE
+        num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, hartid);
+#else
+        num = PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, hartid);
+#endif
+#if CONFIG_INTC_CLIC_PLIC
+        num += PLIC_IRQ_OFFSET;
+#endif
+    } else {
+        num = irqn;
+    }
+    return num;
+#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */
+
+#if CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC
+    uint32_t num;
+#if CONFIG_RISCV_SMODE
+    uint32_t irqn = __get_SCAUSE() & 0x3FFU;
+#else
+    uint32_t irqn = __get_MCAUSE() & 0x3FFU;
+#endif  /* CONFIG_RISCV_SMODE */
+    if (irqn == Machine_External_IRQn || irqn == Supervisor_External_IRQn) {
+        num = csi_aplic_read_claimi(APLIC_BASE, hartid);
+#if CONFIG_INTC_CLIC_APLIC
+        num += APLIC_IRQ_OFFSET;
+#endif
+    } else {
+        num = irqn;
+    }
+    return num;
+#endif /* CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC */
+
+#if CONFIG_INTC_IMSIC_APLIC
+    return g_handing_msi_num[hartid];
+#endif
+}
+
+void soc_irq_end(uint32_t irq_num)
+{
+#if CONFIG_INTC_CLIC
+    // DO NOTHING
+#endif /* CONFIG_INTC_CLIC */
+
+    /**
+     * If aplic works in msi-mode
+     * and the current interrupt is level-triggered
+     * need retrigger
+     */
+#if CONFIG_INTC_IMSIC_APLIC
+    extern csi_dev_t *g_cpu_irq_table[CONFIG_NR_CPUS][CONFIG_IRQ_NUM];
+    csi_aplic_retrigger_level_irq(APLIC_BASE, g_cpu_irq_table[csi_get_cpu_id()][irq_num]->irq_num);
+#endif
+
+
+#if CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC
+#if CONFIG_INTC_CLIC_PLIC
+    if (irq_num <= PLIC_IRQ_OFFSET) {
+        return;
+    }
+    irq_num -= PLIC_IRQ_OFFSET;
+#endif /* CONFIG_INTC_CLIC_PLIC */
+#if CONFIG_RISCV_SMODE
+    PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_SCLAIM, csi_get_cpu_id()) = irq_num;
+#else
+    PLIC_Hn_MSCLAIM_VAL(&PLIC->PLIC_H0_MCLAIM, csi_get_cpu_id()) = irq_num;
+#endif
+#endif /* CONFIG_INTC_PLIC || CONFIG_INTC_CLIC_PLIC */
+
+#if CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC
+    // DO NOTHING
+#endif /* CONFIG_INTC_APLIC || CONFIG_INTC_CLIC_APLIC */
+}
@@ -0,0 +1,103 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pre_main.c
+ * @brief    source file for the pre_main
+ * @version  V1.0
+ * @date     04. April 2024
+ ******************************************************************************/
+
+#include <csi_config.h>
+#include <soc.h>
+#include <board.h>
+
+extern unsigned long __heap_start;
+extern unsigned long __heap_end;
+unsigned long g_heap_start = (unsigned long)&__heap_start;
+unsigned long g_heap_end = (unsigned long)&__heap_end;
+
+extern int main(void);
+/*
+ *  The ranges of copy from/to are specified by following symbols
+ *    __erodata: LMA of start of the section to copy from. Usually end of rodata
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+void section_data_copy(void)
+{
+    extern unsigned long __erodata;
+    extern unsigned long __data_start__;
+    extern unsigned long __data_end__;
+
+    if (((unsigned long)&__erodata != (unsigned long)&__data_start__)) {
+        unsigned long src_addr = (unsigned long)&__erodata;
+        memcpy((void *)(&__data_start__), \
+               (void *)src_addr, \
+               (unsigned long)(&__data_end__) - (unsigned long)(&__data_start__));
+    }
+}
+
+void section_ram_code_copy(void)
+{
+    extern unsigned long __erodata;
+    extern unsigned long __data_start__;
+    extern unsigned long __data_end__;
+    extern unsigned long __ram_code_start__;
+    extern unsigned long __ram_code_end__;
+
+    if (((unsigned long)&__erodata != (unsigned long)&__data_start__)) {
+        unsigned long src_addr = (unsigned long)&__erodata;
+        src_addr += (unsigned long)(&__data_end__) - (unsigned long)(&__data_start__);
+        memcpy((void *)(&__ram_code_start__), \
+               (void *)src_addr, \
+               (unsigned long)(&__ram_code_end__) - (unsigned long)(&__ram_code_start__));
+    }
+}
+
+/*
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+void section_bss_clear(void)
+{
+    extern unsigned long __bss_start__;
+    extern unsigned long __bss_end__;
+
+    memset((void *)(&__bss_start__), \
+           0, \
+           (unsigned long)(&__bss_end__) - (unsigned long)(&__bss_start__));
+
+}
+
+__attribute__((weak)) void pre_main(void)
+{
+#if (!defined(CONFIG_KERNEL_RHINO)) && (!defined(CONFIG_NUTTXMM_NONE)) \
+    && (!defined(CONFIG_KERNEL_FREERTOS)) && (!defined(CONFIG_KERNEL_RTTHREAD)) \
+    && (!defined(CONFIG_KERNEL_THREADX))
+    extern void mm_heap_initialize(void);
+    mm_heap_initialize();
+#endif
+
+    main();
+}
@@ -0,0 +1,100 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <soc.h>
+#include <sys_clk.h>
+#include <drv/io.h>
+
+uint32_t g_system_clock = IHS_VALUE;
+
+#if CONFIG_BOARD_XIAOHUI_EVB
+uint32_t soc_get_cpu_freq(uint32_t idx)
+{
+#ifndef CONFIG_CPU_FREQ_HZ
+    return 50*1000000;
+#else
+    return CONFIG_CPU_FREQ_HZ;
+#endif
+}
+
+uint32_t soc_get_coretim_freq(void)
+{
+    return 25*1000000;
+}
+
+uint32_t soc_get_uart_freq(uint32_t idx)
+{
+    return 36*1000000;
+}
+
+uint32_t soc_get_timer_freq(uint32_t idx)
+{
+    return 25*1000000;
+}
+
+#else
+uint32_t soc_get_cpu_freq(uint32_t idx)
+{
+    return g_system_clock;
+}
+
+uint32_t soc_get_cur_cpu_freq(void)
+{
+    return g_system_clock;
+}
+
+uint32_t soc_get_coretim_freq(void)
+{
+    return g_system_clock;
+}
+
+uint32_t soc_get_uart_freq(uint32_t idx)
+{
+    return g_system_clock;
+}
+
+csi_error_t soc_sysclk_config(system_clk_config_t *config)
+{
+    return CSI_OK;
+}
+
+void soc_reset_uart(uint32_t idx)
+{
+}
+
+uint32_t soc_get_timer_freq(uint32_t idx)
+{
+    return g_system_clock;
+}
+#endif
+
+void soc_clk_enable(int32_t module)
+{
+}
+
+void soc_clk_disable(int32_t module)
+{
+}
+
+void soc_set_sys_freq(uint32_t val)
+{
+    g_system_clock = val;
+}
+
+
@@ -0,0 +1,58 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     weak.c
+ * @brief    source file for the weak
+ * @version  V1.0
+ * @date     04. April 2024
+ ******************************************************************************/
+
+#include <csi_config.h>
+#include <soc.h>
+#include <csi_core.h>
+
+__WEAK void soc_dcache_clean_invalid_range(unsigned long addr, uint32_t size)
+{
+    csi_dcache_clean_invalid_range((unsigned long *)addr, size);
+}
+
+__WEAK void soc_dcache_clean_invalid_all(void)
+{
+    csi_dcache_clean_invalid();
+}
+
+__WEAK void soc_dcache_invalid_range(unsigned long addr, uint32_t size)
+{
+    csi_dcache_invalid_range((unsigned long *)addr, size);
+}
+
+__WEAK void soc_dcache_clean(void)
+{
+    csi_dcache_clean();
+}
+
+__WEAK void soc_icache_invalid(void)
+{
+    csi_icache_invalid();
+}
+
+__WEAK unsigned long soc_dma_address_remap(unsigned long addr)
+{
+    return addr;
+}
@@ -0,0 +1 @@
+Just include csi_core.h!
@@ -0,0 +1,126 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CSI_RV_COMMON_H__
+#define __CSI_RV_COMMON_H__
+
+#include <stdlib.h>
+#include <stdint.h>
+
+#ifndef __ASM
+#define __ASM                   __asm     /*!< asm keyword for GNU Compiler */
+#endif
+
+#ifndef __INLINE
+#define __INLINE                inline    /*!< inline keyword for GNU Compiler */
+#endif
+
+#ifndef __ALWAYS_STATIC_INLINE
+#define __ALWAYS_STATIC_INLINE  __attribute__((always_inline)) static inline
+#endif
+
+#ifndef __STATIC_INLINE
+#define __STATIC_INLINE         static inline
+#endif
+
+#ifndef __NO_RETURN
+#define __NO_RETURN             __attribute__((__noreturn__))
+#endif
+
+#ifndef __USED
+#define __USED                  __attribute__((used))
+#endif
+
+#ifndef __WEAK
+#define __WEAK                  __attribute__((weak))
+#endif
+
+#ifndef __PACKED
+#define __PACKED                __attribute__((packed, aligned(1)))
+#endif
+
+#ifndef __PACKED_STRUCT
+#define __PACKED_STRUCT         struct __attribute__((packed, aligned(1)))
+#endif
+
+#ifndef __PACKED_UNION
+#define __PACKED_UNION          union __attribute__((packed, aligned(1)))
+#endif
+
+#ifdef __ASSEMBLY__
+#define __ASM_STR(x)    x
+#else
+#define __ASM_STR(x)    #x
+#endif
+
+#ifndef __ASSEMBLY__
+#define rv_csr_read(csr)                                   \
+    ({                                                  \
+        register unsigned long __v;                     \
+        __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \
+                             : "=r"(__v)                \
+                             :                          \
+                             : "memory");               \
+        __v;                                            \
+    })
+
+#define rv_csr_write(csr, val)                                \
+    ({                                                     \
+        unsigned long __v = (unsigned long)(val);          \
+        __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \
+                             :                             \
+                             : "rK"(__v)                   \
+                             : "memory");                  \
+    })
+
+#define rv_csr_read_set(csr, val)                                  \
+    ({                                                          \
+        unsigned long __v = (unsigned long)(val);               \
+        __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \
+                             : "=r"(__v) : "rK"(__v)            \
+                             : "memory");                       \
+        __v;                                                    \
+    })
+
+#define rv_csr_set(csr, val)                                  \
+    ({                                                     \
+        unsigned long __v = (unsigned long)(val);          \
+        __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \
+                             : : "rK"(__v)                 \
+                             : "memory");                  \
+    })
+
+#define rv_csr_read_clear(csr, val)                                \
+    ({                                                          \
+        unsigned long __v = (unsigned long)(val);               \
+        __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \
+                             : "=r"(__v) : "rK"(__v)            \
+                             : "memory");                       \
+        __v;                                                    \
+    })
+
+#define rv_csr_clear(csr, val)                                \
+    ({                                                     \
+        unsigned long __v = (unsigned long)(val);          \
+        __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \
+                             : : "rK"(__v)                 \
+                             : "memory");                  \
+    })
+#endif
+
+#endif /* __CSI_RV_COMMON_H__ */
@@ -0,0 +1,60 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/baud_calc.h
+ * @brief      Header File for the PWM capture uart bandrate Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      baud_calc
+ ******************************************************************************/
+
+#ifndef _DRV_BAUD_CALC_H_
+#define _DRV_BAUD_CALC_H_
+
+#include <stdint.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <drv/common.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Baud rate calculation(Algorithm level)
+  \param[in]   idx        PWM idx
+  \param[in]   channel    Channel num
+  \return      Error code(-1) or Baudare value
+*/
+int drv_calc_baud_adjust(uint32_t idx, uint32_t channel);
+
+/**
+  \brief       Baud rate calculation(Capture level)
+  \param[in]   idx        PWM idx
+  \param[in]   channel    Channel num
+  \return      Error code(-1) or Baudare value
+*/
+int drv_calc_baud_original(uint32_t idx, uint32_t channel);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_BAUD_CALC_H_ */
@@ -0,0 +1,50 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/clk.h
+ * @brief    Header File for CLK Driver.
+ * @version  V1.0
+ * @date     18. Mar 2020
+ ******************************************************************************/
+
+#ifndef _DRV_CLK_H_
+#define _DRV_CLK_H_
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t module;
+    uint16_t dev_tag;
+    uint8_t  idx;
+} csi_clkmap_t;
+
+void csi_clk_enable(csi_dev_t *dev);
+void csi_clk_disable(csi_dev_t *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_CLK_H_ */
+
@@ -0,0 +1,154 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/common.h
+ * @brief    Header File for Common Driver
+ * @version  V1.0
+ * @date     31. March 2020
+ * @model    common
+ ******************************************************************************/
+
+#ifndef _DRV_COMMON_H_
+#define _DRV_COMMON_H_
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+#include <drv/list.h>
+#include <drv/dev_tag.h>
+#include <csi_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef CONFIG_DEBUG_MODE
+#define CSI_ASSERT(expr)                            \
+        do {                                        \
+            if ((long)expr == (long)NULL) {   \
+                printf("PROGRAM ASSERT\n");         \
+                while(1);                           \
+            }                                       \
+        } while(0);
+#else
+#define CSI_ASSERT(expr)        ((void)0U)
+#endif
+
+#ifndef CONFIG_PARAM_NOT_CHECK
+#define CSI_PARAM_CHK(para, err)                        \
+    do                                                  \
+    {                                                   \
+        if ((unsigned long)para == (unsigned long)NULL) \
+        {                                               \
+            return (err);                               \
+        }                                               \
+    } while (0)
+
+#define CSI_PARAM_CHK_NORETVAL(para)                    \
+    do                                                  \
+    {                                                   \
+        if ((unsigned long)para == (unsigned long)NULL) \
+        {                                               \
+            return;                                     \
+        }                                               \
+    } while (0)
+#else
+#define CSI_PARAM_CHK(para, err)
+#define CSI_PARAM_CHK_NORETVAL(para)
+#endif
+
+typedef enum {
+    CSI_OK          =  0,
+    CSI_ERROR       = -1,
+    CSI_BUSY        = -2,
+    CSI_TIMEOUT     = -3,
+    CSI_UNSUPPORTED = -4
+} csi_error_t;
+
+typedef struct {
+   uint8_t    readable;
+   uint8_t    writeable;
+   uint8_t    error;
+} csi_state_t;
+
+typedef struct csi_dev csi_dev_t;
+
+#ifdef CONFIG_PM
+typedef enum {
+    PM_DEV_SUSPEND,
+    PM_DEV_RESUME,
+} csi_pm_dev_action_t;
+
+typedef enum {
+    PM_MODE_RUN                  = 0,   ///< Running mode
+    PM_MODE_SLEEP_1,                    ///< Sleep LV1 mode
+    PM_MODE_SLEEP_2,                    ///< Sleep LV2 mode
+    PM_MODE_DEEP_SLEEP_1,               ///< Deep sleep LV1 mode
+    PM_MODE_DEEP_SLEEP_2,               ///< Deep sleep LV2 mode
+} csi_pm_mode_t;
+
+typedef struct {
+    slist_t     next;
+    csi_error_t (*pm_action)(csi_dev_t *dev, csi_pm_dev_action_t action);
+    uint32_t    *reten_mem;
+    uint32_t    size;
+} csi_pm_dev_t;
+#include <drv/pm.h>
+#endif
+
+struct csi_dev {
+    unsigned long reg_base;
+    uint16_t      irq_num;
+    uint16_t      idx;
+    uint16_t      dev_tag;
+    void          (*irq_handler)(void *);
+    void          (*irq_handler2)(uint32_t irqn, void *arg);
+    void          *arg;
+#ifdef CONFIG_PM
+    csi_pm_dev_t  pm_dev;
+#endif
+};
+
+#define DEV_IDX_INVALID             0xFFFFU
+#define HANDLE_REG_BASE(handle)     (handle->dev.reg_base)
+#define HANDLE_IRQ_NUM(handle)      (handle->dev.irq_num)
+#define HANDLE_DEV_IDX(handle)      (handle->dev.idx)
+#define HANDLE_IRQ_HANDLER(handle)  (handle->dev.irq_handler)
+
+typedef struct {
+    unsigned long    reg_base;
+    uint16_t         irq_num;
+    uint16_t         idx;
+    uint16_t         dev_tag;
+} csi_perip_info_t;
+
+csi_error_t target_get(csi_dev_tag_t dev_tag, uint32_t idx, csi_dev_t *dev);
+csi_error_t target_get_optimal_dma_channel(void *dma_list, uint32_t ctrl_num, csi_dev_t *parent_dev, void *ch_info);
+csi_error_t target_get_check_dma_access(uint32_t ctrl_idx, void *srcaddr, void *dstaddr, void **dma_base_src_addr, void **dma_base_dst_addr);
+csi_error_t target_get_dma_handshake(uint16_t dma_id, uint16_t dev_id, uint16_t dev_tag, uint8_t type, uint16_t *handshake);
+void mdelay(uint32_t ms);
+void udelay(uint32_t us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_COMMON_H_ */
+
@@ -0,0 +1,136 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     crc.h
+ * @brief    Header File for CRC Driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    crc
+ ******************************************************************************/
+
+#ifndef _DRV_CRC_H_
+#define _DRV_CRC_H_
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief Compute the CRC-7 checksum of a buffer.
+ *
+ * See JESD84-A441.  Used by the MMC protocol.  Uses 0x09 as the
+ * polynomial with no reflection.  The CRC is left
+ * justified, so bit 7 of the result is bit 6 of the CRC.
+ * init = 0; poly = 0x09 refin = 0 refout = 0 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ *
+ * \return    The computed CRC7 value
+ */
+uint8_t csi_crc7_be(uint8_t crc, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-8 checksum of a buffer.
+ *  init = 0 or 0xff; poly = 0x07 refin = 0 refout = 0 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC8 value
+ */
+uint8_t csi_crc8(uint8_t crc, uint8_t *data, size_t size);
+
+/**
+ * \brief Compute the CRC-8 checksum of a buffer.
+ *  init = 0; poly = 0x31 refin = 1 refout = 1 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC8 value
+ */
+uint8_t csi_crc8_maxim(uint8_t crc, uint8_t *data, size_t size);
+
+/**
+ * \brief Compute the CRC-16 checksum of a buffer.
+ *   init = 0 or 0xffff; poly = 0x8005 refin = 1 refout = 1 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC16 without xorout
+ */
+uint16_t csi_crc16(uint16_t crc, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-16 checksum of a buffer.
+ *  init = 0; poly = 0x1021 refin = 1 refout = 1 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC16 without xorout
+ */
+uint16_t csi_crc16_ccitt(uint16_t crc, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-16 checksum of a buffer.
+ *  init = 0; poly = 0x3d65 refin = 1 refout = 1 xorout = 0xffff
+ * \param[in] init_value      Crc init value
+ * \param[in] data            Data buf to be calculate
+ * \param[in] size            Data size
+ * \return    The computed CRC16 with xorout
+ */
+uint16_t csi_crc16_dnp(uint16_t init_value, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-16 checksum of a buffer.
+ *  init = 0; poly = 0x1021 refin = 0 refout = 0 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC16 without xorout
+ */
+uint16_t csi_crc16_itu(uint16_t crc, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-32 checksum of a buffer.Little-endian by bit.
+ *  init = 0; poly = 0xEDB88320 refin = 0 refout = 0 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC32 without xorout
+ */
+uint32_t csi_crc32_le(uint32_t crc, uint8_t *data, uint32_t size);
+
+/**
+ * \brief Compute the CRC-32 checksum of a buffer.Big-endian by bit.
+ *  init = 0; poly = 0x04C11DB7 refin = 0 refout = 0 xorout = 0
+ * \param[in] crc      Crc init value or crc immediate result
+ * \param[in] data     Data buf to be calculate
+ * \param[in] size     Data size
+ * \return    The computed CRC32 without xorout
+ */
+uint32_t csi_crc32_be(uint32_t crc, uint8_t *data, uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_CRC_H_ */
@@ -0,0 +1,174 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/des.h
+ * @brief      Header File for DES Driver
+ * @version    V1.0
+ * @date       24. Oct 2022
+ * @model      des
+ ******************************************************************************/
+
+#ifndef _DRV_DES_H_
+#define _DRV_DES_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+\brief DES key-len-bits type
+*/
+typedef enum {
+    DES_KEY_LEN_BITS_64        = 0,        /*64 Data bits*/
+    DES_KEY_LEN_BITS_128,                  /*128 Data bits*/
+    DES_KEY_LEN_BITS_192,                  /*192 Data bits*/
+} csi_des_key_bits_t;
+
+/**
+\brief DES Ctrl Block
+*/
+typedef struct {
+    csi_dev_t               dev;
+    void                    *priv;
+} csi_des_t;
+
+/**
+  \brief       Initialize DES interface. Initializes the resources needed for the DES interface
+  \param[in]   des    Handle to operate
+  \param[in]   idx    Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_des_init(csi_des_t *des, uint32_t idx);
+
+/**
+  \brief       De-initialize DES interface. Stops operation and releases the software resources used by the interface
+  \param[in]   des    Dandle to operate
+  \return      None
+*/
+void csi_des_uninit(csi_des_t *des);
+
+/**
+  \brief       Set encrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_encrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       Set decrypt key
+  \param[in]   des        Handle to operate
+  \param[in]   key        Pointer to the key buf
+  \param[in]   key_len    Pointer to \ref csi_des_key_bits_t
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_set_decrypt_key(csi_des_t *des, void *key, csi_des_key_bits_t key_len);
+
+/**
+  \brief       DES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       DES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       DES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_des_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+/**
+  \brief       TDES ecb encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_encrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES ecb decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_ecb_decrypt(csi_des_t *des, void *in, void *out, uint32_t size);
+
+/**
+  \brief       TDES cbc encrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_encrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv) ;
+
+/**
+  \brief       TDES cbc decrypt
+  \param[in]   des     Handle to operate
+  \param[in]   in      Pointer to the source data
+  \param[out]  out     Pointer to the result data
+  \param[in]   size    The source data size
+  \param[in]   iv      Init vector
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_tdes_cbc_decrypt(csi_des_t *des, void *in, void *out, uint32_t size, void *iv);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_DES_H_ */
@@ -0,0 +1,83 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv_fft.h
+ * @brief    header file for gpio driver
+ * @version  V1.0
+ * @date     11. Nov 2017
+ * @model    fft
+ ******************************************************************************/
+
+#ifndef _CSI_FFT_H_
+#define _CSI_FFT_H_
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+//#include <drv_common.h>
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+typedef enum {
+	// 512-point FFT
+	CSKY_MCA_FFT_LEN_512 = 0x1,
+	// 256-point FFT
+	CSKY_MCA_FFT_LEN_256 = 0x2,
+	// 128-point FFT
+	CSKY_MCA_FFT_LEN_128 = 0x4,
+	// 64-point FFT
+	CSKY_MCA_FFT_LEN_64 = 0x8,
+	// 32-point FFT
+	CSKY_MCA_FFT_LEN_32 = 0x10,
+	// 16-point FFT
+	CSKY_MCA_FFT_LEN_16 = 0x20,
+} csky_mca_fft_len_t;
+
+/* 8-bit fixed-point numeric type in user-defined format */
+typedef int8_t fxp8_t;
+/* 16-bit fixed-point numeric type in user-defined format */
+typedef int16_t fxp16_t;
+/* 24-bit fixed-point numeric type in user-defined format */
+typedef int32_t fxp24_t;
+/* 32-bit fixed-point numeric type in user-defined format */
+typedef int32_t fxp32_t;
+/* 64-bit fixed-point numeric type in user-defined format */
+typedef int64_t fxp64_t;
+
+/* 8-bit fixed-point numeric type in 1.0.7 format */
+typedef fxp8_t q7_t;
+/* 16-bit fixed-point numeric type in 1.0.15 format */
+typedef fxp16_t q15_t;
+/* 32-bit fixed-point numeric type in 1.15.16 format */
+typedef fxp32_t q16_t;
+
+void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output);
+void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_FFT_H_ */
@@ -0,0 +1,92 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/ecdh.h
+ * @brief      Header File for ECDH Driver
+ * @version    V1.0
+ * @date       9. May 2023
+ * @model      ecdh
+ ******************************************************************************/
+
+#ifndef _DRV_ECDH_H_
+#define _DRV_ECDH_H_
+
+#include <drv/common.h>
+#include <drv/ecdsa.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+\brief ECDH Ctrl Block
+*/
+typedef struct {
+    csi_dev_t       dev;
+    void            *priv;
+} csi_ecdh_t;
+
+/**
+  \brief       Initialize ECDH interface. Initializes the resources needed for the ECDH interface
+  \param[in]   ecdh    Handle to operate
+  \param[in]   idx    Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdh_init(csi_ecdh_t *ecdh, uint32_t idx);
+
+/**
+  \brief       De-initialize ECDH interface. Stops operation and releases the software resources used by the interface
+  \param[in]   ecdh    Dandle to operate
+  \return      None
+*/
+void csi_ecdh_uninit(csi_ecdh_t *ecdh);
+
+/**
+  \brief       Load curve param to engin
+  \param[in]   ecdh      Handle to operate
+  \param[in]   type       Pointer to \ref csi_curve_type_t
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdh_load_curve(csi_ecdh_t *ecdh, csi_curve_type_t type);
+
+/**
+  \brief       ECDH generate key pair
+  \param[in]   ecdh        Handle to operate
+  \param[out]  prikey      Pointer to the private key buf
+  \param[out]  pubkey      Pointer to the public key buf
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_ecdh_gen_keypair(csi_ecdh_t *ecdh, uint8_t *prikey, uint8_t *pubkey);
+
+/**
+  \brief       ECDH generate secret key
+  \param[in]   ecdh        Handle to operate
+  \param[in]   prikey      Pointer to the private key buf
+  \param[in]   pubkey      Pointer to the public key buf
+  \param[out]  sk          Pointer to the secret key buf
+  \param[out]  sk_len      The secret key length
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_ecdh_calc_secret(csi_ecdh_t *ecdh, const uint8_t *privkey, const uint8_t *pubkey, uint8_t *sk, uint32_t *sk_len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_ECDH_H_ */
@@ -0,0 +1,112 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/ecdsa.h
+ * @brief      Header File for ECDSA Driver
+ * @version    V1.0
+ * @date       9. May 2023
+ * @model      ecdsa
+ ******************************************************************************/
+
+#ifndef _DRV_ECDSA_H_
+#define _DRV_ECDSA_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+\brief EC curve type
+*/
+typedef enum {
+    CSI_CURVES_SECP256K1 =  0U, /* SECG curve over a 256 bit prime field */
+    CSI_CURVES_SECP384R1,       /* NIST/SECG curve over a 384 bit prime field */
+    CSI_CURVES_SECP521R1,       /* NIST/SECG curve over a 521 bit prime field */
+    CSI_CURVES_BRAINPOOL256R1, 	/* RFC 5639 curve over a 256 prime field */
+    CSI_CURVES_BRAINPOOL256T1, 	/* RFC 5639 curve over a 256 prime field */
+    CSI_CURVES_BRAINPOOL512R1, 	/* RFC 5639 curve over a 512 prime field */
+    CSI_CURVES_BRAINPOOL512T1, 	/* RFC 5639 curve over a 512 prime field */
+} csi_curve_type_t;
+
+/**
+\brief ECDSA Ctrl Block
+*/
+typedef struct {
+    csi_dev_t       dev;
+    void            *priv;
+} csi_ecdsa_t;
+
+/**
+  \brief       Initialize ECDSA interface. Initializes the resources needed for the ECDSA interface
+  \param[in]   ecdsa    Handle to operate
+  \param[in]   idx    Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdsa_init(csi_ecdsa_t *ecdsa, uint32_t idx);
+
+/**
+  \brief       De-initialize ECDSA interface. Stops operation and releases the software resources used by the interface
+  \param[in]   ecdsa    Dandle to operate
+  \return      None
+*/
+void csi_ecdsa_uninit(csi_ecdsa_t *ecdsa);
+
+/**
+  \brief       Load curve param to engin
+  \param[in]   ecdsa      Handle to operate
+  \param[in]   type       Pointer to \ref csi_curve_type_t
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_ecdsa_load_curve(csi_ecdsa_t *ecdsa, csi_curve_type_t type);
+
+/**
+  \brief       Ecdsa Sign
+  \param[in]   ecdsa        Handle to operate
+  \param[in]   prikey       Pointer to the private key buf
+  \param[in]   prikey_len   The private key length
+  \param[in]   dgst         Pointer to the digest buf
+  \param[in]   dgst_len     The digest length
+  \param[out]  sig          Pointer to the signature buf
+  \param[out]  sig_len      The signature length
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_ecdsa_sign(csi_ecdsa_t *ecdsa,  const uint8_t *prikey,  uint32_t prikey_len, 
+                                const uint8_t *dgst, uint32_t dgst_len, uint8_t *sig, uint32_t *sig_len);
+
+/**
+  \brief       Ecdsa Verify
+  \param[in]   ecdsa        Handle to operate
+  \param[in]   pubkey       Pointer to the public key buf
+  \param[in]   prikey_len   The public key length
+  \param[in]   dgst         Pointer to the digest buf
+  \param[in]   dgst_len     The digest length
+  \param[in]   sig          Pointer to the signature buf
+  \param[in]   sig_len      The signature length
+  \return      Error code \ref Csi_error_t
+*/
+csi_error_t csi_ecdsa_verify(csi_ecdsa_t *ecdsa, const uint8_t *pubkey, uint32_t pubkey_len, 
+                                const uint8_t *dgst, uint32_t gst_len,  const uint8_t *sig,  uint32_t sig_len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_ECDSA_H_ */
@@ -0,0 +1,140 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     eflash.h
+ * @brief    header file for eflash driver
+ * @version  V1.0
+ * @date     02. June 2017
+ * @model    eflash
+ ******************************************************************************/
+#ifndef _DRV_EFLASH_H_
+#define _DRV_EFLASH_H_
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+\brief Flash information
+*/
+typedef struct {
+    uint32_t          flash_size;         ///< Chip End address (start+size-1)
+    uint32_t          sector_size;        ///< Uniform sector size in bytes
+    uint32_t          erased_value;       ///< erased value
+} csi_eflash_info_t;
+
+/**
+\brief Flash Status
+*/
+typedef struct {
+    uint32_t busy  : 1;                   ///< Flash busy flag
+    uint32_t error : 1;                   ///< Read/Program/Erase error flag (cleared on start of next operation)
+} eflash_status_t;
+
+/// definition for eflash handle.
+typedef struct {
+    csi_dev_t           dev;
+    void                *arg;
+    csi_eflash_info_t   eflashinfo;
+    uint16_t            prog;
+    uint16_t            erase;
+    void                *priv;
+} csi_eflash_t;
+
+// Function documentation
+
+/**
+  \brief       Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function
+  \param[in]   eflash  eflash handle to operate.
+  \param[in]   idx  device id
+  \param[in]   arg  User can define it by himself as callback's param
+  \return      error code
+*/
+csi_error_t csi_eflash_init(csi_eflash_t *eflash, int32_t idx, void *arg);
+
+/**
+  \brief       De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface
+  \param[in]   eflash  eflash handle to operate.
+  \return      error code
+*/
+csi_error_t csi_eflash_uninit(csi_eflash_t *eflash);
+
+/**
+  \brief       Read data from Flash.
+  \param[in]   eflash  eflash handle to operate.
+  \param[in]   offset  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   size   Number of data items to read.
+  \return      error code
+*/
+csi_error_t csi_eflash_read(csi_eflash_t *eflash, uint32_t offset, void *data, uint32_t size);
+
+/**
+  \brief       Program data to Flash.
+  \param[in]   eflash  eflash handle to operate.
+  \param[in]   offset  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash.
+  \param[in]   size   Number of data items to program.
+  \return      error code
+*/
+csi_error_t csi_eflash_program(csi_eflash_t *eflash, uint32_t offset, const void *data, uint32_t size);
+
+/**
+  \brief       Erase Flash Sector.
+  \param[in]   eflash  eflash handle to operate.
+  \param[in]   offset  flash address, flash address need sector size aligned
+  \param[in]   size  erase size
+  \return      error code
+*/
+csi_error_t csi_eflash_erase(csi_eflash_t *eflash, uint32_t offset,uint32_t size);
+
+/**
+  \brief       Erase whole flash
+  \param[in]   eflash  eflash handle to operate.
+  \return      error code
+*/
+csi_error_t csi_eflash_erase_chip(csi_eflash_t *eflash);
+
+/**
+  \brief       Get Flash information.
+  \param[in]   eflash  eflash handle to operate.
+*/
+void csi_eflash_dev_info(csi_eflash_t *eflash,csi_eflash_info_t *eflash_info);
+
+/**
+  \brief       enable eflash power manage
+  \param[in]   eflash  eflash handle to operate.
+  \return      error code
+*/
+csi_error_t csi_eflash_enable_pm(csi_eflash_t *eflash);
+
+/**
+  \brief       disable eflash power manage
+  \param[in]   eflash  eflash handle to operate.
+*/
+void csi_eflash_disable_pm(csi_eflash_t *eflash);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_EFLASH_H_ */
@@ -0,0 +1,93 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/efuse.h
+ * @brief    Header File for EFUSE Driver
+ * @version  V1.0
+ * @date     22. Mar 2020
+ * @model    efuse
+ ******************************************************************************/
+#ifndef _DEV_EFUSEC_H_
+#define _DEV_EFUSEC_H_
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t            start;              ///< Efuse start address
+    uint32_t            end;                ///< Efuse end address
+    uint32_t            size;                ///< Efuse size
+} csi_efuse_info_t;
+
+typedef struct {
+    csi_dev_t           dev;
+    csi_efuse_info_t    info;
+} csi_efuse_t;
+
+/**
+  \brief       Initialize EFUSEC Interface. 1. Initializes the resources needed for the EFUSEC interface
+  \param[in]   idx  Device id
+  \return      Error code
+*/
+csi_error_t csi_efuse_init(csi_efuse_t *efuse, int32_t idx);
+
+/**
+  \brief       De-initialize EFUSEC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   efuse  Efuse efuse to operate.
+  \return      None
+*/
+void csi_efuse_uninit(csi_efuse_t *efuse);
+
+/**
+  \brief       Read data from Efuse.
+  \param[in]   efuse Efuse handle to operate.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Efuse.
+  \param[in]   size  Number of data items to read.
+  \return      Number of data items read or error code
+*/
+int32_t csi_efuse_read(csi_efuse_t *efuse, uint32_t addr, void *data, uint32_t size);
+
+/**
+  \brief       Program data to Efuse.
+  \param[in]   efuse Efuse handle to operate.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Efuse.
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or error code
+*/
+int32_t csi_efuse_program(csi_efuse_t *efuse, uint32_t addr, const void *data, uint32_t size);
+
+/**
+  \brief       Get Efuse information.
+  \param[in]   efuse  Efuse handle to operate.
+  \param[out]  info   Efuse info \refs csi_efuse_info_t.
+  \return      Error code
+*/
+csi_error_t csi_efuse_get_info(csi_efuse_t *efuse, csi_efuse_info_t *info);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_EFUSEC_H_ */
@@ -0,0 +1,102 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv_etb.h
+ * @brief    header file for event trigger driver
+ * @version  V1.0
+ * @date     27. octorber 2017
+ * @model    etb
+ ******************************************************************************/
+
+#ifndef _DRV_ETB_H_
+#define _DRV_ETB_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ETB_HARDWARE_TRIG  = 0,           ///< etb channel inout is hardware trigger.
+    ETB_SOFTWARE_TRIG                 ///< etb channel inout is software trigger.
+} csi_etb_trig_mode_t;
+
+typedef enum {
+    ETB_CH_ONE_TRIGGER_ONE  = 0,      ///< one device trig one deivce
+    ETB_CH_ONE_TRIGGER_MORE,          ///< one device trig two for more device
+    ETB_CH_MORE_TRIGGER_ONE           ///< two or more device trig one deivce
+} csi_etb_ch_type_t;
+
+typedef struct {
+    uint8_t               src_ip;     ///< a specific number represent a location in an source trigger location map to trigger other ip(s).
+    uint8_t               dst_ip;     ///< a specific number represent an location in an dest trigger map to wait signal(s) from source ip(s) or location(s).
+    csi_etb_trig_mode_t   trig_mode;  ///< the input source is hardware trigger or software trigger.
+    csi_etb_ch_type_t     ch_type;    ///< channel type
+} csi_etb_config_t;
+
+/**
+  \brief       Init the etb device
+  \return      error code
+*/
+csi_error_t csi_etb_init(void);
+
+/**
+  \brief       Uninit the etb device
+  \return      none
+*/
+void csi_etb_uninit(void);
+
+/**
+  \brief       alloc an etb channel
+  \param[in]   ch_mode    etb channel work mode
+  \return      channel id or CSI_ERROR
+*/
+int32_t csi_etb_ch_alloc(csi_etb_ch_type_t ch_type);
+
+/**
+  \brief       free an etb channel
+  \param[in]   ch_id      etb channel work mode
+  \return      none
+*/
+void csi_etb_ch_free(int32_t ch_id);
+
+/**
+  \brief       config etb channel
+  \param[in]   ch_id      etb channel id
+  \param[in]   config     the config structure for etb channel
+  \return      csi error code
+*/
+csi_error_t csi_etb_ch_config(int32_t ch_id, csi_etb_config_t *config);
+
+/**
+  \brief       start an etb channel
+  \param[in]   ch_id      etb channel id
+  \return      none
+*/
+void csi_etb_ch_start(int32_t ch_id);
+
+/**
+  \brief       stop an etb channel
+  \param[in]   etb        etb channel id
+  \return      none
+*/
+void csi_etb_ch_stop(int32_t ch_id);
+
+#endif /* _CSI_ETB_H_ */
@@ -0,0 +1,111 @@
+/**
+ * Copyright (C) 2016 CSI Project. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef _CSI_NET_H_
+#define _CSI_NET_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_ETH_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
+
+/**
+\brief Driver Version
+*/
+typedef struct csi_driver_version {
+    uint16_t api;                         ///< API version
+    uint16_t drv;                         ///< Driver version
+} csi_drv_version_t;
+
+/* General return codes */
+#define CSI_ETH_OK                 0 ///< Operation succeeded
+#define CSI_ETH_ERROR             CSI_DRV_ERRNO_ETH_BASE+1 ///< Unspecified error
+#define CSI_ETH_ERROR_BUSY        CSI_DRV_ERRNO_ETH_BASE+2 ///< Driver is busy
+#define CSI_ETH_ERROR_TIMEOUT     CSI_DRV_ERRNO_ETH_BASE+3 ///< Timeout occurred
+#define CSI_ETH_ERROR_UNSUPPORTED CSI_DRV_ERRNO_ETH_BASE+4 ///< Operation not supported
+#define CSI_ETH_ERROR_PARAMETER   CSI_DRV_ERRNO_ETH_BASE+5 ///< Parameter error
+#define CSI_ETH_ERROR_SPECIFIC    CSI_DRV_ERRNO_ETH_BASE+6 ///< Start of driver specific errors
+
+/**
+\brief General power states
+*/
+typedef enum eth_power_state {
+    CSI_ETH_POWER_OFF,                        ///< Power off: no operation possible
+    CSI_ETH_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+    CSI_ETH_POWER_FULL                        ///< Power on: full operation at maximum performance
+} eth_power_state_t;
+
+/**
+\brief Ethernet Media Interface type
+*/
+#define CSI_ETH_INTERFACE_MII           (0)     ///< Media Independent Interface (MII)
+#define CSI_ETH_INTERFACE_RMII          (1)     ///< Reduced Media Independent Interface (RMII)
+#define CSI_ETH_INTERFACE_SMII          (2)     ///< Serial Media Independent Interface (SMII)
+
+/**
+\brief Ethernet link speed
+*/
+#define CSI_ETH_SPEED_10M               (0)     ///< 10 Mbps link speed
+#define CSI_ETH_SPEED_100M              (1)     ///< 100 Mbps link speed
+#define CSI_ETH_SPEED_1G                (2)     ///< 1 Gpbs link speed
+
+/**
+\brief Ethernet duplex mode
+*/
+#define CSI_ETH_DUPLEX_HALF             (0)     ///< Half duplex link
+#define CSI_ETH_DUPLEX_FULL             (1)     ///< Full duplex link
+
+/**
+\brief Ethernet auto-negotiation
+*/
+#define CSI_ETH_AUTONEG_DISABLE         (0)     ///< Disable auto-negotiation
+#define CSI_ETH_AUTONEG_ENABLE          (1)     ///< Enable auto-negotiation
+
+/**
+\brief Ethernet link state
+*/
+typedef enum eth_link_state {
+    ETH_LINK_DOWN,                    ///< Link is down
+    ETH_LINK_UP                       ///< Link is up
+} eth_link_state_t;
+
+/**
+\brief Ethernet link information
+*/
+typedef volatile struct eth_link_info {
+    uint32_t speed              : 2;                ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
+    uint32_t duplex             : 1;                ///< Duplex mode: 0= Half, 1= Full
+    uint32_t autoneg            : 1;                ///< Set the interface to Auto Negotiation mode of transmission parameters
+    uint32_t loopback           : 1;                ///< Set the interface into a Loop-back test mode
+    uint32_t isolation          : 1;                ///< Set to indicate electrical isolation of PHY interface from MII/RMII interface
+    uint32_t reserved           : 26;
+} eth_link_info_t;
+
+/**
+\brief Ethernet MAC Address
+*/
+typedef struct eth_mac_addr {
+    uint8_t b[6];                         ///< MAC Address (6 bytes), MSB first
+} eth_mac_addr_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CSI_NET_H_ */
+
@@ -0,0 +1,124 @@
+/**
+ * Copyright (C) 2016 CSI Project. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _CSI_ETH_PHY_H_
+#define _CSI_ETH_PHY_H_
+
+#include "drv/eth.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void *eth_phy_handle_t;
+
+#define CSI_ETH_PHY_API_VERSION CSI_ETH_VERSION_MAJOR_MINOR(2,1)  /* API version */
+
+
+#define _CSI_Driver_ETH_PHY_(n)      Driver_ETH_PHY##n
+#define  CSI_Driver_ETH_PHY_(n) _CSI_Driver_ETH_PHY_(n)
+
+
+/****** Ethernet PHY Mode *****/
+#define CSI_ETH_PHY_SPEED_Pos            0
+#define CSI_ETH_PHY_SPEED_Msk           (3UL                 << CSI_ETH_PHY_SPEED_Pos)
+#define CSI_ETH_PHY_SPEED_10M           (CSI_ETH_SPEED_10M   << CSI_ETH_PHY_SPEED_Pos)  ///< 10 Mbps link speed
+#define CSI_ETH_PHY_SPEED_100M          (CSI_ETH_SPEED_100M  << CSI_ETH_PHY_SPEED_Pos)  ///< 100 Mbps link speed
+#define CSI_ETH_PHY_SPEED_1G            (CSI_ETH_SPEED_1G    << CSI_ETH_PHY_SPEED_Pos)  ///< 1 Gpbs link speed
+#define CSI_ETH_PHY_DUPLEX_Pos           2
+#define CSI_ETH_PHY_DUPLEX_Msk          (1UL                 << CSI_ETH_PHY_DUPLEX_Pos)
+#define CSI_ETH_PHY_DUPLEX_HALF         (CSI_ETH_DUPLEX_HALF << CSI_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
+#define CSI_ETH_PHY_DUPLEX_FULL         (CSI_ETH_DUPLEX_FULL << CSI_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
+#define CSI_ETH_PHY_AUTO_NEGOTIATE      (1UL << 3)                                      ///< Auto Negotiation mode
+#define CSI_ETH_PHY_LOOPBACK            (1UL << 4)                                      ///< Loop-back test mode
+#define CSI_ETH_PHY_ISOLATE             (1UL << 5)                                      ///< Isolate PHY from MII/RMII interface
+
+typedef int32_t (*csi_eth_phy_read_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);   ///< Read Ethernet PHY Register.
+typedef int32_t (*csi_eth_phy_write_t)(uint8_t phy_addr, uint8_t reg_addr, uint16_t  data);  ///< Write Ethernet PHY Register.
+
+typedef struct {
+    csi_eth_phy_read_t  phy_read;
+    csi_eth_phy_write_t phy_write;
+    eth_link_info_t     link_info;
+} eth_phy_priv_t;
+
+// Function documentation
+/**
+  \brief       Get driver version.
+  \param[in]   handle  ethernet phy handle
+  \return      driver version
+*/
+csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle);
+
+/**
+  \brief       Initialize Ethernet PHY Device.
+  \param[in]   fn_read
+  \param[in]   fn_write
+  \return      ethernet phy handle
+*/
+eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write);
+
+/**
+  \brief       De-initialize Ethernet PHY Device.
+  \param[in]   handle  ethernet phy handle
+  \return      error code
+*/
+int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle);
+
+/**
+  \brief       Control Ethernet PHY Device Power.
+  \param[in]   handle  ethernet phy handle
+  \param[in]   state  Power state
+  \return      error code
+*/
+int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state);
+
+/**
+  \brief       Set Ethernet Media Interface.
+  \param[in]   handle  ethernet phy handle
+  \param[in]   interface  Media Interface type
+  \return      error code
+*/
+int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface);
+
+/**
+  \brief       Set Ethernet PHY Device Operation mode.
+  \param[in]   handle  ethernet phy handle
+  \param[in]   mode  Operation Mode
+  \return      error code
+*/
+int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode);
+
+/**
+  \brief       Get Ethernet PHY Device Link state.
+  \param[in]   handle  ethernet phy handle
+  \return      current link status \ref eth_link_state_t
+*/
+eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle);
+
+/**
+  \brief       Get Ethernet PHY Device Link information.
+  \param[in]   handle  ethernet phy handle
+  \return      current link parameters \ref eth_link_info_t
+*/
+eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
@@ -0,0 +1,87 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/fft.h
+ * @brief    Header File for FFT Driver
+ * @version  V1.0
+ * @date     11. Nov 2020
+ * @model    fft
+ ******************************************************************************/
+
+#ifndef _DRV_FFT_H_
+#define _DRV_FFT_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ///< 512-point FFT
+    CSKY_MCA_FFT_LEN_512 = 0x1,
+    ///< 256-point FFT
+    CSKY_MCA_FFT_LEN_256 = 0x2,
+    ///< 128-point FFT
+    CSKY_MCA_FFT_LEN_128 = 0x4,
+    ///< 64-point FFT
+    CSKY_MCA_FFT_LEN_64 = 0x8,
+    ///< 32-point FFT
+    CSKY_MCA_FFT_LEN_32 = 0x10,
+    ///< 16-point FFT
+    CSKY_MCA_FFT_LEN_16 = 0x20,
+} csky_mca_fft_len_t;
+
+/* 8-bit fixed-point numeric type in user-defined format */
+typedef int8_t fxp8_t;
+
+/* 16-bit fixed-point numeric type in user-defined format */
+typedef int16_t fxp16_t;
+
+/* 24-bit fixed-point numeric type in user-defined format */
+typedef int32_t fxp24_t;
+
+/* 32-bit fixed-point numeric type in user-defined format */
+typedef int32_t fxp32_t;
+
+/* 64-bit fixed-point numeric type in user-defined format */
+typedef int64_t fxp64_t;
+
+/* 8-bit fixed-point numeric type in 1.0.7 format */
+typedef fxp8_t q7_t;
+
+/* 16-bit fixed-point numeric type in 1.0.15 format */
+typedef fxp16_t q15_t;
+
+/* 32-bit fixed-point numeric type in 1.15.16 format */
+typedef fxp32_t q16_t;
+
+void csky_mca_rfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp32_t *output);
+void csky_mca_cfft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_rifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_cifft_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, fxp32_t *output);
+void csky_mca_power_spectrum_fxp32(csky_mca_fft_len_t fft_len, const fxp32_t *input, size_t input_size, fxp64_t *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_FFT_H_ */
@@ -0,0 +1,144 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/gpio_pin.h
+ * @brief    Header File for GPIO PIN Driver
+ * @version  v1.0
+ * @date     2020-06-28
+ * @note     Only one of gpio or gpio_pin interface can be selected
+ ******************************************************************************/
+
+#ifndef _DRV_GPIO_PIN_H_
+#define _DRV_GPIO_PIN_H_
+
+#include <soc.h>
+#include <csi_core.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <drv/common.h>
+#include <drv/gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \struct   csi_gpio_pin_t
+ * \brief    GPIO PIN control block
+ */
+
+typedef struct csi_gpio_pin csi_gpio_pin_t;
+struct csi_gpio_pin {
+    csi_gpio_t      *gpio;
+    uint32_t        pin_idx;
+    void (*callback)(csi_gpio_pin_t *pin, void *arg);
+    void            *arg;
+};
+
+/**
+  \brief       Initialize GPIO pin handle
+  \param[in]   pin         GPIO pin handle
+  \param[in]   pin_name    GPIO pin name
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_init(csi_gpio_pin_t *pin, pin_name_t pin_name);
+
+/**
+  \brief       De-initialize GPIO pin
+  \param[in]   pin         GPIO pin handle
+  \return      None
+*/
+void csi_gpio_pin_uninit(csi_gpio_pin_t *pin);
+
+/**
+  \brief       Attach the interrupt callback to the GPIO pin
+  \param[in]   pin         GPIO pin handle
+  \param[in]   callback    Callback function
+  \param[in]   arg         User param passed to callback
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_attach_callback(csi_gpio_pin_t *pin, void *callback, void *arg);
+
+/**
+  \brief       Config pin direction
+  \param[in]   pin         GPIO pin handle
+  \param[in]   dir         \ref csi_gpio_dir_t
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_dir(csi_gpio_pin_t *pin, csi_gpio_dir_t dir);
+
+/**
+  \brief       Config pin mode
+  \param[in]   pin        GPIO pin handle
+  \param[in]   mode        \ref csi_gpio_mode_t
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_mode(csi_gpio_pin_t *pin, csi_gpio_mode_t mode);
+
+/**
+  \brief       Config pin irq params
+  \param[in]   pin        GPIO pin handle
+  \param[in]   mode        Interrupt trigger mode \ref csi_gpio_irq_mode_t
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_irq_mode(csi_gpio_pin_t *pin, csi_gpio_irq_mode_t mode);
+
+/**
+  \brief       Enable or disable gpio pin interrupt
+  \param[in]   pin        GPIO pin handle
+  \param[in]   enable      0:disable  1:enable
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_irq_enable(csi_gpio_pin_t *pin, bool enable);
+
+/**
+  \brief       Set debounce of pin when pin configed as input
+  \param[in]   pin        GPIO pin handle
+  \param[in]   enbale      0: disable   1:enable
+  \return      Error code
+*/
+csi_error_t csi_gpio_pin_debounce(csi_gpio_pin_t *pin, bool enable);
+
+/**
+  \brief       Set one or zero to specified pin
+  \param[in]   pin        GPIO pin handle
+  \param[in]   value       Value to be set \ref csi_gpio_pin_state_t
+  \return      None
+*/
+void csi_gpio_pin_write(csi_gpio_pin_t *pin, csi_gpio_pin_state_t value);
+
+/**
+  \brief       Toggle output pin value,ex.if previous value is 1, then output 0
+  \param[in]   pin        GPIO pin handle
+  \return      None
+*/
+void csi_gpio_pin_toggle(csi_gpio_pin_t *pin);
+
+/**
+  \brief       Get the value of specified GPIO pin
+  \param[in]   pin        GPIO port handle
+  \return      gpio pin state, \ref csi_gpio_pin_state_t
+*/
+csi_gpio_pin_state_t csi_gpio_pin_read(csi_gpio_pin_t *pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _GPIO_PIN_H_*/
@@ -0,0 +1,122 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     drv/hmac.h
+ * @brief    Header File for HMAC
+ * @version  V1.0
+ * @date     27. Apri 2023
+ * @model    hmac
+ ******************************************************************************/
+#ifndef _DRV_HMAC_H_
+#define _DRV_HMAC_H_
+
+#include <drv/common.h>
+#include <drv/dma.h>
+#include <drv/sha.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****** HMAC Event ******/
+typedef enum {
+    HMAC_EVENT_COMPLETE    = 0U,           /* Calculate completed */
+    HMAC_EVENT_ERROR                       /* Calculate error */
+} csi_hmac_event_t;
+
+/****** HMAC Context ******/
+typedef struct {
+    csi_sha_mode_t   mode;                 /* SHA mode */
+    uint32_t         total[2];             /* Number of bytes processed */
+    uint8_t          buffer[128];          /* Data block being processed */
+} csi_hmac_context_t;
+
+/****** HMAC Ctrl ******/
+typedef struct csi_hmac {
+    csi_dev_t   dev;
+    void        *priv;
+}csi_hmac_t;
+
+/**
+  \brief       Initialize MAC Interface. Initializes the resources needed for the MAC interface
+  \param[in]   mac       operate handle.
+  \param[in]   idx       index of mac
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_init(csi_hmac_t *mac, uint32_t idx);
+
+/**
+  \brief       De-initialize MAC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   mac       mac handle to operate.
+  \return      none
+*/
+void csi_hmac_uninit(csi_hmac_t *mac);
+
+/**
+  \brief       MAC set key function.
+  \param[in]   mac       mac handle to operate.
+  \param[in]   key       Pointer to the mac key.
+  \param[in]   key_len   Length of key.
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_set_key(csi_hmac_t *mac, uint8_t *key, uint32_t key_len);
+
+/**
+  \brief       MAC start operation function.
+  \param[in]   mac        mac handle to operate.
+  \param[in]   context 	  mac context pointer.
+  \param[in]   mode 	  sc_sha_mode_t.
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_start(csi_hmac_t *mac, csi_hmac_context_t *context, csi_sha_mode_t mode);
+
+/**
+  \brief       MAC start operation function.
+  \param[in]   mac        mac handle to operate.
+  \param[in]   msg        Pointer to the mac input message.
+  \param[in]   msg_len    Length of msg.
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_update(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *msg, uint32_t msg_len);
+
+/**
+  \brief       MAC start operation function.
+  \param[in]   mac        mac handle to operate.
+  \param[out]  out        mac buffer, malloc by caller.
+  \param[out]  out_len    out mac length,
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_finish(csi_hmac_t *mac, csi_hmac_context_t *context, uint8_t *out, uint32_t *out_len);
+
+/**
+  \brief       MAC cacl operation function.
+  \param[in]   mac        mac handle to operate.
+  \param[in]   mode 	  sc_sha_mode_t.
+  \param[in]   msg        Pointer to the mac input message.
+  \param[in]   msg_len    Length of msg.
+  \param[out]  out        mac buffer, malloc by caller.
+  \param[out]  out_len    out mac length,
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_hmac_calc(csi_hmac_t *mac, csi_sha_mode_t mode, uint8_t *msg,
+                            uint32_t msg_len, uint8_t *out, uint32_t *out_len);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SC_MAC_H_ */
@@ -0,0 +1,178 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/intc.h
+ * @brief    Header File for INTC Driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    intc
+ ******************************************************************************/
+
+#ifndef _DRV_INTC_H_
+#define _DRV_INTC_H_
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+typedef enum int_trigger_mode_t {
+    INT_MODE_LOW_LEVEL,
+    INT_MODE_HIGH_LEVEL,
+    INT_MODE_RISING_EDGE,
+    INT_MODE_FALLING_EDGE,
+    INT_MODE_DOUBLE_EDGE,
+} int_trigger_mode_t;
+
+/**
+  \brief    Initialize the INTC interrupt controller
+ */
+void csi_intc_init(void);
+
+/**
+  \brief        Enable External Interrupt
+  \details      Enables a device-specific interrupt in the INTC interrupt controller.
+  \param[in]    IRQn  External interrupt number. Value cannot be negative.
+ */
+void csi_intc_enable_irq(int32_t IRQn);
+
+/**
+  \brief        Disable External Interrupt
+  \details      Disables a device-specific interrupt in the INTC interrupt controller.
+  \param[in]    IRQn  External interrupt number. Value cannot be negative.
+ */
+void csi_intc_disable_irq(int32_t IRQn);
+
+/**
+  \brief        Get Pending Interrupt
+  \details      Reads the pending register in the INTC and returns the pending bit for the specified interrupt.
+  \param[in]    IRQn  Interrupt number.
+  \return       0  Interrupt status is not pending.
+  \return       1  Interrupt status is pending.
+ */
+uint32_t csi_intc_get_pending_irq(int32_t IRQn);
+
+/**
+  \brief        Set Pending Interrupt
+  \details      Sets the pending bit of an external interrupt.
+  \param[in]    IRQn  Interrupt number. Value cannot be negative.
+ */
+void csi_intc_set_pending_irq(int32_t IRQn);
+
+/**
+  \brief        Clear Pending Interrupt
+  \details      Clears the pending bit of an external interrupt.
+  \param[in]    IRQn  External interrupt number. Value cannot be negative.
+ */
+void csi_intc_clear_pending_irq(int32_t IRQn);
+
+/**
+  \brief        Get Wake up Interrupt
+  \details      Reads the wake up register in the INTC and returns the pending bit for the specified interrupt.
+  \param[in]    IRQn  Interrupt number.
+  \return       0  Interrupt is not set as wake up interrupt.
+  \return       1  Interrupt is set as wake up interrupt.
+ */
+uint32_t csi_intc_get_wakeup_irq(int32_t IRQn);
+
+/**
+  \brief        Set Wake up Interrupt
+  \details      Sets the wake up bit of an external interrupt.
+  \param[in]    IRQn  Interrupt number. Value cannot be negative.
+ */
+void csi_intc_set_wakeup_irq(int32_t IRQn);
+
+/**
+  \brief        Clear Wake up Interrupt
+  \details      Clears the wake up bit of an external interrupt.
+  \param[in]    IRQn  External interrupt number. Value cannot be negative.
+ */
+void csi_intc_clear_wakeup_irq(int32_t IRQn);
+
+/**
+  \brief        Get Active Interrupt
+  \details      Reads the active register in the INTC and returns the active bit for the device specific interrupt.
+  \param[in]    IRQn  Device specific interrupt number.
+  \return       0  Interrupt status is not active.
+  \return       1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+uint32_t csi_intc_get_active(int32_t IRQn);
+
+/**
+  \brief        Set Threshold register
+  \details      set the threshold register in the INTC.
+  \param[in]    VectThreshold  specific vecter threshold.
+  \param[in]    PrioThreshold  specific priority threshold.
+ */
+void csi_intc_set_threshold(uint32_t VectThreshold, uint32_t PrioThreshold);
+
+/**
+  \brief        Set Interrupt Priority
+  \details      Sets the priority of an interrupt.
+  \note         The priority cannot be set for every core interrupt.
+  \param[in]    IRQn  Interrupt number.
+  \param[in]    priority  Priority to set.
+ */
+void csi_intc_set_prio(int32_t IRQn, uint32_t priority);
+
+/**
+  \brief        Get Interrupt Priority
+  \details      Reads the priority of an interrupt.
+                The interrupt number can be positive to specify an external (device specific) interrupt,
+                or negative to specify an internal (core) interrupt.
+  \param[in]    IRQn  Interrupt number.
+  \return       Interrupt Priority.
+                Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+uint32_t csi_intc_get_prio(int32_t IRQn);
+
+/**
+  \brief        funciton is acknowledge the IRQ. this interface is internally used by irq system
+  \param[in]    irq  irq number to operate
+  \return       0 on success; -1 on failure
+ */
+int csi_intc_ack_irq(int32_t IRQn);
+
+/**
+  \brief        This function is set the attributes of an IRQ.
+  \param[in]    irq    irq number to operate
+  \param[in]    priority    interrupt priority
+  \param[in]    trigger_mode    interrupt trigger_mode
+  \return       0 on success; -1 on failure
+*/
+int csi_intc_set_attribute(int32_t IRQn, uint32_t priority, int_trigger_mode_t trigger_mode);
+
+/**
+  \brief        Set interrupt handler
+  \details      Set the interrupt handler according to the interrupt num, the handler will be filled in g_irqvector[].
+  \param[in]    IRQn  Interrupt number.
+  \param[in]    handler  Interrupt handler.
+ */
+void csi_intc_set_vector(int32_t IRQn, uint32_t handler);
+
+/**
+  \brief        Get interrupt handler
+  \details      Get the address of interrupt handler function.
+  \param[in]    IRQn  Interrupt number.
+ */
+uint32_t csi_intc_get_vector(int32_t IRQn);
+
+#endif /* _DRV_INTC_H_ */
@@ -0,0 +1,131 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/io.h
+ * @brief      Header File for register bits operation
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      io
+ ******************************************************************************/
+
+#ifndef _DRV_IO_H_
+#define _DRV_IO_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Bit field operate*/
+#define REG64(addr)        (*(volatile uint64_t *)(addr))
+#define REG32(addr)        (*(volatile uint32_t *)(addr))
+#define REG16(addr)        (*(volatile uint16_t *)(addr))
+#define REG8(addr)         (*(volatile uint8_t *)(addr))
+
+/* Insert value to some field in reg, other field is set to 0(the field make macro) */
+#define HAL_FMK(PER_REG_FIELD, val)                                         \
+    (((val) << PER_REG_FIELD##_SHIFT) & PER_REG_FIELD##_MASK)
+
+/* Get value of some field in reg(the field extract macro) */
+#define HAL_FEXT(reg, PER_REG_FIELD)                                        \
+    (((reg) & PER_REG_FIELD##_MASK) >> PER_REG_FIELD##_SHIFT)
+
+/* Insert value to some field in reg, other field don't change(the field insert macro) */
+#define HAL_FINS(reg, PER_REG_FIELD, val)                                   \
+    ((reg) = ((reg) & ~PER_REG_FIELD##_MASK)                                \
+             | HAL_FMK(PER_REG_FIELD, val))
+
+
+/* Bit operate */
+/* Set one value to 1, other bit don't change*/
+#define HAL_BIT_SET(reg, bit) ((reg) = ((reg) | (1U << (bit))))
+
+/* Set one value to 0, other bit don't change*/
+#define HAL_BIT_CLR(reg, bit) ((reg) = ((reg) & (~(1U << (bit)))))
+
+/* Get value of one bit(0/1) */
+#define HAL_GET_BIT_VAL(reg, bit) (((reg)>> (bit)) & 1U)
+
+/* Judge one bit is 1 or not */
+#define HAL_IS_BIT_SET(reg, pos) (((reg) & (1U << (pos))) != 0x0U)
+
+/* Judge one bit is 0 or not */
+#define HAL_IS_BIT_CLR(reg, pos) (((reg) & (1U << (pos))) == 0x0U)
+
+/* Set one value to bit, other bit don't change*/
+#define HAL_BIT_INSR(reg, bit, val)                                       \
+    ((reg) = (((reg) & (~(1U << (bit)))) | (((val) & 1U) << (bit))))
+
+
+static inline uint8_t getreg8(volatile void *addr)
+{
+    return *(volatile uint8_t *)addr;
+}
+
+static inline void putreg8(uint8_t val, volatile void *addr)
+{
+    *(volatile uint8_t *)addr = val;
+}
+
+static inline uint16_t getreg16(volatile void *addr)
+{
+    return *(volatile uint16_t *)addr;
+}
+
+static inline void putreg16(uint16_t val, volatile void *addr)
+{
+    *(volatile uint16_t *)addr = val;
+}
+
+static inline uint32_t getreg32(volatile void *addr)
+{
+    return *(volatile uint32_t *)addr;
+}
+
+static inline void putreg32(uint32_t val, volatile void *addr)
+{
+    *(volatile uint32_t *)addr = val;
+}
+
+static inline uint64_t getreg64(volatile void *addr)
+{
+    return *(volatile uint64_t *)addr;
+}
+
+static inline void putreg64(uint32_t val, volatile void *addr)
+{
+    *(volatile uint64_t *)addr = val;
+}
+
+static inline uint32_t inl(void *addr)
+{
+    return *(volatile uint32_t *)addr;
+}
+
+static inline void outl(uint32_t val, void *addr)
+{
+    *(volatile uint32_t *)addr = val;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_IO_H_ */
@@ -0,0 +1,149 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/irq.h
+ * @brief    header File for IRQ Driver
+ * @version  V1.0
+ * @date     16. Mar 2020
+ * @model    irq
+ ******************************************************************************/
+
+#ifndef _DRV_IRQ_H_
+#define _DRV_IRQ_H_
+
+#include <soc.h>
+#include <csi_core.h>
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Enable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+__ALWAYS_STATIC_INLINE void csi_irq_enable(uint32_t irq_num)
+{
+    extern void soc_irq_enable(uint32_t irq_num);
+    soc_irq_enable(irq_num);
+}
+
+/**
+  \brief       Disable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+__ALWAYS_STATIC_INLINE void csi_irq_disable(uint32_t irq_num)
+{
+    extern void soc_irq_disable(uint32_t irq_num);
+    soc_irq_disable(irq_num);
+}
+
+/**
+  \brief       Attach irq handler.
+  \param[in]   irq_num     Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \param[in]   dev         The dev to operate
+  \return      None.
+*/
+void csi_irq_attach(uint32_t irq_num, void *irq_handler, csi_dev_t *dev);
+
+/**
+  \brief       Attach irq handler2 for compatible.
+  \param[in]   irq_num      Number of IRQ.
+  \param[in]   irq_handler2 IRQ Handler.
+  \param[in]   dev          The dev to operate
+  \param[in]   arg          user data of irq_handler2 
+  \return      None.
+*/
+void csi_irq_attach2(uint32_t irq_num, void *irq_handler2, csi_dev_t *dev, void *arg);
+
+/**
+  \brief       detach irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void csi_irq_detach(uint32_t irq_num);
+
+/**
+  \brief       Set irq priority
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   priority IRQ Priority.
+  \return      None.
+*/
+__ALWAYS_STATIC_INLINE void csi_irq_priority(uint32_t irq_num, uint32_t priority)
+{
+    extern void soc_irq_priority(uint32_t irq_num, uint32_t priority);
+    soc_irq_priority(irq_num, priority);
+}
+
+/**
+  \brief       Gets whether the interrupt is enabled
+  \param[in]   irq_num Number of IRQ.
+  \return      true or false.
+*/
+static inline bool csi_irq_is_enabled(uint32_t irq_num)
+{
+    extern bool soc_irq_is_enabled(uint32_t irq_num);
+    return soc_irq_is_enabled(irq_num);
+}
+
+/**
+  \brief       Enable the interrupt wakeup attribution
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+__ALWAYS_STATIC_INLINE void csi_irq_enable_wakeup(uint32_t irq_num)
+{
+    extern void soc_irq_enable_wakeup(uint32_t irq_num);
+    soc_irq_enable_wakeup(irq_num);
+}
+
+/**
+  \brief       Disable the interrupt wakeup attribution
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+__ALWAYS_STATIC_INLINE void csi_irq_disable_wakeup(uint32_t irq_num)
+{
+    extern void soc_irq_disable_wakeup(uint32_t irq_num);
+    soc_irq_disable_wakeup(irq_num);
+}
+
+/**
+  \brief       Gets whether in irq context
+  \return      true or false.
+*/
+bool csi_irq_context(void);
+
+/**
+  \brief       Dispatching irq handlers
+  \return      None.
+*/
+void do_irq(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_IRQ_H_ */
@@ -0,0 +1,104 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/mbox.h
+ * @brief    Header File for MBOX Driver
+ * @version  V1.0
+ * @date     5. Apr 2020
+ * @model    mbox
+ ******************************************************************************/
+
+#ifndef _DRV_MBOX_H_
+#define _DRV_MBOX_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    MBOX_EVENT_SEND_COMPLETE       = 0U,  ///< Send completed; however mbox may still transmit data
+    MBOX_EVENT_RECEIVED            = 1U,  ///< Data Received, only in mbox buf, call memcpy() get the data
+    MBOX_EVENT_ERROR               = 2U,  ///< Mbox transmit error occurred
+} csi_mbox_event_t;
+
+typedef struct csi_mbox csi_mbox_t;
+struct csi_mbox {
+    csi_dev_t        dev;
+    void (*callback)(csi_mbox_t *mbox, csi_mbox_event_t event, uint32_t channel_id, uint32_t received_len, void *arg);
+    void             *arg;
+    void             *priv;
+};
+
+/**
+  \brief       Initialize mbox Interface.
+               Initializes the resources needed for the mbox interface.
+  \param[in]   mbox  Operate handle.
+  \param[in]   idx  The device idx.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_mbox_init(csi_mbox_t *mbox, uint32_t idx);
+
+/**
+  \brief       Uninitialize mbox interface. stops operation and releases the software resources used by the interface.
+  \param[in]   mbox  Operate handle.
+*/
+void csi_mbox_uninit(csi_mbox_t *mbox);
+
+/**
+  \brief       Start sending data to mbox transmitter.
+  \param[in]   mbox  Operate handle.
+  \param[in]   channel_id  Index of channel.
+  \param[in]   data  Pointer to buffer with data to send to mbox transmitter.
+  \param[in]   size  Number of data items to send.
+  \return      sent Number of data or error code.
+*/
+int32_t csi_mbox_send(csi_mbox_t *mbox, uint32_t channel_id, const void *data, uint32_t size);
+
+/**
+  \brief       Start receiving data from mbox receiver.
+  \param[in]   mbox  Operate handle.
+  \param[in]   channel_id  Index of channel.
+  \param[out]  data  Pointer to buffer with data to receive from mailbox.
+  \param[in]   size  Number of data items to receive.
+  \return      received  Number or error code.
+*/
+int32_t csi_mbox_receive(csi_mbox_t *mbox, uint32_t channel_id, void *data, uint32_t size);
+
+/**
+  \brief       Attach callback to the mbox.
+  \param[in]   mbox  Operate handle.
+  \param[in]   cb  Event callback function.
+  \param[in]   arg  User private param  for event callback.
+  \return      Error code \ref csi_error_t.
+*/
+csi_error_t csi_mbox_attach_callback(csi_mbox_t *mbox, void *callback, void *arg);
+
+/**
+  \brief       Detach callback from the mbox
+  \param[in]   mbox  Operate handle.
+*/
+void csi_mbox_detach_callback(csi_mbox_t *mbox);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_MBOX_H_ */
@@ -0,0 +1,198 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     soc.h
+ * @brief    For pin
+ * @version  V1.0
+ * @date     11. Mar 2020
+ ******************************************************************************/
+
+#ifndef _DRV_PIN_H_
+#define _DRV_PIN_H_
+
+#include <soc.h>
+#include <csi_core.h>
+#include <drv/common.h>
+#include <drv/gpio.h>
+
+typedef csi_gpio_mode_t csi_pin_mode_t;
+
+typedef enum {
+    PIN_SPEED_LV0 = 0U,
+    PIN_SPEED_LV1,
+    PIN_SPEED_LV2,
+    PIN_SPEED_LV3
+} csi_pin_speed_t;
+
+typedef enum {
+    PIN_DRIVE_LV0 = 0U,
+    PIN_DRIVE_LV1,
+    PIN_DRIVE_LV2,
+    PIN_DRIVE_LV3
+} csi_pin_drive_t;
+
+typedef enum{
+    PIN_UART_TX = 0U,
+    PIN_UART_RX,
+    PIN_UART_CTS,
+    PIN_UART_RTS
+}csi_pin_uart_t;
+
+typedef enum{
+    PIN_IIC_SCL = 0U,
+    PIN_IIC_SDA
+}csi_pin_iic_t;
+
+typedef enum{
+    PIN_SPI_MISO = 0U,
+    PIN_SPI_MOSI,
+    PIN_SPI_SCK,
+    PIN_SPI_CS
+}csi_pin_spi_t;
+
+typedef enum{
+    PIN_I2S_MCLK = 0U,
+    PIN_I2S_SCLK,
+    PIN_I2S_WSCLK,
+    PIN_I2S_SDA,
+    PIN_I2S_SDI,
+    PIN_I2S_SDO
+}csi_pin_i2s_t;
+ 
+typedef struct {
+    pin_name_t  pin_name;
+    uint8_t     idx;        ///< ctrl idx.    e.g: ADC0 channel 1, idx = 0, channel = 1
+    uint8_t     channel;    ///< channel idx. e.g: same as the previous line
+    pin_func_t  pin_func;
+} csi_pinmap_t;
+
+extern uint32_t target_pin_to_devidx(pin_name_t pin_name, const csi_pinmap_t *pinmap);
+extern uint32_t target_pin_to_channel(pin_name_t pin_name,const csi_pinmap_t *pinmap);
+extern pin_name_t target_gpio_to_pin(uint8_t gpio_idx, uint8_t channel,const csi_pinmap_t *pinmap);
+
+/**
+  \brief       Set pin mux function
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \param[in]   pin_func    Pin function, defined in soc.h
+  \return      \ref  csi_error_t
+*/
+csi_error_t csi_pin_set_mux(pin_name_t pin_name, pin_func_t pin_func);
+
+/**
+  \brief       Get pin function
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \return      pin function
+*/
+pin_func_t csi_pin_get_mux(pin_name_t pin_name);
+
+/**
+  \brief       Set pin mode
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \param[in]   mode        Push/pull mode
+  \return      \ref  csi_error_t
+*/
+csi_error_t csi_pin_mode(pin_name_t pin_name, csi_pin_mode_t mode);
+
+/**
+  \brief       Set pin speed
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \param[in]   speed       Io speed
+  \return      \ref  csi_error_t
+*/
+csi_error_t csi_pin_speed(pin_name_t pin_name, csi_pin_speed_t speed);
+
+/**
+  \brief       Set pin drive
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \param[in]   drive       Io drive
+  \return      \ref  csi_error_t
+*/
+csi_error_t csi_pin_drive(pin_name_t pin_name, csi_pin_drive_t drive);
+
+/**
+  \brief       Get ctrl idx by pin
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \return      idx
+*/
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_devidx(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t gpio_pinmap[];
+    return target_pin_to_devidx(pin_name, gpio_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_uart_devidx(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t uart_pinmap[];
+    return target_pin_to_devidx(pin_name, uart_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_iic_devidx(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t iic_pinmap[];
+    return target_pin_to_devidx(pin_name, iic_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_spi_devidx(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t spi_pinmap[];
+    return target_pin_to_devidx(pin_name, spi_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_i2s_devidx(pin_name_t pin_name)
+{
+    extern  const csi_pinmap_t i2s_pinmap[];
+    return target_pin_to_devidx(pin_name, i2s_pinmap);
+}
+
+/**
+  \brief       Get channel by pin
+  \param[in]   pin_name    Pin name, defined in soc.h
+  \return      channel
+*/
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_adc_channel(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t adc_pinmap[];
+    return target_pin_to_channel(pin_name, adc_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_pwm_channel(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t pwm_pinmap[];
+    return target_pin_to_channel(pin_name, pwm_pinmap);
+}
+
+__ALWAYS_STATIC_INLINE uint32_t csi_pin_get_gpio_channel(pin_name_t pin_name)
+{
+    extern const csi_pinmap_t gpio_pinmap[];
+    return target_pin_to_channel(pin_name, gpio_pinmap);
+}
+
+/**
+  \brief       Get pin name by gpio ctrl idx and channel
+  \param[in]   gpio_idx    Idx, defined in soc.h
+  \param[in]   channel     Channel, defined in soc.h
+  \return      pin name
+*/
+__ALWAYS_STATIC_INLINE pin_name_t csi_pin_get_pinname_by_gpio(uint8_t gpio_idx, uint8_t channel)
+{
+    extern const csi_pinmap_t gpio_pinmap[];
+    return target_gpio_to_pin(gpio_idx,channel,gpio_pinmap);
+}
+
+#endif /* _DRV_PIN_H_ */
@@ -0,0 +1,122 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/pm.h
+ * @brief    Header File for PM Driver
+ * @version  V1.0
+ * @date     10. Oct 2020
+ * @model    pm
+ ******************************************************************************/
+
+#ifndef _DRV_PM_H_
+#define _DRV_PM_H_
+
+#include <stdint.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Initialize PM module
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_init(void);
+
+/**
+  \brief       De-initialize PM module
+  \return      None
+*/
+void csi_pm_uninit(void);
+
+/**
+  \brief       Set the retention memory used to save registers
+  \param[in]   mem    Retention memory(word align)
+  \param[in]   num    Number of memory(1: 1 word)
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_set_reten_mem(uint32_t *mem, uint32_t num);
+
+/**
+  \brief       Config the wakeup source
+  \param[in]   wakeup_num    Wakeup source num
+  \param[in]   enable        Flag control the wakeup source is enable or not
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_config_wakeup_source(uint32_t wakeup_num, bool enable);
+
+/**
+  \brief       System enter low-power mode
+  \param[in]   mode    Low-power mode, \ref csi_pm_mode_t
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_enter_sleep(csi_pm_mode_t mode);
+
+/**
+  \brief       Register device to the PM list
+  \param[in]   dev          Csi dev
+  \param[in]   pm_action    PM action function
+  \param[in]   mem_size     Size of memory for saving registers
+  \param[in]   priority     PM dev priority(0-3), The smaller the value,
+                            the last execution before entering low power consumption,
+                            the first execution after exiting low power consumption
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_dev_register(csi_dev_t *dev, void *pm_action, uint32_t mem_size, uint8_t priority);
+
+/**
+  \brief       Deregister device to the PM list
+  \param[in]   dev    Csi dev
+  \return      None
+*/
+void csi_pm_dev_unregister(csi_dev_t *dev);
+
+/**
+  \brief       Save registers to memory
+  \param[in]   mem     Mem to store registers
+  \param[in]   addr    Registers address
+  \param[in]   num     Number of memory(1: 1 word)
+  \return      None
+*/
+void csi_pm_dev_save_regs(uint32_t *mem, uint32_t *addr, uint32_t num);
+
+/**
+  \brief       Save registers to memory
+  \param[in]   mem     Mem to store registers
+  \param[in]   addr    Registers address
+  \param[in]   num     Number of memory(1: 1 word)
+  \return      None
+*/
+void csi_pm_dev_restore_regs(uint32_t *mem, uint32_t *addr, uint32_t num);
+
+/**
+  \brief       Notify devices enter low-power states
+  \param[in]   action    Device low-power action
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pm_dev_notify(csi_pm_dev_action_t action);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_PM_H_ */
@@ -0,0 +1,118 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv_pmu.h
+ * @brief    header file for pmu driver
+ * @version  V1.0
+ * @date     02. June 2017
+ * @model    pmu
+ ******************************************************************************/
+
+#ifndef _DRV_PMU_H_
+#define _DRV_PMU_H_
+
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for pmu handle.
+typedef void *pmu_handle_t;
+
+/****** PMU specific error codes *****/
+typedef enum {
+    EDRV_PMU_MODE  = (1),      ///< Specified Mode not supported
+} pmu_error_e;
+
+/*----- PMU Control Codes: Mode -----*/
+typedef enum {
+    PMU_MODE_RUN                  = 0,   ///< Running mode
+    PMU_MODE_SLEEP,                      ///< Sleep mode
+    PMU_MODE_DOZE,                       ///< Doze mode
+    PMU_MODE_DORMANT,                    ///< Dormant mode
+    PMU_MODE_STANDBY,                    ///< Standby mode
+    PMU_MODE_SHUTDOWN                    ///< Shutdown mode
+} pmu_mode_e;
+
+/*----- PMU Control Codes: Wakeup type -----*/
+typedef enum {
+    PMU_WAKEUP_TYPE_PULSE   = 0,    ///< Pulse interrupt
+    PMU_WAKEUP_TYPE_LEVEL           ///< Level interrupt
+} pmu_wakeup_type_e;
+
+/*----- PMU Control Codes: Wakeup polarity -----*/
+typedef enum {
+    PMU_WAKEUP_POL_LOW      = 0,       ///< Low or negedge
+    PMU_WAKEUP_POL_HIGH                ///< High or posedge
+} pmu_wakeup_pol_e;
+
+/****** PMU Event *****/
+typedef enum {
+    PMU_EVENT_SLEEP_DONE        = 0,  ///< Send completed; however PMU may still transmit data
+    PMU_EVENT_PREPARE_SLEEP     = 1
+} pmu_event_e;
+
+typedef void (*pmu_event_cb_t)(int32_t idx, pmu_event_e event, pmu_mode_e mode);   ///< Pointer to \ref pmu_event_cb_t : PMU Event call back.
+
+/**
+  \brief       Initialize PMU Interface. 1. Initializes the resources needed for the PMU interface 2.registers event callback function
+  \param[in]   idx the id of the pmu
+  \param[in]   cb_event  Pointer to \ref pmu_event_cb_t
+  \return      return pmu handle if success
+*/
+pmu_handle_t csi_pmu_initialize(int32_t idx, pmu_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize PMU Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  pmu handle to operate.
+  \return      error code
+*/
+int32_t csi_pmu_uninitialize(pmu_handle_t handle);
+
+/**
+  \brief       choose the pmu mode to enter
+  \param[in]   handle  pmu handle to operate.
+  \param[in]   mode    \ref pmu_mode_e
+  \return      error code
+*/
+int32_t csi_pmu_enter_sleep(pmu_handle_t handle, pmu_mode_e mode);
+
+/**
+  \brief       control pmu power.
+  \param[in]   handle  pmu handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+/**
+  \brief       Config the wakeup source.
+  \param[in]   handle  pmu handle to operate
+  \param[in]   wakeup_num wakeup source num
+  \param[in]   type    \ref pmu_wakeup_type
+  \param[in]   pol     \ref pmu_wakeup_pol
+  \param[in]   enable  flag control the wakeup source is enable or not
+  \return      error code
+*/
+int32_t csi_pmu_config_wakeup_source(pmu_handle_t handle, uint32_t wakeup_num, pmu_wakeup_type_e type, pmu_wakeup_pol_e pol, uint8_t enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_PMU_H_ */
@@ -0,0 +1,184 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/porting.h
+ * @brief    Header File for SOC Porting
+ * @version  V1.0
+ * @date     8. Apr 2020
+ * @model    porting
+ ******************************************************************************/
+
+#ifndef _DRV_PORTING_H_
+#define _DRV_PORTING_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    BOOTREASON_WDT      = 0,    // System WDT reset
+    BOOTREASON_SOFT     = 1,    // soft reset
+    BOOTREASON_POWER    = 2,    // chip power on reset
+    BOOTREASON_OTHER    = 0xFF
+} boot_reason_t;
+
+/*
+  \brief       Soc get boot reason
+  \return      boot reason, \ref boot_reason_t
+*/
+boot_reason_t soc_get_boot_reason(void);
+
+/**
+  \brief       Soc get device frequence.
+  \param[in]   idx      Device index
+  \return      frequence
+*/
+uint32_t soc_get_apb_freq(uint32_t idx);
+uint32_t soc_get_ahb_freq(uint32_t idx);
+uint32_t soc_get_cpu_freq(uint32_t idx);
+
+uint32_t soc_get_uart_freq(uint32_t idx);
+uint32_t soc_get_spi_freq(uint32_t idx);
+uint32_t soc_get_iic_freq(uint32_t idx);
+uint32_t soc_get_i2s_freq(uint32_t idx);
+uint32_t soc_get_pwm_freq(uint32_t idx);
+uint32_t soc_get_adc_freq(uint32_t idx);
+uint32_t soc_get_qspi_freq(uint32_t idx);
+uint32_t soc_get_usi_freq(uint32_t idx);
+uint32_t soc_get_timer_freq(uint32_t idx);
+uint32_t soc_get_rtc_freq(uint32_t idx);
+uint32_t soc_get_wdt_freq(uint32_t idx);
+uint32_t soc_get_sdio_freq(uint32_t idx);
+uint32_t soc_get_emmc_freq(uint32_t idx);
+uint32_t soc_get_usb_freq(uint32_t idx);
+uint32_t soc_get_ref_clk_freq(uint32_t idx);
+uint32_t soc_get_coretim_freq(void);
+uint32_t soc_get_cur_cpu_freq(void);
+uint32_t soc_get_sys_freq(void);
+
+/**
+  \brief       Soc get device frequence.
+  \param[in]   freq     CPU frequence
+  \return      none
+*/
+void soc_set_sys_freq(uint32_t freq);
+
+/*
+  \brief       Soc init clock unit
+  \return      none
+*/
+void soc_clk_init(void);
+
+/*
+  \brief       Soc enable device clock
+  \param[in]   module   Clock module, defined in sys_clk.h, \ref clk_module_t
+  \return      none
+*/
+void soc_clk_enable(int32_t module);
+
+/*
+  \brief       Soc disable device clock
+  \param[in]   module   Clock module, defined in sys_clk.h, \ref clk_module_t
+  \return      none
+*/
+void soc_clk_disable(int32_t module);
+
+/*
+  \brief       Get CPU ID
+  \return      CPU ID, the val is 0, 1, 2...
+*/
+uint32_t soc_get_cpu_id(void);
+
+/**
+  \brief       SOC Dcache clean & invalid by range.
+  \return      None
+*/
+void soc_dcache_clean_invalid_range(unsigned long addr, uint32_t size);
+
+/**
+  \brief       SOC Dcache clean & invalid all.
+  \return      None
+*/
+void soc_dcache_clean_invalid_all(void);
+
+/**
+  \brief       SOC Dcache invalid by range.
+  \return      None
+*/
+void soc_dcache_invalid_range(unsigned long addr, uint32_t size);
+
+/**
+  \brief       SOC Dcache invalid all.
+  \return      None
+*/
+void soc_dcache_invalid(void);
+
+/**
+  \brief       SOC Dcache clean all.
+  \return      None
+*/
+void soc_dcache_clean(void);
+
+
+/**
+  \brief       SOC Dcache clean by range.
+  \return      None
+*/
+void soc_dcache_clean_range(unsigned long addr, uint32_t size);
+
+/**
+  \brief       SOC Icache invalid all.
+  \return      None
+*/
+void soc_icache_invalid(void);
+
+/**
+  \brief       SOC dma address remap.
+  \return      Remaped address
+*/
+extern unsigned long soc_dma_address_remap(unsigned long addr);
+
+
+#ifdef CONFIG_PM
+/**
+  \brief       SoC enter low-power mode, each chip's implementation is different
+               called by csi_pm_enter_sleep
+  \param[in]   mode        low-power mode
+  \return      Error code
+*/
+csi_error_t soc_pm_enter_sleep(csi_pm_mode_t mode);
+
+/**
+  \brief       SoC the wakeup source.
+  \param[in]   wakeup_num  Wakeup source num
+  \param[in]   enable      Flag control the wakeup source is enable or not
+  \return      Error code
+*/
+csi_error_t soc_pm_config_wakeup_source(uint32_t wakeup_num, bool enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_PORTING_H_ */
@@ -0,0 +1,172 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/pwm.h
+ * @brief      Header File for PWM Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      pwm
+ ******************************************************************************/
+
+#ifndef _DRV_PWM_H_
+#define _DRV_PWM_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PWM_POLARITY_HIGH = 0U,                          ///< High level
+    PWM_POLARITY_LOW                                 ///< Low level
+} csi_pwm_polarity_t;
+
+typedef enum {
+    PWM_CAPTURE_POLARITY_POSEDGE = 0U,               ///< Posedge Edge
+    PWM_CAPTURE_POLARITY_NEGEDGE,                    ///< Negedge Edge
+    PWM_CAPTURE_POLARITY_BOTHEDGE                    ///< Both Edge
+} csi_pwm_capture_polarity_t;
+
+typedef enum {
+    PWM_EVENT_CAPTURE_POSEDGE = 0U,                  ///< Capture Posedge Event
+    PWM_EVENT_CAPTURE_NEGEDGE,                       ///< Capture Negedge Event
+    PWM_EVENT_CAPTURE_BOTHEDGE,                      ///< Capture Bothedge Event
+    PWM_EVENT_ERROR,                                 ///< Error
+} csi_pwm_event_t;
+
+typedef struct csi_pwm csi_pwm_t;
+
+struct csi_pwm {
+    csi_dev_t      dev;
+    void (*callback)(csi_pwm_t *pwm, csi_pwm_event_t event, uint32_t ch, uint32_t time_us, void *arg);
+    void           *arg;
+    void           *priv;
+};
+
+/**
+  \brief       Initialize PWM interface. Initializes the resources needed for the PWM interface
+  \param[in]   pwm    Handle to operate
+  \param[in]   idx    PWM idx
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_init(csi_pwm_t *pwm, uint32_t idx);
+
+/**
+  \brief       De-initialize PWM interface. Stops operation and releases the software resources used by the interface
+  \param[in]   pwm    Handle to operate
+  \return      None
+*/
+void csi_pwm_uninit(csi_pwm_t *pwm);
+
+/**
+  \brief       Config PWM out mode
+  \param[in]   pwm               Handle to operate
+  \param[in]   channel           Channel num
+  \param[in]   period_us         The PWM period in us
+  \param[in]   pulse_width_us    The PMW pulse width in us
+  \param[in]   polarity          The PWM polarity \ref csi_pwm_polarity_t
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_out_config(csi_pwm_t *pwm,
+                               uint32_t channel,
+                               uint32_t period_us,
+                               uint32_t pulse_width_us,
+                               csi_pwm_polarity_t polarity);
+
+/**
+  \brief       Start generate PWM signal
+  \param[in]   pwm        Handle to operate
+  \param[in]   channel    Channel num
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_out_start(csi_pwm_t *pwm, uint32_t channel);
+
+/**
+  \brief       Stop generate PWM signal
+  \param[in]   pwm        Handle to operate
+  \param[in]   channel    Channel num
+  \return      None
+*/
+void csi_pwm_out_stop(csi_pwm_t *pwm, uint32_t channel);
+
+/**
+  \brief       Config PWM capture mode
+  \param[in]   pwm         Handle to operate
+  \param[in]   channel     Channel num
+  \param[in]   polarity    PWM capture polarity \ref csi_pwm_capture_polarity_t
+  \param[in]   count       PWM capture polarity count
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_capture_config(csi_pwm_t *pwm,
+                                   uint32_t channel,
+                                   csi_pwm_capture_polarity_t polarity,
+                                   uint32_t count);
+
+/**
+  \brief       Start PWM capture
+  \param[in]   pwm        Handle to operate
+  \param[in]   channel    Channel num
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_capture_start(csi_pwm_t *pwm, uint32_t channel);
+
+/**
+  \brief       Stop PWM capture
+  \param[in]   pwm        Handle to operate
+  \param[in]   channel    Channel num
+  \return      None
+*/
+void csi_pwm_capture_stop(csi_pwm_t *pwm, uint32_t channel);
+
+/**
+  \brief       Attach PWM callback
+  \param[in]   pwm         Handle to operate
+  \param[in]   callback    Callback func
+  \param[in]   arg         Callback's param
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_attach_callback(csi_pwm_t *pwm, void *callback, void *arg);
+
+/**
+  \brief       Detach PWM callback
+  \param[in]   pwm    Handle to operate
+  \return      None
+*/
+void csi_pwm_detach_callback(csi_pwm_t *pwm);
+
+/**
+  \brief       Enable PWM power manage
+  \param[in]   pwm    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_pwm_enable_pm(csi_pwm_t *pwm);
+
+/**
+  \brief       Disable PWM power manage
+  \param[in]   pwm    Handle to operate
+  \return      None
+*/
+void csi_pwm_disable_pm(csi_pwm_t *pwm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_PWM_H_ */
@@ -0,0 +1,62 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+* @file     ringbuffer.h
+* @brief    header file for ringbuffer Driver
+* @version  V1.0
+* @date     August 15.  2019
+******************************************************************************/
+#ifndef _RING_BUFFER_H_
+#define _RING_BUFFER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "stdint.h"
+#include <stdbool.h>
+
+typedef struct ringbuffer {
+    uint8_t *buffer;
+    uint32_t size;
+    uint32_t write;
+    uint32_t read;
+    uint32_t data_len;
+} csi_ringbuf_t;
+
+void csi_ringbuf_reset(csi_ringbuf_t *fifo);
+uint32_t csi_ringbuf_len(csi_ringbuf_t *fifo);
+uint32_t csi_ringbuf_avail(csi_ringbuf_t *fifo);
+bool csi_ringbuf_is_empty(csi_ringbuf_t *fifo);
+bool csi_ringbuf_is_full(csi_ringbuf_t *fifo);
+
+/*write to ringbuffer*/
+uint32_t csi_ringbuf_in(csi_ringbuf_t *fifo, const void *in, uint32_t len);
+
+/*read to ringbuffer*/
+uint32_t csi_ringbuf_out(csi_ringbuf_t *fifo, void *out, uint32_t len);
+
+/*move to another ringbuffer*/
+uint32_t csi_ringbuf_move(csi_ringbuf_t *fifo_in, csi_ringbuf_t *fifo_out);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RING_BUFFER_H_ */
@@ -0,0 +1,54 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/tng.h
+ * @brief    Header File for RNG Driver
+ * @version  V1.0
+ * @date     22. Apr 2020
+ * @model    tng
+ ******************************************************************************/
+#ifndef _DRV_TNG_H_
+#define _DRV_TNG_H_
+
+#include "drv/common.h"
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Get data from the TNG engine
+  \param[out]  Data  Pointer to buffer with data get from TNG
+  \param[in]   Num   Number of data items,uinit in uint32
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rng_get_multi_word(uint32_t *data, uint32_t num);
+
+/**
+  \brief       Get data from the TNG engine
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rng_get_single_word(uint32_t* data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TNG_H_ */
@@ -0,0 +1,198 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     drv/rsa.h
+ * @brief    Header File for RSA Driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    rsa
+ ******************************************************************************/
+#ifndef _DRV_RSA_H_
+#define _DRV_RSA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <drv/common.h>
+
+/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/
+/****** RSA Key bits Type *****/
+typedef enum {
+    RSA_KEY_BITS_192  = 0U,  		           /* 192 Key bits */ 
+    RSA_KEY_BITS_256,                      /* 256 Key bits */ 
+    RSA_KEY_BITS_512,                      /* 512 Key bits */ 
+    RSA_KEY_BITS_1024,                     /* 1024 Key bits */ 
+    RSA_KEY_BITS_2048,                     /* 2048 Key bits */ 
+    RSA_KEY_BITS_3072,                     /* 3072 Key bits */ 
+    RSA_KEY_BITS_4096                      /* 4096 Key bits */ 
+} csi_rsa_key_bits_t;
+
+/****** RSA Padding Type *****/
+typedef enum {
+    RSA_PADDING_MODE_NO  = 0,              /* RSA NO Padding Mode */ 
+    RSA_PADDING_MODE_PKCS1,                /* RSA PKCS1 Padding Mode */ 
+    RSA_PADDING_MODE_PKCS1_OAEP,           /* RSA PKCS1 OAEP Padding Mode */ 
+    RSA_PADDING_MODE_SSLV23,               /* RSA SSLV23 Padding Mode */ 
+    RSA_PADDING_MODE_X931,                 /* RSA X931 Padding Mode */ 
+    RSA_PADDING_MODE_PSS                   /* RSA PSS Padding Mode */ 
+} csi_rsa_padding_type_t;
+
+/****** RSA Hash Type *****/
+typedef enum {
+    RSA_HASH_TYPE_MD5  = 0,               
+    RSA_HASH_TYPE_SHA1,
+    RSA_HASH_TYPE_SHA224,
+    RSA_HASH_TYPE_SHA256,
+    RSA_HASH_TYPE_SHA384,
+    RSA_HASH_TYPE_SHA512
+} csi_rsa_hash_type_t;
+
+/****** RSA Context *****/
+typedef struct {
+    void *n;                                /* Pointer to the public modulus */
+    void *e;                                /* Pointer to the public exponent */
+    void *d;                                /* Pointer to the private exponent */
+    csi_rsa_key_bits_t  key_bits;           /* RSA KEY BITS */
+    csi_rsa_padding_type_t padding_type;    /* RSA PADDING TYPE */
+} csi_rsa_context_t;
+
+/****** RSA State *****/
+typedef struct {
+    uint8_t busy             : 1;           /* Calculate busy flag */
+    uint8_t error            : 1;           /* Calculate error flag */
+} csi_rsa_state_t;
+
+/****** RSA Ctrl *****/
+typedef struct {
+    csi_dev_t           dev;
+    void                *cb;
+    void                *arg;
+    csi_rsa_state_t     state;
+    void                *prim;
+} csi_rsa_t;
+
+/****** RSA Moddle *****/
+typedef struct {
+  uint32_t pout[64];
+  uint8_t  *pouts;
+  uint32_t *pout_size;
+  uint32_t u32keywords;
+  uint8_t  *pdst;
+  uint32_t u32padding;
+  uint32_t u32dst_words;
+  uint32_t u32type;
+  uint32_t rsa_state;
+}rsa_middle_t;
+
+/****** RSA Event *****/
+typedef enum {
+    RSA_EVENT_COMPLETE    = 0,            /* rsa event completed */
+    RSA_EVENT_VERIFY_SUCCESS,             /* rsa event verify success */
+    RSA_EVENT_VERIFY_FAILED,              /* rsa event verify failed */
+    RSA_EVENT_ERROR,                      /* rsa event error */
+} csi_rsa_event_t;
+
+typedef void (*csi_rsa_callback_t)(csi_rsa_t *rsa, csi_rsa_event_t event, void *arg);   ///< Pointer to \ref csi_rsa_callback_t : RSA Event call back.
+
+/**
+  \brief       Initialize RSA Interface. 1. Initializes the resources needed for the RSA interface 2.registers event callback function
+  \param[in]   rsa  RSA handle to operate.
+  \param[in]   idx  Device id
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_init(csi_rsa_t *rsa, uint32_t idx);
+
+/**
+  \brief       De-initialize RSA Interface. stops operation and releases the software resources used by the interface
+  \param[in]   rsa  RSA handle to operate.
+  \return      none
+*/
+void csi_rsa_uninit(csi_rsa_t *rsa);
+
+/**
+  \brief       Generate rsa key pair.
+  \param[in]   rsa       RSA handle to operate.
+  \param[out]  context   Pointer to the rsa context
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_gen_key(csi_rsa_t *rsa, csi_rsa_context_t *context);
+
+/**
+  \brief       Encrypt
+  \param[in]   rsa       RSA handle to operate.
+  \param[in]   context   Pointer to the rsa context
+  \param[in]   src       Pointer to the source data.
+  \param[in]   src_size  The source data len
+  \param[out]  out       Pointer to the result buffer
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_encrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out);
+
+/**
+  \brief       decrypt
+  \param[in]   rsa       RSA handle to operate.
+  \param[in]   context   Pointer to the rsa context
+  \param[in]   src       Pointer to the source data.
+  \param[in]   src_size  The source data len
+  \param[out]  out       Pointer to the result buffer
+  \param[out]  out_size  The result size
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_decrypt(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *out, uint32_t *out_size);
+
+/**
+  \brief       RSA sign
+  \param[in]   rsa       RSA handle to operate.
+  \param[in]   context   Pointer to the rsa context
+  \param[in]   src       Pointer to the source data.
+  \param[in]   src_size  The source data len
+  \param[out]  signature Pointer to the signature
+  \param[in]   hash_type The source data hash type
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_sign(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, csi_rsa_hash_type_t hash_type);
+
+/**
+  \brief       RSA verify
+  \param[in]   rsa       RSA handle to operate.
+  \param[in]   context   Pointer to the rsa context
+  \param[in]   src       Pointer to the source data.
+  \param[in]   src_size  The source data len
+  \param[in]   signature Pointer to the signature
+  \param[in]   sig_size  The signature size
+  \param[in]   hash_type The source data hash type
+  \return      Verify result
+*/
+bool csi_rsa_verify(csi_rsa_t *rsa, csi_rsa_context_t *context, void *src, uint32_t src_size, void *signature, uint32_t sig_size, csi_rsa_hash_type_t hash_type);
+
+/**
+  \brief       Get big prime data
+  \param[in]   rsa          RSA handle to operate.
+  \param[in]   p            Pointer to the prime
+  \param[in]   bit_length   Pointer to the prime bit length
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rsa_get_prime(csi_rsa_t *rsa, void *p, uint32_t bit_length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_RSA_H_ */
@@ -0,0 +1,148 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/rtc.h
+ * @brief      Header File for RTC Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      rtc
+ ******************************************************************************/
+
+#ifndef _DRV_RTC_H_
+#define _DRV_RTC_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****** RTC time ******/
+typedef struct {
+    int tm_sec;             ///< Second.      [0-59]
+    int tm_min;             ///< Minute.      [0-59]
+    int tm_hour;            ///< Hour.        [0-23]
+    int tm_mday;            ///< Day.         [1-31]
+    int tm_mon;             ///< Month.       [0-11]
+    int tm_year;            ///< Year-1900.   [70- ]      !NOTE:Set 100 mean 2000
+    int tm_wday;            ///< Day of week. [0-6 ]      !NOTE:Set 0 mean Sunday
+    int tm_yday;            ///< Days in year.[0-365]     !NOTE:Set 0 mean January 1st
+} csi_rtc_time_t;
+
+/****** definition for RTC ******/
+typedef struct csi_rtc csi_rtc_t;
+
+struct csi_rtc {
+    csi_dev_t           dev;
+    void (*callback)(csi_rtc_t *rtc, void *arg);
+    void               *arg;
+    void               *priv;
+};
+
+/**
+  \brief       Initialize RTC interface. Initializes the resources needed for the RTC interface
+  \param[in]   rtc    Handle to operate
+  \param[in]   idx    RTC index
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_init(csi_rtc_t *rtc, uint32_t idx);
+
+/**
+  \brief       De-initialize RTC interface. Stops operation and releases the software resources used by the interface
+  \param[in]   rtc    Handle to operate
+  \return      None
+*/
+void csi_rtc_uninit(csi_rtc_t *rtc);
+
+/**
+  \brief       Set system date and wait for synchro
+  \param[in]   rtc        Handle to operate
+  \param[in]   rtctime    Pointer to RTC time
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_set_time(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime);
+
+/**
+  \brief       Set system date but no wait
+  \param[in]   rtc        Handle to operate
+  \param[in]   rtctime    Pointer to RTC time
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_set_time_no_wait(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime);
+
+/**
+  \brief       Get system date
+  \param[in]   rtc        Handle to operate
+  \param[out]  rtctime    Pointer to RTC time
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_get_time(csi_rtc_t *rtc, csi_rtc_time_t *rtctime);
+
+/**
+  \brief       Get alarm remaining time
+  \param[in]   rtc    Handle to operate
+  \return      The remaining time(s)
+*/
+uint32_t csi_rtc_get_alarm_remaining_time(csi_rtc_t *rtc);
+
+/**
+  \brief       Config RTC alarm timer
+  \param[in]   rtc         Handle to operate
+  \param[in]   rtctime     Time to wake up
+  \param[in]   callback    Callback function
+  \param[in]   arg         Callback's param
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_set_alarm(csi_rtc_t *rtc, const csi_rtc_time_t *rtctime, void *callback, void *arg);
+
+/**
+  \brief       Cancel the RTC alarm
+  \param[in]   rtc    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_cancel_alarm(csi_rtc_t *rtc);
+
+/**
+  \brief       Judge RTC is running
+  \param[in]   rtc    Handle to operate
+  \return
+               true  - RTC is running
+               false - RTC is not running
+*/
+bool csi_rtc_is_running(csi_rtc_t *rtc);
+
+/**
+  \brief       Enable RTC power manage
+  \param[in]   rtc    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_rtc_enable_pm(csi_rtc_t *rtc);
+
+/**
+  \brief       Disable RTC power manage
+  \param[in]   rtc    Handle to operate
+  \return      None
+*/
+void csi_rtc_disable_pm(csi_rtc_t *rtc);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_RTC_H_ */
@@ -0,0 +1,144 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/sasc.h
+ * @brief    Header File for SASC driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    sasc
+ ******************************************************************************/
+#ifndef _DRV_SASC_H_
+#define _DRV_SASC_H_
+
+
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+typedef enum {
+    SASC_RW = 0,
+    SASC_RO = 1,
+    SASC_WO = 2,
+    SASC_AP_DENY = 3
+} csi_sasc_ap_t;
+
+typedef enum {
+    SASC_DI = 0,
+    SASC_DO = 1,
+    SASC_IO = 2,
+    SASC_DI_DENY = 3
+} csi_sasc_di_t;
+
+typedef enum {
+    SASC_RAM_4B = 5,
+    SASC_RAM_8B = 6,
+    SASC_RAM_16B = 7,
+    SASC_RAM_32B = 8,
+    SASC_RAM_64B = 9,
+    SASC_RAM_128B = 10,
+    SASC_RAM_256B = 11,
+    SASC_RAM_512B = 12,
+    SASC_RAM_1KB = 13,
+    SASC_RAM_2KB = 14,
+    SASC_RAM_4KB = 15,
+    SASC_RAM_8KB = 16,
+    SASC_RAM_16KB = 17,
+    SASC_RAM_32KB = 18,
+    SASC_RAM_64KB = 19,
+    SASC_RAM_128KB = 20,
+} csi_sasc_ram_size_t;
+
+typedef enum {
+    SASC_FLASH_1S = 0,
+    SASC_FLASH_2S,
+    SASC_FLASH_4S,
+    SASC_FLASH_8S,
+    SASC_FLASH_16S,
+    SASC_FLASH_32S,
+    SASC_FLASH_64S,
+    SASC_FLASH_128S,
+    SASC_FLASH_256S,
+    SASC_FLASH_512S,
+    SASC_FLASH_1024S,
+    SASC_FLASH_2048S
+} csi_sasc_flash_size_t;
+
+typedef struct {
+    csi_sasc_ap_t   super_ap;
+    csi_sasc_ap_t   user_ap;
+    csi_sasc_di_t   super_di;
+    csi_sasc_di_t   user_di;
+    bool            is_secure;
+} csi_sasc_attr_t;
+
+/**
+  \brief       Config the sasc ram region attribute.
+  \param[in]   region_id  Config region index
+  \param[in]   base_addr  Config region base address.
+  \param[in]   size  config region size.
+  \param[in]   attr  Region attr.
+  \return      Error code
+*/
+csi_error_t csi_sasc_ram_config(uint8_t region_id, uint32_t base_addr, csi_sasc_ram_size_t size, csi_sasc_attr_t attr);
+
+/**
+  \brief       Config the sasc flash region attribute.
+  \param[in]   region_id  Config region index
+  \param[in]   base_addr  Config region base address.
+  \param[in]   size  Config region size.
+  \param[in]   attr  Region attr.
+  \return      Error code
+*/
+csi_error_t csi_sasc_flash_config(uint8_t region_id, uint32_t base_addr, csi_sasc_flash_size_t size, csi_sasc_attr_t attr);
+
+/**
+  \brief       Enable sasc ram config.
+  \param[in]   region_id  Region index
+  \return      error code
+*/
+csi_error_t csi_sasc_ram_enable(uint8_t region_id);
+
+/**
+  \brief       Enable sasc flash config
+  \param[in]   region_id  Config region index
+  \return      error code
+*/
+csi_error_t csi_sasc_flash_enable(uint8_t region_id);
+
+/**
+  \brief       Disable sasc ram config.
+  \param[in]   region_id  Region index
+  \return      error code
+*/
+csi_error_t csi_sasc_ram_disable(uint8_t region_id);
+
+/**
+  \brief       Disable sasc flash config
+  \param[in]   region_id  Region index
+  \return      error code
+*/
+csi_error_t csi_sasc_flash_disable(uint8_t region_id);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_SASC_H_ */
@@ -0,0 +1,195 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     sensor.h
+ * @brief    Header File for SENSOR Driver
+ * @version  V1.0
+ * @date     15. June 2020
+ * @model    sensor
+ ******************************************************************************/
+
+#ifndef _DRV_SENSOR_H_
+#define _DRV_SENSOR_H_
+
+#include <soc.h>
+#include <csi_core.h>
+#include <drv/common.h>
+
+
+typedef enum {
+    SENSOR_VDS_3V3_3V3 = 1,
+    SENSOR_VDS_2V5_3V3,
+    SENSOR_VDS_1V8_1V8,
+    SENSOR_VDS_1V5_1V8,
+    SENSOR_VDS_1V2_1V2,
+    SENSOR_VDS_1V1_1V2
+}drv_sensor_vds_t;
+
+typedef enum {
+    SENSOR_VHS_RANGE_15 = 0,
+    SENSOR_VHS_RANGE_12,
+    SENSOR_VHS_RANGE_9,
+    SENSOR_VHS_RANGE_6,
+}drv_sensor_vhs_t;
+
+typedef enum {
+    SENSOR_VLS_RANGE_6 = 0,
+    SENSOR_VLS_RANGE_9,
+    SENSOR_VLS_RANGE_12,
+    SENSOR_VLS_RANGE_15,
+}drv_sensor_vls_t;
+
+typedef enum {
+    SENSOR_TDHS_NEG_55 = 0,     ///< -55
+    SENSOR_TDHS_NEG_50,
+    SENSOR_TDHS_NEG_45,
+    SENSOR_TDHS_NEG_40,
+    SENSOR_TDHS_NEG_35,
+    SENSOR_TDHS_NEG_30,
+    SENSOR_TDHS_NEG_25,
+    SENSOR_TDHS_NEG_20,
+    SENSOR_TDHS_NEG_15,
+    SENSOR_TDHS_NEG_10,
+    SENSOR_TDHS_NEG_5,
+    SENSOR_TDHS_NEG_0,
+    SENSOR_TDHS_POS_5,          ///< +5
+    SENSOR_TDHS_POS_10,
+    SENSOR_TDHS_POS_15,
+    SENSOR_TDHS_POS_20,
+    SENSOR_TDHS_POS_25,
+    SENSOR_TDHS_POS_30,
+    SENSOR_TDHS_POS_35,
+    SENSOR_TDHS_POS_40,
+    SENSOR_TDHS_POS_45,
+    SENSOR_TDHS_POS_50,
+    SENSOR_TDHS_POS_55,
+    SENSOR_TDHS_POS_60,
+    SENSOR_TDHS_POS_65,
+    SENSOR_TDHS_POS_70,
+    SENSOR_TDHS_POS_75,
+    SENSOR_TDHS_POS_80,
+    SENSOR_TDHS_POS_85,
+    SENSOR_TDHS_POS_90,
+    SENSOR_TDHS_POS_95,
+    SENSOR_TDHS_POS_100,
+    SENSOR_TDHS_POS_105,
+    SENSOR_TDHS_POS_110,
+    SENSOR_TDHS_POS_115,
+    SENSOR_TDHS_POS_120,
+    SENSOR_TDHS_POS_125
+}drv_sensor_tdhs_t;
+
+typedef enum {
+    SENSOR_TDLS_NEG_55 = 0,     ///< -55
+    SENSOR_TDLS_NEG_50,
+    SENSOR_TDLS_NEG_45,
+    SENSOR_TDLS_NEG_40,
+    SENSOR_TDLS_NEG_35,
+    SENSOR_TDLS_NEG_30,
+    SENSOR_TDLS_NEG_25,
+    SENSOR_TDLS_NEG_20,
+    SENSOR_TDLS_NEG_15,
+    SENSOR_TDLS_NEG_10,
+    SENSOR_TDLS_NEG_5,
+    SENSOR_TDLS_NEG_0,
+    SENSOR_TDLS_POS_5,          ///< +5
+    SENSOR_TDLS_POS_10,
+    SENSOR_TDLS_POS_15,
+    SENSOR_TDLS_POS_20,
+}drv_sensor_tdls_t;
+
+typedef enum {
+    SENSOR_FHS_RANGE_50 = 0,
+    SENSOR_FHS_RANGE_30,
+    SENSOR_FHS_RANGE_10,
+    SENSOR_FHS_RANGE_5,
+}drv_sensor_fhs_t;
+
+typedef enum {
+    SENSOR_FLS_RANGE_50 = 0,
+    SENSOR_FLS_RANGE_30,
+    SENSOR_FLS_RANGE_10,
+    SENSOR_FLS_RANGE_5,
+}drv_sensor_fls_t;
+
+typedef enum {
+    SENSOR_FHS_FREQ_33M = 0,
+    SENSOR_FHS_FREQ_66M,
+    SENSOR_FHS_FREQ_24M,
+    SENSOR_FHS_FREQ_12M,
+    SENSOR_FHS_FREQ_99M,
+    SENSOR_FHS_FREQ_198M,
+    SENSOR_FHS_FREQ_72M,
+    SENSOR_FHS_FREQ_36M,
+}drv_sensor_freq_t;
+
+typedef enum {
+    SENSOR_WARN_H = 0,
+    SENSOR_WARN_L,
+    SENSOR_WARN_RST,
+}drv_sensor_warn_t;
+
+/**
+  \brief       Initialize Sensor VD
+  \param[in]   vds   Voltage range
+  \param[in]   vhs   Voltage high threshold
+  \param[in]   vls   Voltage low threshold
+  \param[in]   vtm   Used to modify the threshold value of the voltage detection point
+  \return      Error code
+*/
+csi_error_t drv_sensor_vd_init(drv_sensor_vds_t vds,drv_sensor_vhs_t vhs,drv_sensor_vls_t vls,uint8_t vtm);
+
+/**
+  \brief       Get vd  warn
+  \param[in]   warn  Vd warn select
+  \return      Vd warn code
+*/
+uint32_t drv_sensor_vd_get_warn(drv_sensor_warn_t warn);
+
+/**
+  \brief       Initialize Sensor td
+  \param[in]   hs   Temp high threshold
+  \param[in]   ls   Temp low threshold
+  \return      Error code
+*/
+csi_error_t drv_sensor_td_init(drv_sensor_tdhs_t hs,drv_sensor_tdls_t ls);
+
+/**
+  \brief       Get td  warn
+  \param[in]   warn  Td warn select
+  \return      Td warn code
+*/
+uint32_t drv_sensor_td_get_warn(drv_sensor_warn_t warn);
+
+/**
+  \brief       Initialize Sensor FD
+  \param[in]   hs   Temp high threshold
+  \param[in]   ls   Temp low threshold
+  \return      Error code
+*/
+csi_error_t drv_sensor_fd_init(drv_sensor_freq_t freq,drv_sensor_fhs_t fhs,drv_sensor_fls_t fls);
+
+/**
+  \brief       Get fd  warn
+  \param[in]   warn  Fd warn select
+  \return      FD warn code
+*/
+uint32_t drv_sensor_fd_get_warn(drv_sensor_warn_t warn);
+
+#endif /* _DRV_SENSOR_H_ */
@@ -0,0 +1,128 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/sha.h
+ * @brief      Header File for SHA Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      sha
+ ******************************************************************************/
+
+#ifndef _DRV_SHA_H_
+#define _DRV_SHA_H_
+
+#include <drv/common.h>
+#include <drv/dma.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****** SHA mode ******/
+typedef enum {
+    SHA_MODE_1 = 1U,                     /* SHA_1 mode */ 
+    SHA_MODE_256,                        /* SHA_256 mode */ 
+    SHA_MODE_224,                        /* SHA_224 mode */ 
+    SHA_MODE_512,                        /* SHA_512 mode */ 
+    SHA_MODE_384,                        /* SHA_384 mode */ 
+    SHA_MODE_512_256,                    /* SHA_512_256 mode */ 
+    SHA_MODE_512_224,                    /* SHA_512_224 mode */ 
+    SHA_MODE_MD5                         /* MD5 mode */ 
+} csi_sha_mode_t;
+
+/****** SHA State ******/
+typedef struct {
+    uint32_t busy             : 1;        /* Calculate busy flag */
+    uint32_t error            : 1;        /* Calculate error flag */
+} csi_sha_state_t;
+
+/****** SHA Context ******/
+typedef struct {
+    csi_sha_mode_t  mode;                 /* SHA mode */
+    uint32_t        total[2];             /* Number of bytes processed */
+    uint32_t         state[16];            /* Intermediate digest state */
+    uint8_t         buffer[128];          /* Data block being processed */
+} csi_sha_context_t;
+
+/****** SHA Event ******/
+typedef enum {
+    SHA_EVENT_COMPLETE    = 0U,           /*Calculate completed*/
+    SHA_EVENT_ERROR                       /*Calculate error*/
+} csi_sha_event_t;
+
+/****** SHA Ctrl ******/
+typedef struct csi_sha csi_sha_t;
+struct csi_sha{
+    csi_dev_t		dev;
+    void (*callback)(csi_sha_t *sha, csi_sha_event_t event, void *arg);   /* SHA event callback for user */
+    void            *arg;                                                 /* SHA custom designed param passed to evt_cb */
+    csi_dma_ch_t    *dma_in;                                              /* SHA in dma handle param */
+    csi_sha_state_t state;                                                /* SHA state */
+    void            *priv;
+};
+
+/**
+  \brief       Initialize SHA Interface. Initializes the resources needed for the SHA interface
+  \param[in]   sha    Operate handle
+  \param[in]   idx    Index of SHA
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_sha_init(csi_sha_t *sha, uint32_t idx);
+
+/**
+  \brief       De-initialize SHA Interface. Stops operation and releases the software resources used by the interface
+  \param[in]   sha    SHA handle to operate
+  \return      None
+*/
+void csi_sha_uninit(csi_sha_t *sha);
+
+/**
+  \brief       Start the engine
+  \param[in]   sha        Handle to operate
+  \param[in]   context    Pointer to the SHA context \ref csi_sha_context_t
+  \param[in]   mode       SHA mode \ref csi_sha_mode_t
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_sha_start(csi_sha_t *sha, csi_sha_context_t *context, csi_sha_mode_t mode);
+
+/**
+  \brief       Update the engine
+  \param[in]   sha        Handle to operate
+  \param[in]   context    Pointer to the SHA context \ref csi_sha_context_t
+  \param[in]   input      Pointer to the Source data
+  \param[in]   size       The data size
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_sha_update(csi_sha_t *sha, csi_sha_context_t *context, const void *input, uint32_t size);
+
+/**
+  \brief       Finish the engine
+  \param[in]   sha         Handle to operate
+  \param[in]   context     Pointer to the SHA context \ref csi_sha_context_t
+  \param[out]  output      Pointer to the result data
+  \param[out]  out_size    Pointer to the result data size(bytes)
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_sha_finish(csi_sha_t *sha, csi_sha_context_t *context, void *output, uint32_t *out_size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_SHA_H_ */
@@ -0,0 +1,92 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     tick.h
+ * @brief    Header File for TICK Driver
+ * @version  V1.0
+ * @date     28. Sep 2020
+ ******************************************************************************/
+
+#ifndef _DRV_TICK_H_
+#define _DRV_TICK_H_
+
+#include <stdint.h>
+#include <stdint.h>
+#include <drv/common.h>
+
+#ifndef CONFIG_SYSTICK_HZ
+#define CONFIG_SYSTICK_HZ  100U
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Initializes the resources needed for the TICK interface
+  \return      error code \ref csi_error_t
+*/
+csi_error_t csi_tick_init(void);
+
+/**
+  \brief       De-initialize TICK Interface
+*/
+void csi_tick_uninit(void);
+
+/**
+  \brief       Get the sys-tick, one tick == (1000 / CONFIG_SYSTICK_HZ) ms
+  \return      the sys-tick
+*/
+uint32_t csi_tick_get(void);
+
+/**
+  \brief       Get the time which start from csi_tick_init
+  \return      The time which start from csi_tick_init (ms)
+*/
+uint32_t csi_tick_get_ms(void);
+
+/**
+  \brief       Get the time which start from csi_tick_init
+  \return      The time which start from csi_tick_init (us)
+*/
+uint64_t csi_tick_get_us(void);
+
+/**
+  \brief       Get the calendar time in microseconds
+  \return      The absolute timestamp in microseconds since Unix epoch (1970-01-01 00:00:00 UTC)
+*/
+uint64_t csi_get_calendar_us(void);
+
+/**
+  \brief       Set the calendar time in microseconds
+  \param[in]   timestamp  The absolute timestamp in microseconds since Unix epoch (1970-01-01 00:00:00 UTC)
+  \return      None
+*/
+void csi_set_calendar_us(uint64_t timestamp);
+
+/**
+  \brief       Increase the sys-tick
+*/
+void csi_tick_increase(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_DRV_TICK_H_*/
@@ -0,0 +1,132 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/timer.h
+ * @brief      Header File for TIMER Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      timer
+ ******************************************************************************/
+
+#ifndef _DRV_TIMER_H_
+#define _DRV_TIMER_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct csi_timer csi_timer_t;
+
+struct csi_timer {
+    csi_dev_t        dev;
+    void (*callback)(csi_timer_t *timer, void *arg);
+    void            *arg;
+    void            *priv;
+};
+
+/**
+  \brief       Initialize TIMER interface. initializes the resources needed for the TIMER interface
+  \param[in]   timer    Handle to operate
+  \param[in]   idx      TIMER index
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_timer_init(csi_timer_t *timer, uint32_t idx);
+
+/**
+  \brief       De-initialize TIMER interface. stops operation and releases the software resources used by the interface
+  \param[in]   timer    Handle to operate
+  \return      None
+*/
+void csi_timer_uninit(csi_timer_t *timer);
+
+/**
+  \brief       Start TIMER
+  \param[in]   timer         Handle to operate
+  \param[in]   timeout_us    The timeout for TIMER
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_timer_start(csi_timer_t *timer, uint32_t timeout_us);
+
+/**
+  \brief       Stop TIMER
+  \param[in]   timer    Handle to operate
+  \return      None
+*/
+void csi_timer_stop(csi_timer_t *timer);
+
+/**
+  \brief       Get TIMER remaining value
+  \param[in]   timer    Handle to operate
+  \return      remaining value
+*/
+uint32_t csi_timer_get_remaining_value(csi_timer_t *timer);
+
+/**
+  \brief       Get TIMER load value
+  \param[in]   timer    Handle to operate
+  \return      Load value
+*/
+uint32_t csi_timer_get_load_value(csi_timer_t *timer);
+
+/**
+  \brief       Check TIMER is running
+  \param[in]   timer    Handle to operate
+  \return
+               true  - TIMER is running
+               false - TIMER is stopped
+*/
+bool csi_timer_is_running(csi_timer_t *timer);
+
+/**
+  \brief       Attach the callback handler to TIMER
+  \param[in]   timer       Operate handle
+  \param[in]   callback    Callback function
+  \param[in]   arg         Callback's param
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_timer_attach_callback(csi_timer_t *timer, void *callback, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   timer    Operate handle
+  \return      None
+*/
+void csi_timer_detach_callback(csi_timer_t *timer);
+
+/**
+  \brief       Enable TIMER power manage
+  \param[in]   timer    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_timer_enable_pm(csi_timer_t *timer);
+
+/**
+  \brief       Disable TIMER power manage
+  \param[in]   timer    Handle to operate
+  \return      None
+*/
+void csi_timer_disable_pm(csi_timer_t *timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TIMER_H_ */
@@ -0,0 +1,56 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/tipc.h
+ * @brief    Header File for TIPC Driver
+ * @version  V1.0
+ * @date     08. Mar 2020
+ * @model    tipc
+ ******************************************************************************/
+
+#ifndef _DRV_TIPC_H_
+#define _DRV_TIPC_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <csi_core.h>
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t ip;
+    uint16_t dev_tag;
+    uint8_t  idx;
+} csi_tipcmap_t;
+
+/**
+  \brief       Config the tipc module properity
+  \param[in]   dev Dev handle \ref csi_dev_t
+  \param[in]   is_secure is secure or not
+*/
+csi_error_t csi_dev_secure_config(csi_dev_t *dev, bool is_secure);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_TIPC_H_ */
@@ -0,0 +1,42 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/usi.h
+ * @brief    Header File for USI Driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    usi
+ ******************************************************************************/
+
+#ifndef _DRV_USI_H_
+#define _DRV_USI_H_
+
+#include <drv/usi_iic.h>
+#include <drv/usi_spi.h>
+#include <drv/usi_usart.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_USI_H_ */
@@ -0,0 +1,192 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     drv/usi_usart.h
+ * @brief    Header File for USART Driver
+ * @version  V1.0
+ * @date     02. June 2020
+ * @model    usi_usart
+ ******************************************************************************/
+
+#ifndef _DRV_USI_USART_H_
+#define _DRV_USI_USART_H_
+
+#include <drv/common.h>
+#include <drv/uart.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  \brief       Initialize UART Interface. 1. Initializes the resources needed for the UART interface 2.registers event callback function
+  \param[in]   uart      Operate handle.
+  \param[in]   idx       The device idx
+  \param[in]   cb_event  Event call back function \ref uart_event_cb_t
+  \param[in]   arg       User can define it by himself
+  \return      error code
+*/
+csi_error_t csi_usi_uart_init(csi_uart_t *uart, uint32_t idx);
+
+/**
+  \brief       De-initialize UART Interface. stops operation and releases the software resources used by the interface
+  \param[in]   uart  Operate handle.
+  \return      Error code
+*/
+void csi_usi_uart_uninit(csi_uart_t *uart);
+
+/**
+  \brief       Attach the callback handler to UART
+  \param[in]   uart  Operate handle.
+  \param[in]   cb    Callback function
+  \param[in]   arg   User can define it by himself as callback's param
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_attach_callback(csi_uart_t *uart, void * cb, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   uart  Operate handle.
+*/
+void  csi_usi_uart_detach_callback(csi_uart_t *uart);
+
+/**
+  \brief       Config the baudrate.
+  \param[in]   uart  UART handle to operate.
+  \param[in]   baud  UART baudrate
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_baud(csi_uart_t *uart, uint32_t baud);
+
+/**
+  \brief       Config the uart format.
+  \param[in]   uart      UART handle to operate.
+  \param[in]   data_bit  UART data bits
+  \param[in]   parity    UART data parity
+  \param[in]   stop_bit  UART stop bits
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_format(csi_uart_t *uart,  csi_uart_data_bits_t data_bits,
+                            csi_uart_parity_t parity, csi_uart_stop_bits_t stop_bits);
+
+/**
+  \brief       Config the uart flow control.
+  \param[in]   uart      UART handle to operate.
+  \param[in]   flowctrl  UART flow control
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_flowctrl(csi_uart_t *uart,  csi_uart_flowctrl_t flowctrl);
+
+/**
+  \brief       Start sending data to UART transmitter.
+  \param[in]   uart     UART handle to operate.
+  \param[in]   data     Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num      Number of data items to send (byte)
+  \param[in]   Timeout  is the number of queries, not time
+  \return      The num of data witch is send successful
+*/
+int32_t csi_usi_uart_send(csi_uart_t *uart, const void *data, uint32_t size, uint32_t timeout);
+
+/**
+  \brief       Start sending data to UART transmitter (interrupt mode).
+  \param[in]   uart   UART handle to operate.
+  \param[in]   data     Pointer to buffer with data to send to UART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num      Number of data items to send
+  \return      The status of send func
+*/
+csi_error_t csi_usi_uart_send_async(csi_uart_t *uart, const void *data, uint32_t size);
+
+/**
+  \brief       Get the num of data in RX_FIFO.
+  \param[in]   uart   UART handle to operate.
+  \return      The num of data in RX_FIFO
+*/
+uint32_t csi_usi_uart_get_recvfifo_waiting_num(csi_uart_t *uart);
+
+/**
+  \brief       Start receiving data from UART receiver. \n
+               This function is non-blocking,\ref uart_event_e is signaled when operation completes or error happens.
+               \ref csi_uart_get_status can get operation status.
+  \param[in]   uart  UART handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num   Number of data items to receive
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_receive_async(csi_uart_t *uart, void *data, uint32_t size);
+
+/**
+  \brief       Query data from UART receiver FIFO.
+  \param[in]   uart  UART handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver
+  \param[in]   num   Number of data items to receive
+  \param[in]   Timeout  is the number of queries, not time
+  \return      FIFO data num to receive
+*/
+int32_t csi_usi_uart_receive(csi_uart_t *uart, void *data, uint32_t size, uint32_t timeout);
+
+/**
+  \brief       Get character in query mode.
+  \param[in]   uart  UART handle to operate.
+  \param[out]  ch The pointer to the received character.
+  \return      Error code
+*/
+uint8_t  csi_usi_uart_getchar(csi_uart_t *uart);
+
+/**
+  \brief       Transmit character in query mode.
+  \param[in]   uart  UART handle to operate.
+  \param[in]   ch  The input character
+  \return      Error code
+*/
+void csi_usi_uart_putchar(csi_uart_t *uart, uint8_t ch);
+
+/**
+  \brief       Link DMA channel to uart device
+  \param[in]   uart  UART handle to operate.
+  \param[in]   tx_dma The DMA channel handle for send, when it is NULL means to unlink the channel
+  \param[in]   rx_dma The DMA channel handle for receive, when it is NULL means to unlink the channel
+  \return      Error code
+*/
+csi_error_t csi_usi_uart_link_dma(csi_uart_t *uart, csi_dma_ch_t *tx_dma, csi_dma_ch_t *rx_dma);
+
+/**
+  \brief       Get the state of uart device.
+  \param[in]   uart   UART handle to operate.
+  \param[out]  state  The state of uart device.
+  \return      Error code.
+*/
+csi_error_t csi_usi_uart_get_state(csi_uart_t *uart, csi_state_t *state);
+
+/**
+  \brief       Enable uart power manage.
+  \param[in]   uart   UART handle to operate.
+  \return      Error code.
+*/
+csi_error_t csi_usi_uart_enable_pm(csi_uart_t *uart);
+
+/**
+  \brief       Disable uart power manage.
+  \param[in]   uart   UART handle to operate.
+*/
+void csi_usi_uart_disable_pm(csi_uart_t *uart);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_USI_USART_H_ */
@@ -0,0 +1,139 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file       drv/wdt.h
+ * @brief      Header File for WDT Driver
+ * @version    V1.0
+ * @date       9. Oct 2020
+ * @model      wdt
+ ******************************************************************************/
+
+#ifndef _DRV_WDT_H_
+#define _DRV_WDT_H_
+
+#include <drv/common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct csi_wdt csi_wdt_t;
+
+struct csi_wdt {
+    csi_dev_t       dev;
+    void (*callback)(csi_wdt_t *wdt,  void *arg);
+    void            *arg;
+    void            *priv;
+};
+
+/**
+  \brief       Initialize WDT interface. Initializes the resources needed for the WDT interface
+  \param[in]   wdt    Handle to operate
+  \param[in]   idx    WDT index
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_init(csi_wdt_t *wdt, uint32_t idx);
+
+/**
+  \brief       De-initialize WDT interface. Stops operation and releases the software resources used by the interface
+  \param[in]   wdt    Handle to operate
+  \return      None
+*/
+void csi_wdt_uninit(csi_wdt_t *wdt);
+
+/**
+  \brief       Set the WDT value
+  \param[in]   wdt    Handle to operate
+  \param[in]   ms     The timeout value(ms)
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_set_timeout(csi_wdt_t *wdt, uint32_t ms);
+
+/**
+  \brief       Start the WDT
+  \param[in]   wdt    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_start(csi_wdt_t *wdt);
+
+/**
+  \brief       Stop the WDT
+  \param[in]   wdt    Handle to operate
+  \return      None
+*/
+void csi_wdt_stop(csi_wdt_t *wdt);
+
+/**
+  \brief       Feed the WDT
+  \param[in]   wdt    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_feed(csi_wdt_t *wdt);
+
+/**
+  \brief       Get the remaining time to timeout
+  \param[in]   wdt    Handle to operate
+  \return      The remaining time of WDT(ms)
+*/
+uint32_t csi_wdt_get_remaining_time(csi_wdt_t *wdt);
+
+/**
+  \brief       Check WDT is running
+  \param[in]   wdt    Handle to operate
+  \return
+               true  - WDT is running
+               false - WDT is stopped
+*/
+bool csi_wdt_is_running(csi_wdt_t *wdt);
+
+/**
+  \brief       Attach the callback handler to WDT
+  \param[in]   wdt         Handle to operate
+  \param[in]   callback    Callback function
+  \param[in]   arg         Callback's param
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_attach_callback(csi_wdt_t *wdt, void *callback, void *arg);
+
+/**
+  \brief       Detach the callback handler
+  \param[in]   wdt    Handle to operate
+  \return      None
+*/
+void csi_wdt_detach_callback(csi_wdt_t *wdt);
+
+/**
+  \brief       Enable WDT power manage
+  \param[in]   wdt    Handle to operate
+  \return      Error code \ref csi_error_t
+*/
+csi_error_t csi_wdt_enable_pm(csi_wdt_t *wdt);
+
+/**
+  \brief       Disable WDT power manage
+  \param[in]   wdt    Handle to operate
+  \return      None
+*/
+void csi_wdt_disable_pm(csi_wdt_t *wdt);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_WDT_H_ */
@@ -0,0 +1,157 @@
+ /*
+ * Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     csi_const_structs.h
+ * @brief    Constant structs that are initialized for user convenience.
+ * @version  V1.0
+ * @date     Feb. 2020
+ ******************************************************************************/
+
+
+#ifndef _RISCV_CONST_STRUCTS_H
+#define _RISCV_CONST_STRUCTS_H
+
+#include "csi_math.h"
+#include "csi_common_tables.h"
+
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len16;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len32;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len64;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len128;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len256;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len512;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len1024;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len2048;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_fast_sR_f32_len4096;
+
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len16;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len32;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len64;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len128;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len256;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len512;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len1024;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len2048;
+extern const csi_cfft_instance_f32 csi_cfft_radix2_sR_f32_len4096;
+
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len16;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len32;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len64;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len128;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len256;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len512;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len1024;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len2048;
+extern const csi_cfft_instance_f32 csi_cfft_radix4_sR_f32_len4096;
+
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len16 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len32 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len64 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len128 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len256 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len512 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len1024 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len2048 ;
+extern const csi_cfft_instance_f32 csi_cfft_sR_f32_len4096 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len16 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len32 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len64 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len128 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len256 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len512 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len1024 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len2048 ;
+extern const csi_cfft_instance_q31 csi_cfft_sR_q31_len4096 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len16 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len32 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len64 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len128 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len256 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len512 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len1024 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len2048 ;
+extern const csi_cfft_instance_q15 csi_cfft_sR_q15_len4096 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len32 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len64 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len128 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len256 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len512 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len1024 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len2048 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len4096 ;
+extern const csi_rfft_fast_instance_f32 csi_rfft_sR_f32_len8192 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len32 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len64 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len128 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len256 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len512 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len1024 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len2048 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len4096 ;
+extern const csi_rfft_instance_q31 csi_rfft_sR_q31_len8192 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len32 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len64 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len128 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len256 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len512 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len1024 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len2048 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len4096 ;
+extern const csi_rfft_instance_q15 csi_rfft_sR_q15_len8192 ;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len32;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len64;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len128;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len256;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len512;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len1024;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len2048;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len4096;
+extern const csi_rfft_instance_f32 csi_inv_rfft_sR_f32_len8192;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len32;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len64;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len128;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len256;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len512;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len1024;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len2048;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len4096;
+extern const csi_rfft_instance_q31 csi_inv_rfft_sR_q31_len8192;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len32;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len64;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len128;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len256;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len512;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len1024;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len2048;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len4096;
+extern const csi_rfft_instance_q15 csi_inv_rfft_sR_q15_len8192;
+extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len128;
+extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len512;
+extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len2048;
+extern const csi_dct4_instance_q31 csi_dct4_sR_q31_len8192;
+extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len128;
+extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len512;
+extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len2048;
+extern const csi_dct4_instance_q15 csi_dct4_sR_q15_len8192;
+extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len128;
+extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len512;
+extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len2048;
+extern const csi_dct4_instance_f32 csi_dct4_sR_f32_len8192;
+
+#endif
--- a/Show More
+++ b/Show More