When ESP32's flat build mode is selected with the external PSRAM
on USER_HEAP mode, the ROM strdup internally calls malloc which may
be mapped to a different heap than lib_free, causing cross-heap
allocation issues and system crashes.
This commit adds a new Kconfig option ESP32_DONT_USE_ROM_LIBC to
allow using NuttX libc instead of ROM newlib functions. When
USER_HEAP mode is selected, this option is automatically enabled.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
In ESP32-S3 flat build with USER_HEAP mode, ROM strdup internally calls
malloc which may be mapped to a different heap than lib_free, causing
cross-heap allocation issues and system crashes.
This commit adds a new Kconfig option ESP32S3_DONT_USE_ROM_LIBC to
allow using NuttX libc instead of ROM newlib functions. When USER_HEAP
mode is selected, this option is automatically enabled.
Fixes: 60ca804b56 ("esp32s3: Fix bug related to the PSRAM-allocated task stack")
Signed-off-by: 461911662 <461911662@qq.com>
Reviewed-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Reviewed-by: Almir Okato <almir.okato@espressif.com>
Reviewed-by: Eren Terzioglu <eren.terzioglu@espressif.com>
Wi-Fi used a locally allocated vector_desc, so those CPU interrupt lines
were never recorded in the HAL non_iram_int_mask.
During SPI flash, esp_intr_noniram_disable() therefore did not mask them,
and Wi-Fi ISRs could still run with the cache off.
Now, Wi-Fi IRQs are treated as non-IRAM and get masked while flash/cache is suspended.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Wi-Fi used a locally allocated vector_desc, so those CPU interrupt lines
were never recorded in the HAL non_iram_int_mask.
During SPI flash, esp_intr_noniram_disable() therefore did not mask them,
and Wi-Fi ISRs could still run with the cache off.
Now, Wi-Fi IRQs are treated as non-IRAM and get masked while flash/cache is suspended.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Replace direct putreg32/getreg32 register accesses in esp32s3_cam.c
with cam_ll_* inline functions from Espressif's esp_hal_cam component.
This reduces maintenance burden by using the vendor-provided HAL
abstraction instead of raw register manipulation.
Changes:
- Add lcd_cam_dev_t *hw pointer to driver struct
- Use cam_ll_start/stop/reset/fifo_reset for CAM control
- Use cam_ll_get_interrupt_status/clear_interrupt_status for ISR
- Use cam_ll_set_recv_data_bytelen for DMA buffer length
- Use cam_ll_select_clk_src/set_group_clock_coeff for clock config
- Use cam_ll_enable_vsync_filter/set_vsync_filter_thres
- Use cam_ll_enable_vsync_generate_eof/enable_rgb_yuv_convert
- Use struct access for interrupt enable (cam_ll_enable_interrupt
requires __DECLARE_RCC_ATOMIC_ENV not available in NuttX)
- Add esp_hal_cam include paths to hal.mk
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
This commit introduces the necessary changes to enable low power
mode for ESP32-P4. Please check the corresponding documentation.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This adds support for the PBKDF2 algorithm in the ESP32 crypto
driver. Here, it will take advantage of the hardware-accelerated
implementation of SHA.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
Add an RP23xx hardware crypto driver for /dev/crypto with SHA-256
support backed by the RP2350 SHA accelerator.
Wire the new driver into the RP23xx ARM build and register
CRYPTO_SHA2_256 through cryptodev.
Also fix the RP23xx SHA256 CSR BSWAP bit definition in both the ARM and
RISC-V RP23xx headers. The previous value used bit 18, but the RP2350
hardware uses bit 12. Without this fix, the accelerator hashed input
words with the wrong byte order and produced incorrect digests.
Signed-off-by: karaketir16 <osmankaraketir@gmail.com>
Implement imgdata_ops alloc/free callbacks so the V4L2 framework
can use MMAP mode to allocate frame buffers with proper GDMA
alignment. This lets applications avoid hardcoding platform-
specific alignment values.
- Add esp32s3_cam_alloc() using kmm_memalign with the alignment
derived from the GDMA external memory block size setting.
- Add esp32s3_cam_free() wrapper around kmm_free.
- Introduce ESP32S3_CAM_EXT_MEMBLK / ESP32S3_CAM_DMA_ALIGN macros
so the block size enum and byte alignment are defined in one
place and stay in sync automatically.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Fix several issues in the ESP32-S3 CAM driver:
- stop_capture: reset DMA channel, CAM module and AFIFO under
spinlock to fully quiesce hardware before returning. Clear
pending VSYNC interrupt to prevent stale ISR firing.
- uninit: reset CAM/AFIFO before releasing DMA to prevent
in-flight transfers after channel detach. Use esp_teardown_irq
with correct peripheral ID (ESP32S3_PERIPH_LCD_CAM) instead of
irq_detach which corrupts the shared IRQ mapping table. Mask
interrupts and clear pending flags under spinlock before
detaching handler.
- uninit: preserve XCLK output so the sensor remains accessible
via I2C for subsequent re-initialization.
- set_buf/uninit: track driver-allocated vs user-provided frame
buffers with fb_allocated flag to prevent double-free when
using V4L2 USERPTR mode.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
arch/arm/include/imx6/irq.h looks to originally be for i.MX6 Quad
and includes multiple (re)definitions of IRQ names, some of which are
different or don't exist on i.MX6 SoloLite/Solo/Dual/DualLite.
Update irq.h to specify/reserve IRQ names/numbers as defined by the
IM6SDLRM, IMX6DLRM, and IMX6DQRM reference manuals.
Signed-off-by Peter Barada <peter.barada@gmail.com>
The struct stm32_mdio_bus_s aka g_stm32_mdio_bus
has not been referenced at all, because mdio_register()
allocates its own structure. Then lower half drivers
receive only their respective part in mdio_read()
and mdio_write() because MDIO_WRITE/MDIO_READ provides
only d->lower to the specific lower level drivers.
Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
Protect the common Espressif Wi-Fi netdev RX queue with a spinlock. The Wi-Fi RX callback enqueues packets while the netdev upper-half RX thread dequeues them, and the IOB queue helpers are not internally serialized.
Under sustained receive traffic that race can corrupt the queue state, strand IOBs, and degrade throughput over time as reported in issue #16915.
Initialize the lock during device setup and use it when clearing the queue on ifup, enqueueing received packets, and dequeuing them for the upper half.
Signed-off-by: aviralgarg05 <gargaviral99@gmail.com>
Align RISC-V timer integration with Xtensa by replacing the
legacy systimer-thread backend with esp_timer adapter layers.
Rename local GPTIMER files to avoid header ambiguity, and
update board/build integration plus sdkconfig timer task
options for HAL compatibility.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
arm_dispatch_syscall in armv7-m clobbered r11 with 'mov r11, sp' and the
user-space callee-saved register value leaked back through the exception
frame when SYS_syscall_return restored the context, resulting in corrupted
parameters on subsequent syscalls and system hangs in protected builds.
In armv6-m, r4 was used to load g_stublookup (Thumb-1 cannot use ip for
indexed addressing) but was not restored before SYS_syscall_return,
causing the same class of register corruption.
Fix with minimal changes:
- armv7-m: remove 'mov r11, sp' to stop clobbering user r11
- armv6-m: restore r4 from the stack frame before SYS_syscall_return
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
debug.h is a NuttX-specific, non-POSIX header. Placing it in the
top-level include/ directory creates naming conflicts with external
projects that define their own debug.h.
This commit moves the canonical header to include/nuttx/debug.h,
following the NuttX convention for non-POSIX/non-standard headers,
and updates all in-tree references.
A backward-compatibility shim is left at include/debug.h that
emits a deprecation #warning and re-includes <nuttx/debug.h>,
allowing out-of-tree code to continue building while migrating.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
esp_ws2812.h exposes esp_ws2812_setup() with a struct rmt_dev_s * argument
but did not include esp_rmt.h directly.
After guarding the LIRC board registration path with CONFIG_DRIVERS_RC,
non-RC ESP configs no longer pulled in the RMT type indirectly and CI
started failing with an incomplete struct rmt_dev_s declaration.
Include esp_rmt.h in the Xtensa and RISC-V ws2812 headers.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
Add documentation for the RC/LIRC character driver subsystem covering
device registration, the LIRC interface, and usage from user space.
Remove placeholder empty files under drivers/rmt that were left over
from the rmtchar era and are no longer referenced.
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
Replace the ESP-specific rmtchar upper-half with arch-local esp_lirc
adapters for Xtensa and RISC-V.
This moves the RMT upper-half out of drivers/rmt, registers LIRC
devices from the ESP board bring-up paths, and removes the old common
rmtchar driver and headers.
Also update the ESP Kconfig and build wiring to build esp_lirc when
ESP_RMT and DRIVERS_RC are enabled.
Fixes discovered during hardware validation:
- register TX as /dev/lirc1 so RX and TX do not collide
- parse the RX worker thread argument from the correct argv slot
- keep RX devices from advertising TX capability
Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
The I2S BCLK frequency is calculated as:
bclk = sample_rate * total_slot * data_width
Previously, total_slot was always taken from the static config
(esp_i2s0_config / esp_i2s1_config), which is hardcoded to 2.
This is correct for mono and stereo, but wrong for TDM modes
with more than 2 channels (e.g. 4-channel recording with ES7210).
With 4 channels but total_slot=2, the BCLK is only half of what
it should be, causing the actual sample rate to be half of the
requested rate (e.g. requesting 16 kHz actually samples at 8 kHz).
Replace priv->config->total_slot with MAX(priv->channels, 2) in
all three BCLK calculation sites (i2s_check_mclkfrequency and
i2s_set_clock for both master and slave paths). The MIN of 2
preserves the I2S protocol requirement that at least 2 slots
exist even for mono, while correctly scaling for multi-channel
TDM configurations.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Fix multiple bugs in the I2S RX receive path on ESP32-S3 with GDMA:
- Set streaming=true in i2s_rxdma_start so completed buffers are not
incorrectly marked AUDIO_APB_FINAL
- Restore up_enable_irq calls for DMA interrupt after esp_dma_load
resets the channel
- Skip i2s_hal_rx_reset/rx_reset_fifo on ESP32-S3 which clears the
TDM slot configuration set by i2s_configure
- Accept 1-16 RX channels on ESP32-S3 (was limited to 2)
- Add getreg32 read-back after DMA start to flush CPU write buffer
- Auto-stop RX channel when no pending buffers remain, preventing
hardware from running without DMA descriptors after stop
- Remove duplicate return OK in i2s_rxdma_start
- Fix i2s_ll_tx_enable_mono_mode to i2s_ll_rx_enable_mono_mode in
i2s_rxchannels
- Fix tx_slot_cfg.std to rx_slot_cfg.std in RX PCM slot config
- Fix DMA direction, peripheral ID, data_width, rx_start sequencing,
and rx_eof_num word count in RX path
- Fix esp32s3_board_i2s.c I2S port index
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Use static lower-half instances per timer and select the channel
through Kconfig and board data instead of passing runtime PWM
routing into the driver.
This keeps the HT32 PWM support aligned with the existing NuttX
pattern and documents the esk32 single-device TMR3 routing.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Adds CMake build support. Touches arch and board at the same time to avoid
creating a commit that is not able to build.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
On ESP32-P4 rev < v3, the 768KB HP L2MEM is split into two
non-contiguous regions: sram_low and sram_high. Previously only
sram_low was used for the heap, wasting 384KB of sram_high.
Export _sram_high_heap_start and _sram_high_heap_end symbols from
the linker script and add sram_high to the heap via kumm_addregion()
in riscv_addregion() when MM_REGIONS > 1.
Signed-off-by: likun17 <likun17@xiaomi.com>
The chip revision check was disabled with #if 0 for v1.0 bringup.
Restore the original #ifndef ESP32P4_IGNORE_CHIP_REVISION_CHECK
guard so boards can selectively bypass the PANIC by defining
this macro, while keeping the warning message in the #else branch.
Signed-off-by: likun17 <likun17@xiaomi.com>
Add ESPRESSIF_FLASH_32M Kconfig option and the corresponding
esptool flash size mapping in Config.mk to support boards with
32MB NOR flash.
Signed-off-by: likun17 <likun17@xiaomi.com>
Document the HT32F491x3 ESK32 board, build steps,
flashing flow, and validation commands. Add WSL and
PowerShell flash backends plus a Python wrapper.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
Add initial HT32F491x3 support with startup, IRQ handling,
serial console, GPIO helpers, custom vectors, and CMake build files.
Signed-off-by: Felipe Moura <moura.fmo@gmail.com>
include/cxx contains NuttX's mini C++ ABI shims and must only be added
to the include path when CONFIG_LIBMINIABI is selected. tools/Config.mk
was adding it unconditionally for every non-LIBCXX/non-UCLIBCXX build,
and the platform.cmake files for arm, arm64, risc-v, x86_64 and tricore
were adding it inside the CONFIG_LIBCXXTOOLCHAIN block.
With an unpatched downloaded ARM GNU Toolchain, <cstdlib> uses
newlib's stdlib.h, defining div_t as an anonymous struct. A later
inclusion of NuttX's stdlib.h via <cstdio>->stdio.h->kmalloc.h then
redefines div_t with struct tag div_s, causing a conflicting declaration
error.
Guard the div_t/ldiv_t/lldiv_t definitions in stdlib.h with
redefinitions when a toolchain stdlib.h was already processed.
Also fix lldiv_s members typed as long instead of long long.
Signed-off-by: trns1997 <trns1997@gmail.com>
- Remove debug polling loop from esp32s3_cam_start_capture() that
busy-waited on DMA status register.
- Fix DMA ISR race: stop DMA before invoking capture callback to
prevent ISR re-triggering while callback processes the buffer.
Check priv->capturing before restarting DMA in ISR.
- Move DMA descriptors from struct to heap allocation, avoiding
stack/BSS alignment issues with cache-line-aligned descriptors.
Signed-off-by: wangjianyu3 <wangjianyu3@xiaomi.com>
Export qemu_rv_configure_mpu() and invoke it on the secondary-hart
boot path before riscv_cpu_boot().
This keeps protected SMP builds from faulting on !CPU0 when userspace
work is first scheduled there.
Signed-off-by: Shunchao Hu <ankohuu@gmail.com>
This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.
Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements
Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
options from interrupt sources to CPU interrupts, providing flexibility
required by modern peripherals. Although this introduces breaking changes
to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
Kconfig option is explicitly checked during startup to ensure proper
configuration. This validation prevents runtime issues from configuration
mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
NuttX-native implementations of xt_ints_on/off and interrupt handlers,
avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
RTC/RT-timer code to common-source Espressif integration, including
esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
implementation, including common-source auto-sleep behavior, UART/Wi-Fi
wakeup coordination, and tickless-safe sleep flow compatibility.
Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.
Tested configurations:
- All defconfigs were tested, including `ostest`.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Tiago Medicci Serrano
461911662
Peter van der Perk
raiden00pl
Filipe Cavalcanti
wangjianyu3
Vlad Pruteanu
simbit18
karaketir16
Peter Barada
Eren Terzioglu
Pavel Pisa
aviralgarg05
Jiri Vlasak
buxiasen
Piyush Patle
Felipe Moura
p-szafonimateusz
likun17
trns1997
Shunchao Hu