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xtensa/espressif: Update common-source integration for Xtensa devices

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This commit updates the common-source integration for Xtensa-based
Espressif devices (ESP32, ESP32-S2, and ESP32-S3). This is part of a larger
common-source update split by architecture for better maintainability.

Major components updated:
- IRQ allocator refactoring with intr_alloc integration
- Common-source drivers (GPIO, RMT, I2C, SPI, UART, etc.)
- Espressif components upgrade to release/master.b-test
- Peripheral drivers (ADC, PWM, LEDC, MCPWM, PCNT, Temperature Sensor, etc.)
- Wireless adapters (Wi-Fi and BLE)
- esp_timer migration to the common-source path for Xtensa devices
- Common-source power management implementation (auto-sleep and wakeup paths)
- Board defconfigs for all Xtensa Espressif boards
- SMP support improvements for ESP32-S3
- Critical section handling improvements

Key architectural changes:
- IRQ Allocator: The new interrupt allocator enables multiple mapping
  options from interrupt sources to CPU interrupts, providing flexibility
  required by modern peripherals. Although this introduces breaking changes
  to the interrupt handling API, the required ARCH_MINIMAL_VECTORTABLE
  Kconfig option is explicitly checked during startup to ensure proper
  configuration. This validation prevents runtime issues from configuration
  mismatches.
- Xtensa-specific interrupt handling via esp_xtensa_intr.c providing
  NuttX-native implementations of xt_ints_on/off and interrupt handlers,
  avoiding conflicts with NuttX's core Xtensa macros.
- Timer/RTC unification: ESP32/ESP32-S2/ESP32-S3 move from chip-specific
  RTC/RT-timer code to common-source Espressif integration, including
  esp_timer_adapter/esp_rtc paths and the required bringup/defconfig updates.
- Power management consolidation: Xtensa PM follows the common-source
  implementation, including common-source auto-sleep behavior, UART/Wi-Fi
  wakeup coordination, and tickless-safe sleep flow compatibility.

Note: This is a large commit to maintain bisectability. Breaking the
changes into smaller commits would result in non-building intermediate
states across the common-source infrastructure update.

Tested configurations:
- All defconfigs were tested, including `ostest`.

Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit is contained in:
Tiago Medicci Serrano
2026-02-27 15:06:57 -03:00
committed by Xiang Xiao
parent c64b95ccbf
commit c17e16eaed
621 changed files with 11436 additions and 53138 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/src/common/espressif/Make.defs
+1 -1
View File
@@ -207,7 +207,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309
ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif
ifndef ESP_HAL_3RDPARTY_URL
arch/xtensa/Kconfig
+3
View File
@@ -22,6 +22,7 @@ config ARCH_CHIP_ESP32
select ARCH_HAVE_TESTSET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
@@ -56,6 +57,7 @@ config ARCH_CHIP_ESP32S2
select ARCH_HAVE_RESET
select ARCH_HAVE_TEXT_HEAP
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
@@ -92,6 +94,7 @@ config ARCH_CHIP_ESP32S3
select ARCH_DCACHE
select ARCH_ICACHE
select ARCH_VECNOTIRQ
select ARCH_MINIMAL_VECTORTABLE
select LIBC_PREVENT_STRING_KERNEL
select LIBC_ARCH_MEMCPY if BUILD_FLAT
select LIBC_ARCH_MEMCHR if BUILD_FLAT
arch/xtensa/include/esp32/irq.h
+27 -10
View File
@@ -39,7 +39,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32_setup_irq needs.
* code calling esp_setup_irq needs.
*/
#define ESP32_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -190,24 +190,39 @@
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
* interrupts. These use negative source IDs for internal CPU interrupts.
*/
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* Legacy definitions for compatibility */
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id)+XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32_PERIPH2IRQ(id)
/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
@@ -299,7 +314,7 @@
#define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS
#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* The PRO and APP CPU have different interrupts sources for the GPIO
* peripheral. Each CPU needs to allocate a separate interrupt and attach
@@ -325,6 +340,8 @@
# define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1)
# define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ)
# define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32_IRQ2PIN(i)
#else
# define ESP32_NIRQ_GPIO 0
#endif
@@ -477,7 +494,7 @@
* Inline functions
****************************************************************************/
#ifdef CONFIG_ESP32_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
#ifdef CONFIG_SMP
static inline_function int esp32_irq_gpio(int cpu)
{
arch/xtensa/include/esp32s2/irq.h
+19 -9
View File
@@ -197,14 +197,19 @@
* interrupts
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -213,6 +218,9 @@
#define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32S2_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S2_PERIPH2IRQ(id)
#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC_NMI)
@@ -304,12 +312,14 @@
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 47
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S2_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S2_IRQ2PIN(i)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
@@ -360,7 +370,7 @@
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
arch/xtensa/include/esp32s3/irq.h
+20 -11
View File
@@ -41,7 +41,7 @@
/* CPU interrupt flags:
* These flags can be used to specify which interrupt qualities the
* code calling esp32s3_setup_irq needs.
* code calling esp_setup_irq needs.
*/
#define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */
@@ -156,7 +156,6 @@
#define ESP32S3_PERIPH_AES 77
#define ESP32S3_PERIPH_SHA 78
#define ESP32S3_PERIPH_INT_FROM_CPU0 79
#define ESP32S3_PERIPH_INT_FROM_CPU1 80
#define ESP32S3_PERIPH_INT_FROM_CPU2 81
#define ESP32S3_PERIPH_INT_FROM_CPU3 82
@@ -201,14 +200,19 @@
* interrupts.
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_SWINT 4 /* Software interrupt */
#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */
#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */
#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */
#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */
#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */
#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */
#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */
#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */
#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
@@ -217,6 +221,9 @@
#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
#define ESP_IRQ2SOURCE(irq) ESP32S3_IRQ2PERIPH(irq)
#define ESP_SOURCE2IRQ(id) ESP32S3_PERIPH2IRQ(id)
#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
@@ -329,7 +336,7 @@
#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
#ifdef CONFIG_ESP32S3_GPIO_IRQ
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
@@ -341,6 +348,8 @@
# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
# define ESP_PIN2IRQ(p) ESP32S3_PIN2IRQ(p)
# define ESP_IRQ2PIN(i) ESP32S3_IRQ2PIN(i)
#else
# define ESP32S3_NIRQ_GPIO 0
#endif
@@ -392,7 +401,7 @@
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO)
/* Xtensa CPU Interrupts.
*
arch/xtensa/src/common/espressif/Kconfig
+243 -20
View File
@@ -1,3 +1,73 @@
menu "Espressif Log Level"
visible if DEBUG_FEATURES
config ESPRESSIF_LOG_LEVEL_NONE
bool "NONE"
depends on !DEBUG_FEATURES && !DEBUG_ERROR && !DEBUG_WARN && !DEBUG_INFO
default y
---help---
No log output from Espressif log messages.
config ESPRESSIF_LOG_LEVEL_ERROR
bool "ERROR"
depends on DEBUG_ERROR
default y
---help---
Display critical errors from Espressif log messages.
config ESPRESSIF_LOG_LEVEL_WARN
bool "WARN"
depends on DEBUG_WARN
default y
---help---
Display warning messages from Espressif log messages.
config ESPRESSIF_LOG_LEVEL_INFO
bool "INFO"
depends on DEBUG_INFO
default y
---help---
Display information messages from Espressif log messages.
config ESPRESSIF_LOG_LEVEL_DEBUG
bool "DEBUG"
depends on DEBUG_INFO
default n
---help---
Display extra information from Espressif log messages.
config ESPRESSIF_LOG_LEVEL_VERBOSE
bool "VERBOSE"
depends on DEBUG_INFO
default n
---help---
Display bigger chunks of debugging information, or frequent messages
which can potentially flood the output from Espressif log messages.
config ESPRESSIF_LOG_LEVEL
int
default 5 if ESPRESSIF_LOG_LEVEL_VERBOSE
default 4 if ESPRESSIF_LOG_LEVEL_DEBUG
default 3 if ESPRESSIF_LOG_LEVEL_INFO
default 2 if ESPRESSIF_LOG_LEVEL_WARN
default 1 if ESPRESSIF_LOG_LEVEL_ERROR
default 0 if ESPRESSIF_LOG_LEVEL_NONE
endmenu # Espressif Log Level
menu "Interrupt Configuration"
config ESPRESSIF_IRAM_ISR_DEBUG
bool "Enable debugging of the IRAM-enabled interrupts"
default n
---help---
This option enables keeping track of the IRAM-enabled interrupts by
registering its execution when non-IRAM interrupts are disabled. It
keeps track of the IRQ executed and register how many times since
boot it was executed.
endmenu # Interrupt Configuration
config ESP_RMT
bool "Remote Control Module (RMT)"
default n
@@ -132,9 +202,9 @@ config ESPRESSIF_I2S0
select ESPRESSIF_I2S
select I2S
select ESP32S3_DMA if ARCH_CHIP_ESP32S3
select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
select ESP32S2_GPIO_IRQ if ARCH_CHIP_ESP32S2
select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3
select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S2
select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32
select SCHED_HPWORK
select ARCH_DMA
@@ -145,8 +215,8 @@ config ESPRESSIF_I2S1
select ESPRESSIF_I2S
select I2S
select ESP32S3_DMA if ARCH_CHIP_ESP32S3
select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3
select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32
select SCHED_HPWORK
select ARCH_DMA
@@ -219,6 +289,12 @@ config ESPRESSIF_DEDICATED_GPIO
It can work as pin grouping and you can use any pin up to 8 pins for
input and 8 pins for output for dedicated gpio in total.
config ESPRESSIF_GPIO_IRQ
bool "GPIO pin interrupts"
default n
---help---
Enable support for interrupting GPIO pins.
config ESPRESSIF_DEDICATED_GPIO_IRQ
bool "Dedicated GPIO IRQ"
depends on ESPRESSIF_DEDICATED_GPIO && ARCH_CHIP_ESP32S2
@@ -520,7 +596,17 @@ endmenu # LP Core (Low-power core) Coprocessor Configuration
menu "PM Configuration"
if PM && !ARCH_CHIP_ESP32
config ESPRESSIF_AUTO_SLEEP
bool "Auto-sleep"
depends on !ARCH_CHIP_ESP32H2
default n
select PM
select ESPRESSIF_HR_TIMER
select ESP32_TICKLESS if ARCH_CHIP_ESP32
---help---
Enable Auto-sleep
if PM
config PM_EXT1_WAKEUP
bool "PM EXT1 Wakeup"
@@ -643,18 +729,28 @@ config PM_EXT1_WAKEUP_RTC_GPIO17
config PM_EXT1_WAKEUP_RTC_GPIO18
bool "RTC_GPIO18"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO18 as an EXT1 wakeup source.
config PM_EXT1_WAKEUP_RTC_GPIO19
bool "RTC_GPIO19"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO19 as an EXT1 wakeup source.
config PM_EXT1_WAKEUP_RTC_GPIO20
bool "RTC_GPIO20"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO20 as an EXT1 wakeup source.
config PM_EXT1_WAKEUP_RTC_GPIO21
bool "RTC_GPIO21"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable RTC GPIO20 as an EXT1 wakeup source.
@@ -688,7 +784,8 @@ config PM_EXT0_WAKEUP_GPIO
int "EXT0 Wakeup GPIO"
depends on PM_EXT0_WAKEUP
default 0
range 0 20
range 0 17 if ARCH_CHIP_ESP32
range 0 21 if ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
---help---
GPIO to wake the device up from PM_STANDBY or PM_SLEEP using as EXT0 wakeup GPIO
@@ -708,6 +805,7 @@ endmenu # PM_EXT0_WAKEUP_SOURCES
config PM_ULP_WAKEUP
bool "PM ULP Wakeup"
depends on !ARCH_CHIP_ESP32
default n
---help---
Enable ULP coprocessor wakeup functionality.
@@ -726,6 +824,12 @@ config PM_GPIO_WAKEUP
menu "PM GPIO Wakeup Sources"
depends on PM_GPIO_WAKEUP
config PM_GPIO_WAKEUP_GPIO0
bool "GPIO0"
default n
---help---
Enable GPIO0 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO1
bool "GPIO1"
default n
@@ -854,67 +958,175 @@ config PM_GPIO_WAKEUP_GPIO21
config PM_GPIO_WAKEUP_GPIO22
bool "GPIO22"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO22 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO23
bool "GPIO23"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO23 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO24
bool "GPIO24"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO24 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO25
bool "GPIO25"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO25 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO26
bool "GPIO26"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO26 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO27
bool "GPIO27"
depends on !ARCH_CHIP_ESP32C3_GENERIC
default n
---help---
Enable GPIO27 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO28
bool "GPIO28"
depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO28 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO29
bool "GPIO29"
depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO29 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO30
bool "GPIO30"
depends on ARCH_CHIP_ESP32C6
default n
---help---
Enable GPIO30 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO31
bool "GPIO31"
default n
---help---
Enable GPIO31 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO32
bool "GPIO32"
default n
---help---
Enable GPIO32 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO33
bool "GPIO33"
default n
---help---
Enable GPIO33 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO34
bool "GPIO34"
default n
---help---
Enable GPIO34 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO35
bool "GPIO35"
default n
---help---
Enable GPIO35 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO36
bool "GPIO36"
default n
---help---
Enable GPIO36 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO37
bool "GPIO37"
default n
---help---
Enable GPIO37 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO38
bool "GPIO38"
default n
---help---
Enable GPIO38 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO39
bool "GPIO39"
default n
---help---
Enable GPIO39 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO40
bool "GPIO40"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO40 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO41
bool "GPIO41"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO41 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO42
bool "GPIO42"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO42 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO43
bool "GPIO43"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO43 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO44
bool "GPIO44"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO44 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO45
bool "GPIO45"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO45 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO46
bool "GPIO46"
depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO46 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO47
bool "GPIO47"
depends on ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO47 as an GPIO wakeup source.
config PM_GPIO_WAKEUP_GPIO48
bool "GPIO48"
depends on ARCH_CHIP_ESP32S3
default n
---help---
Enable GPIO48 as an GPIO wakeup source.
choice PM_GPIO_WAKEUP_TRIGGER_MODE
prompt "PM GPIO Wakeup Trigger Mode"
default PM_GPIO_WAKEUP_TRIGGER_ANY_LOW
@@ -931,7 +1143,7 @@ endmenu # PM_GPIO_WAKEUP_SOURCES
config PM_UART_WAKEUP
bool "PM UART Wakeup"
depends on ESP32S3_UART0 || ESP32S3_UART1
depends on ESP32_UART0 || ESP32_UART1 || ESP32S3_UART0 || ESP32S3_UART1
default n
---help---
Enable UART wakeup functionality.
@@ -943,15 +1155,17 @@ menu "PM UART Wakeup Sources"
choice PM_UART_WAKEUP_UART_NUM
prompt "PM UART Wakeup UART Number"
default PM_UART_WAKEUP_UART0 if ESP32_UART0
default PM_UART_WAKEUP_UART1 if ESP32_UART1
default PM_UART_WAKEUP_UART0 if ESP32S3_UART0
default PM_UART_WAKEUP_UART1 if ESP32S3_UART1
config PM_UART_WAKEUP_UART0
depends on ESP32S3_UART0
depends on ESP32_UART0 || ESP32S3_UART0
bool "Wake the chip up when UART0 gets a data"
config PM_UART_WAKEUP_UART1
depends on ESP32S3_UART1
depends on ESP32_UART1 || ESP32S3_UART1
bool "Wake the chip up when UART1 gets a data"
endchoice # PM_UART_WAKEUP_UART_NUM
@@ -986,7 +1200,7 @@ config PM_SLEEP_WAKEUP_NSEC
---help---
Number of additional nanoseconds to wait in PM_SLEEP.
endif # PM && !ARCH_CHIP_ESP32
endif # PM
endmenu # PM Configuration
@@ -2262,3 +2476,12 @@ config ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS
Number of interrupt save status variables to keep track. Increase it if any related bug is found.
endmenu # BLE Configuration
config ESPRESSIF_HR_TIMER
bool
default RTC_DRIVER
---help---
A high-resolution hardware timer for supporting the management of
kernel events.
The HR Timer is built on top of the System Timer (SYSTIMER) peripheral.
Timer callbacks are dispatched from a high-priority kernel task.
arch/xtensa/src/common/espressif/Make.defs
+15 -4
View File
@@ -20,6 +20,10 @@
#
############################################################################
# Silent preprocessor warnings
CFLAGS += -Wno-shadow -Wno-undef
ifeq ($(CONFIG_ESP_RMT),y)
CHIP_CSRCS += esp_rmt.c
ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y)
@@ -124,19 +128,26 @@ ifeq ($(CONFIG_ESPRESSIF_ADC),y)
CHIP_CSRCS += esp_adc.c
endif
ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp_pm_initialize.c
endif
CHIP_CSRCS += esp_pm.c
LDFLAGS += -u esp_timer_init_include_func
endif
endif
CHIP_CSRCS += esp_efuse.c
CHIP_CSRCS += esp_efuse.c esp_irq.c esp_xtensa_intr.c esp_gpio.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp_rtc.c
endif
ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y)
CHIP_CSRCS += esp_timer_adapter.c
endif
LDFLAGS += -u esp_system_include_startup_funcs
LDFLAGS += -u esp_timer_init_include_func
ifeq ($(CONFIG_ESPRESSIF_EFUSE),y)
LDFLAGS += -u esp_efuse_startup_include_func
endif
arch/xtensa/src/common/espressif/Wireless.mk
+52 -14
View File
@@ -20,6 +20,8 @@
#
############################################################################
WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
ifeq ($(CONFIG_ARCH_CHIP_ESP32),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include
endif
@@ -27,6 +29,7 @@ ifeq ($(CONFIG_ARCH_CHIP_ESP32S3),y)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)$(DELIM)wifi_apps$(DELIM)roaming_app$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi
@@ -59,21 +62,32 @@ ifeq ($(CONFIG_WPA_WAPI_PSK),y)
EXTRA_LIBS += -lwapi
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
ifeq ($(CONFIG_ESPRESSIF_WIFI),y)
## ESP-IDF's mbedTLS
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls
### Define Espressif's configs for mbedTLS
CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="<mbedtls/esp_config.h>"
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src
CHIP_CSRCS += aes.c
CHIP_CSRCS += aria.c
CHIP_CSRCS += bignum_core.c
@@ -110,21 +124,48 @@ CHIP_CSRCS += hmac_drbg.c
CHIP_CSRCS += rsa_alt_helpers.c
CHIP_CSRCS += ecdh.c
CHIP_CSRCS += pk_ecc.c
CHIP_CSRCS += pk_rsa.c
CHIP_CSRCS += psa_util.c
CHIP_CSRCS += psa_crypto_ffdh.c
CHIP_CSRCS += psa_crypto_ecp.c
CHIP_CSRCS += psa_crypto_rsa.c
CHIP_CSRCS += psa_crypto_cipher.c
CHIP_CSRCS += psa_crypto_mac.c
CHIP_CSRCS += psa_crypto_hash.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core
CHIP_CSRCS += psa_crypto_client.c
CHIP_CSRCS += psa_crypto_driver_wrappers_no_static.c
CHIP_CSRCS += psa_crypto_slot_management.c
CHIP_CSRCS += psa_crypto_storage.c
CHIP_CSRCS += psa_crypto.c
CHIP_CSRCS += psa_its_file.c
CHIP_CSRCS += tf_psa_crypto_config.c
CHIP_CSRCS += tf_psa_crypto_version.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port
CHIP_CSRCS += esp_psa_crypto_init.c
CHIP_CSRCS += esp_hardware.c
CHIP_CSRCS += esp_mem.c
CHIP_CSRCS += esp_timing.c
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md
# Ensure PSA crypto initialization is included in the build
CHIP_CSRCS += esp_md.c
LDFLAGS += -u mbedtls_psa_crypto_init_include_impl
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_mac
ifneq ($(CONFIG_ARCH_CHIP_ESP32),y)
CHIP_CSRCS += psa_crypto_driver_esp_hmac_opaque.c
endif
VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_md
CHIP_CSRCS += psa_crypto_driver_esp_md5.c
## WPA Supplicant
WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant
CFLAGS += $(DEFINE_PREFIX)__ets__
CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS
CFLAGS += $(DEFINE_PREFIX)CONFIG_ECC
@@ -132,14 +173,18 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W
CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE
CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD
CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1
CFLAGS += $(DEFINE_PREFIX)TF_PSA_CRYPTO_USER_CONFIG_FILE=\"mbedtls/esp_config.h\"
CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT
CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE
CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL
CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK
CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK
ifeq ($(CONFIG_ESPRESSIF_WIFI_SOFTAP_SAE_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE
endif
ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK
endif
@@ -160,9 +205,6 @@ ifeq ($(CONFIG_ESPRESSIF_WIFI_GMAC_SUPPORT),y)
CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC
endif
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap
@@ -193,7 +235,6 @@ VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto
CHIP_CSRCS += aes-ccm.c
CHIP_CSRCS += aes-gcm.c
CHIP_CSRCS += aes-omac1.c
CHIP_CSRCS += aes-unwrap.c
CHIP_CSRCS += aes-wrap.c
CHIP_CSRCS += ccmp.c
@@ -246,8 +287,6 @@ CHIP_CSRCS += os_xtensa.c
## ESP Supplicant (Espressif's WPA supplicant extension)
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include
VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src
@@ -272,7 +311,6 @@ CHIP_CSRCS += crypto_mbedtls.c
CHIP_CSRCS += tls_mbedtls.c
CHIP_CSRCS += aes-siv.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)lib_printf.c
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)regulatory$(DELIM)esp_wifi_regulatory.c
arch/xtensa/src/common/espressif/esp_adc.c
+4 -7
View File
@@ -45,16 +45,16 @@
#include "hal/adc_oneshot_hal.h"
#include "hal/adc_ll.h"
#include "hal/sar_ctrl_ll.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/periph_defs.h"
#include "esp_clk_tree.h"
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "esp32_gpio.h"
#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -66,15 +66,12 @@
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32
# define esp_configgpio esp32_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_3
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S2
# define esp_configgpio esp32s2_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
#ifdef CONFIG_ARCH_CHIP_ESP32S3
# define esp_configgpio esp32s3_configgpio
# define GPIO_ADC_FUNCTION FUNCTION_2
#endif
arch/xtensa/src/common/espressif/esp_dedic_gpio.c
+26 -41
View File
@@ -46,19 +46,14 @@
#include "chip.h"
#include "esp_dedic_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_irq.h"
#include "esp32s2_gpio.h"
#endif
#include "espressif/esp_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "soc/dedic_gpio_struct.h"
#endif
#include "hal/dedic_gpio_ll.h"
#include "hal/dedic_gpio_cpu_ll.h"
#include "soc/dedic_gpio_periph.h"
#include "hal/dedic_gpio_periph.h"
#include "hal/dedic_gpio_caps.h"
#include "soc/gpio_sig_map.h"
#include "periph_ctrl.h"
#include "soc/soc_caps.h"
@@ -71,19 +66,11 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#endif
/****************************************************************************
@@ -252,7 +239,7 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
}
/****************************************************************************
* Name: esp_pcnt_isr_register
* Name: esp_dedic_gpio_isr_register
*
* Description:
* This function registers an interrupt service routine (ISR) for the
@@ -271,29 +258,23 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context,
static int esp_dedic_gpio_isr_register(void)
{
int cpuint;
#ifndef CONFIG_ARCH_CHIP_ESP32S2
int ret;
#endif
int cpu = this_cpu();
uint32_t status;
cpuint = esp_setup_irq(dedic_gpio_periph_signals.irq,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL);
ESP_IRQ_TRIGGER_LEVEL,
esp_dedic_gpio_isr_default,
&dedic_gpio_common[cpu]);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
ret = irq_attach(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH,
esp_dedic_gpio_isr_default,
&dedic_gpio_common[cpu]);
if (ret < 0)
{
cperr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(dedic_gpio_periph_signals.irq, cpuint);
return ERROR;
}
status = dedic_gpio_ll_get_interrupt_status(dedic_gpio_common[cpu].dev);
dedic_gpio_ll_clear_interrupt_status(dedic_gpio_common[cpu].dev, status);
up_enable_irq(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH);
@@ -538,9 +519,9 @@ struct file *esp_dedic_gpio_new_bundle(
}
dedic_gpio_common[cpu].out_occupied_mask =
UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1);
UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1);
dedic_gpio_common[cpu].in_occupied_mask =
UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1);
UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1);
spin_unlock_irqrestore(&dedic_gpio_common[cpu].spinlock, flags);
}
@@ -557,11 +538,12 @@ struct file *esp_dedic_gpio_new_bundle(
out_offset = 0;
if (config->flags->output_enable)
{
if (config->array_size > SOC_DEDIC_GPIO_OUT_CHANNELS_NUM)
if (config->array_size > DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU))
{
gpioerr("ERROR: array size(%d) exceeds maximum supported out\
gpioerr("ERROR: array size(%d) exceeds maximum supported out \
channels(%d)\n",
config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM);
config->array_size,
DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -569,8 +551,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size;
i++)
i <= (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - \
config->array_size);
i++)
{
if ((dedic_gpio_common[cpu].out_occupied_mask & (pattern << i))
== 0)
@@ -608,11 +591,12 @@ struct file *esp_dedic_gpio_new_bundle(
if (config->flags->input_enable)
{
if (config->array_size > SOC_DEDIC_GPIO_IN_CHANNELS_NUM)
if (config->array_size > DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU))
{
gpioerr("ERROR: array size(%d) exceeds maximum supported in\
channels(%d)\n",
config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM);
config->array_size,
DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU));
free(priv);
return NULL;
}
@@ -620,8 +604,9 @@ struct file *esp_dedic_gpio_new_bundle(
flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock);
for (int i = 0;
i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size;
i++)
i <= (DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - \
config->array_size);
i++)
{
if ((dedic_gpio_common[cpu].in_occupied_mask &
(pattern << i)) == 0)
arch/xtensa/src/common/espressif/esp_efuse.c
+4 -10
View File
@@ -42,6 +42,7 @@
#include "xtensa.h"
#include "soc/syscon_reg.h"
#include "esp_efuse_table.h"
#include "hal/efuse_ll.h"
#endif
/****************************************************************************
@@ -345,16 +346,9 @@ uint32_t esp_efuse_hal_chip_revision(void)
uint32_t combine_value;
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1,
&eco_bit0,
ESP_EFUSE_CHIP_VER_REV1[0]->bit_count);
esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2,
&eco_bit1,
ESP_EFUSE_CHIP_VER_REV2[0]->bit_count);
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION_MINOR,
&minor_chip_version,
ESP_EFUSE_WAFER_VERSION_MINOR[0]->bit_count);
eco_bit0 = efuse_ll_get_chip_ver_rev1();
eco_bit1 = efuse_ll_get_chip_ver_rev2();
minor_chip_version = efuse_ll_get_chip_wafer_version_minor();
eco_bit2 = (getreg32(SYSCON_DATE_REG) & 0x80000000) >> 31;
combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
arch/xtensa/src/common/espressif/esp_espnow_pktradio.c
+1 -1
View File
@@ -47,7 +47,7 @@
#include <nuttx/wdog.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp_now.h"
#include "esp_mac.h"
#include "esp_espnow_pktradio.h"
arch/xtensa/src/common/espressif/esp_gpio.c
+457
View File
@@ -0,0 +1,457 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_gpio.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
/* Config */
#include <nuttx/config.h>
/* Libc */
#include <assert.h>
#include <debug.h>
#include <stdint.h>
#include <sys/types.h>
/* NuttX */
#include <arch/irq.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/kmalloc.h>
/* Arch */
#include "xtensa.h"
#include "esp_gpio.h"
#include "esp_irq.h"
/* HAL */
#include "esp_err.h"
#include "soc/interrupts.h"
#include "esp_rom_gpio.h"
#include "hal/gpio_hal.h"
#include "driver/gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define ESP_INTR_FLAG_DEFAULT 0
/****************************************************************************
* Private Data
****************************************************************************/
static gpio_hal_context_t g_gpio_hal =
{
.dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp_intr_handler_adapter
*
* Description:
* This function acts as an adapter to bridge interrupt service routines
* between NuttX and the Espressif's interrupt service routine. It is
* called when a GPIO interrupt occurs, retrieves the function pointer and
* associated data from the 'intr_adapter_from_nuttx' structure passed as
* an argument, and invokes the original user-provided interrupt handler
* with the IRQ number and user argument.
*
* Input Parameters:
* arg - Pointer to a structure of type 'intr_adapter_from_nuttx' that
* holds the handler function, the associated IRQ, the context, and
* the user argument.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
static void esp_intr_handler_adapter(void *arg)
{
struct intr_adapter_from_nuttx *adapter;
adapter = (struct intr_adapter_from_nuttx *)arg;
adapter->func(adapter->irq, adapter->context, adapter->arg);
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
* Input Parameters:
* pin - GPIO pin to be configured.
* attr - Attributes to be configured for the selected GPIO pin.
* The following attributes are accepted:
* - Direction (OUTPUT or INPUT)
* - Pull (PULLUP, PULLDOWN or OPENDRAIN)
* - Function (if not provided, assume function GPIO by
* default)
* - Drive strength (if not provided, assume DRIVE_2 by
* default)
*
* Returned Value:
* Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
int esp_configgpio(int pin, gpio_pinattr_t attr)
{
DEBUGASSERT(pin >= 0 && pin < SOC_GPIO_PIN_COUNT);
/* Handle input pins */
if ((attr & INPUT) != 0)
{
gpio_hal_input_enable(&g_gpio_hal, pin);
}
else
{
gpio_hal_input_disable(&g_gpio_hal, pin);
}
if ((attr & OPEN_DRAIN) != 0)
{
gpio_hal_od_enable(&g_gpio_hal, pin);
}
else
{
gpio_hal_od_disable(&g_gpio_hal, pin);
}
if ((attr & OUTPUT) != 0)
{
gpio_hal_output_enable(&g_gpio_hal, pin);
}
else
{
gpio_hal_output_disable(&g_gpio_hal, pin);
}
if ((attr & PULLUP) != 0)
{
gpio_pullup_en(pin);
}
else
{
gpio_pullup_dis(pin);
}
if ((attr & PULLDOWN) != 0)
{
gpio_pulldown_en(pin);
}
else
{
gpio_pulldown_dis(pin);
}
gpio_hal_set_intr_type(&g_gpio_hal, pin,
(attr & INTR_TYPE_MASK) >> INTR_TYPE_SHIFT);
if ((attr & DRIVE_MASK) != 0)
{
uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1;
gpio_hal_set_drive_capability(&g_gpio_hal, pin, val);
}
else
{
gpio_hal_set_drive_capability(&g_gpio_hal, pin,
GPIO_DRIVE_CAP_DEFAULT);
}
if ((attr & FUNCTION_MASK) != 0)
{
uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1;
gpio_hal_func_sel(&g_gpio_hal, pin, val);
}
else
{
gpio_hal_func_sel(&g_gpio_hal, pin, PIN_FUNC_GPIO);
}
return OK;
}
/****************************************************************************
* Name: esp_gpio_matrix_in
*
* Description:
* Set GPIO input to a signal.
* NOTE: one GPIO can receive inputs from several signals.
*
* Input Parameters:
* pin - GPIO pin to be configured.
* - If pin == 0x3c, cancel input to the signal, input 0
* to signal.
* - If pin == 0x3a, input nothing to signal.
* - If pin == 0x38, cancel input to the signal, input 1
* to signal.
* signal_idx - Signal index.
* inv - Flag indicating whether the signal is inverted.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv)
{
esp_rom_gpio_connect_in_signal(pin, signal_idx, inv);
}
/****************************************************************************
* Name: esp_gpio_matrix_out
*
* Description:
* Set signal output to GPIO.
* NOTE: one signal can output to several GPIOs.
*
* Input Parameters:
* pin - GPIO pin to be configured.
* signal_idx - Signal index.
* - If signal_idx == 0x100, cancel output to the GPIO.
* out_inv - Flag indicating whether the signal output is inverted.
* oen_inv - Flag indicating whether the signal output enable is
* inverted.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
bool oen_inv)
{
esp_rom_gpio_connect_out_signal(pin, signal_idx, out_inv, oen_inv);
}
/****************************************************************************
* Name: esp_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
* Input Parameters:
* pin - GPIO pin to be modified.
* value - The value to be written (0 or 1).
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_gpiowrite(int pin, bool value)
{
DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT);
gpio_hal_set_level(&g_gpio_hal, pin, value);
}
/****************************************************************************
* Name: esp_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
* Input Parameters:
* pin - GPIO pin to be read.
*
* Returned Value:
* The boolean representation of the input value (true/false).
*
****************************************************************************/
bool esp_gpioread(int pin)
{
DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT);
return gpio_hal_get_level(&g_gpio_hal, pin) != 0;
}
/****************************************************************************
* Name: esp_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
void esp_gpioirqinitialize(void)
{
/* Setup the GPIO interrupt. */
gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);
}
#endif
/****************************************************************************
* Name: esp_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO
*
* Input Parameters:
* id - GPIO to be enabled.
*
* Returned Value:
* Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpioirqenable(int id)
{
esp_err_t esp_ret;
esp_ret = gpio_intr_enable(id);
if (esp_ret != ESP_OK)
{
gpioerr("gpio_intr_enable() failed: %d\n", esp_ret);
return -ERROR;
}
return OK;
}
#endif
/****************************************************************************
* Name: esp_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO
*
* Input Parameters:
* id - GPIO to be disabled.
*
* Returned Value:
* Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpioirqdisable(int id)
{
esp_err_t esp_ret;
esp_ret = gpio_intr_disable(id);
if (esp_ret != ESP_OK)
{
gpioerr("gpio_intr_disable() failed: %d\n", esp_ret);
return -ERROR;
}
return OK;
}
#endif
/****************************************************************************
* Name: esp_gpio_irq
*
* Description:
* Register or unregister a button interrupt handler for the specified
* button ID. Passing a non-NULL handler attaches and enables the ISR for
* the button; passing NULL disables the interrupt and removes any
* previously registered handler.
*
* Input Parameters:
* id - Identifies the button to be monitored.
* irqhandler - The handler to be called when the interrupt occurs.
* Set to NULL to disable the interrupt.
* arg - Pointer to the argument that will be provided to the
* interrupt handler.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg)
{
int ret;
int irq = ESP_PIN2IRQ(id);
if (NULL != irqhandler)
{
esp_err_t esp_ret;
struct intr_adapter_from_nuttx *adapter;
gpioinfo("Attach %p\n", irqhandler);
adapter = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx));
if (adapter == NULL)
{
gpioerr("kmm_calloc() failed\n");
return -ERROR;
}
adapter->func = irqhandler;
adapter->irq = irq;
adapter->context = NULL;
adapter->arg = arg;
esp_ret = gpio_isr_handler_add(id, esp_intr_handler_adapter,
(void *)adapter);
if (esp_ret != ESP_OK)
{
gpioerr("gpio_isr_handler_add() failed: %d\n", ret);
return -ERROR;
}
}
else
{
gpioinfo("Disable the interrupt\n");
gpio_isr_handler_remove(id);
}
return OK;
}
#endif
arch/xtensa/src/esp32s2/esp32s2_gpio.h → arch/xtensa/src/common/espressif/esp_gpio.h
+150 -143
View File
@@ -1,5 +1,7 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_gpio.h
* arch/xtensa/src/common/espressif/esp_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,14 +20,15 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <stdbool.h>
#include <stdint.h>
@@ -34,17 +37,17 @@
* Pre-processor Definitions
****************************************************************************/
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT sig */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
/* Bit-encoded input to esp32s2_configgpio() ********************************/
/* Bit-encoded input to esp_configgpio() ************************************/
/* Encoded pin attributes used with esp32s2_configgpio()
/* Encoded pin attributes used with esp_configgpio()
*
* 8 7 6 5 4 3 2 1 0
* -- -- -- -- -- -- -- -- --
* FN FN FN OD PD PU F O I
* 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
* -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
* IT IT IT DR DR DR FN FN FN OD PD PU F O I
*/
#define MODE_SHIFT 0
@@ -75,6 +78,15 @@
# define DRIVE_2 (3 << DRIVE_SHIFT)
# define DRIVE_3 (4 << DRIVE_SHIFT)
#define INTR_TYPE_SHIFT 12
#define INTR_TYPE_MASK (7 << INTR_TYPE_SHIFT)
# define DISABLED (0 << INTR_TYPE_SHIFT)
# define RISING (1 << INTR_TYPE_SHIFT)
# define FALLING (2 << INTR_TYPE_SHIFT)
# define CHANGE (3 << INTR_TYPE_SHIFT)
# define ONLOW (4 << INTR_TYPE_SHIFT)
# define ONHIGH (5 << INTR_TYPE_SHIFT)
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
@@ -93,33 +105,6 @@
# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6)
/* Interrupt type used with esp32s2_gpioirqenable() */
#define DISABLED 0x00
#define RISING 0x01
#define FALLING 0x02
#define CHANGE 0x03
#define ONLOW 0x04
#define ONHIGH 0x05
/* Check whether it is a valid GPIO number */
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \
(((1ULL << (gpio_num)) & \
SOC_GPIO_VALID_GPIO_MASK) != 0))
/* Check whether it can be a valid GPIO number of output mode */
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \
((gpio_num >= 0) && \
(((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0))
/* Check whether it can be a valid digital I/O pad */
#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \
((gpio_num >= 0) && \
(((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0))
/****************************************************************************
* Public Types
****************************************************************************/
@@ -149,28 +134,7 @@ extern "C"
****************************************************************************/
/****************************************************************************
* Name: esp32s2_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqinitialize(void);
#else
# define esp32s2_gpioirqinitialize()
#endif
/****************************************************************************
* Name: esp32s2_configgpio
* Name: esp_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
@@ -191,86 +155,10 @@ void esp32s2_gpioirqinitialize(void);
*
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr);
int esp_configgpio(int pin, gpio_pinattr_t attr);
/****************************************************************************
* Name: esp32s2_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin.
*
* Input Parameters:
* pin - GPIO pin to be written.
* value - Value to be written to the GPIO pin. True will output
* 1 (one) to the GPIO, while false will output 0 (zero).
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value);
/****************************************************************************
* Name: esp32s2_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin.
*
* Input Parameters:
* pin - GPIO pin to be read.
*
* Returned Value:
* True in case the read value is 1 (one). If 0 (zero), then false will be
* returned.
*
****************************************************************************/
bool esp32s2_gpioread(int pin);
/****************************************************************************
* Name: esp32s2_gpioirqenable
*
* Description:
* Enable the interrupt for the specified GPIO IRQ.
*
* Input Parameters:
* irq - Identifier of the interrupt request.
* intrtype - Interrupt type, select from gpio_intrtype_t.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype);
#else
# define esp32s2_gpioirqenable(irq,intrtype)
#endif
/****************************************************************************
* Name: esp32s2_gpioirqdisable
*
* Description:
* Disable the interrupt for the specified GPIO IRQ.
*
* Input Parameters:
* irq - Identifier of the interrupt request.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqdisable(int irq);
#else
# define esp32s2_gpioirqdisable(irq)
#endif
/****************************************************************************
* Name: esp32s2_gpio_matrix_in
* Name: esp_gpio_matrix_in
*
* Description:
* Set GPIO input to a signal.
@@ -291,10 +179,10 @@ void esp32s2_gpioirqdisable(int irq);
*
****************************************************************************/
void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
* Name: esp_gpio_matrix_out
*
* Description:
* Set signal output to GPIO.
@@ -313,8 +201,127 @@ void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv);
*
****************************************************************************/
void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
bool oen_inv);
void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
bool oen_inv);
/****************************************************************************
* Name: esp_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
* Input Parameters:
* pin - GPIO pin to be modified.
* value - The value to be written (0 or 1).
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_gpiowrite(int pin, bool value);
/****************************************************************************
* Name: esp_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
* Input Parameters:
* pin - GPIO pin to be read.
*
* Returned Value:
* The boolean representation of the input value (true/false).
*
****************************************************************************/
bool esp_gpioread(int pin);
/****************************************************************************
* Name: esp_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
void esp_gpioirqinitialize(void);
#else
# define esp_gpioirqinitialize()
#endif
/****************************************************************************
* Name: esp_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO
*
* Input Parameters:
* id - GPIO to be enabled.
*
* Returned Value:
* Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpioirqenable(int id);
#else
# define esp_gpioirqenable(id)
#endif
/****************************************************************************
* Name: esp_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO
*
* Input Parameters:
* id - GPIO to be disabled.
*
* Returned Value:
* Zero (OK) on success, or -1 (ERROR) in case of failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpioirqdisable(int id);
#else
# define esp_gpioirqdisable(id)
#endif
/****************************************************************************
* Name: esp_gpio_irq
*
* Description:
* Register or unregister a button interrupt handler for the specified
* button ID. Passing a non-NULL handler attaches and enables the ISR for
* the button; passing NULL disables the interrupt and removes any
* previously registered handler.
*
* Input Parameters:
* id - Identifies the button to be monitored.
* irqhandler - The handler to be called when the interrupt occurs.
* Set to NULL to disable the interrupt.
* arg - Pointer to the argument that will be provided to the
* interrupt handler.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_GPIO_IRQ
int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg);
#endif
#ifdef __cplusplus
}
@@ -322,4 +329,4 @@ void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv,
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H */
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h → arch/xtensa/src/common/espressif/esp_hr_timer.h
+8 -30
View File
@@ -1,5 +1,7 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
* arch/xtensa/src/common/espressif/esp_hr_timer.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,39 +20,15 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* This is a compatibility wrapper for the new ESP-HAL timer adapter */
#ifdef CONFIG_RTC_DRIVER
#include "esp_timer_adapter.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int esp32s3_rtc_driverinit(void);
#endif /* CONFIG_RTC_DRIVER */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H */
arch/xtensa/src/common/espressif/esp_i2c_bitbang.c
+19 -19
View File
@@ -33,16 +33,16 @@
#include <nuttx/kmalloc.h>
#include "espressif/esp_i2c_bitbang.h"
#include "espressif/esp_gpio.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "esp32s2_gpio_sigmap.h"
# include "esp32s2_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp32s3_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp32_gpio_sigmap.h"
# error "Unsupported chip"
#endif
/****************************************************************************
@@ -50,23 +50,23 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s2_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#else
#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
#define GPIO_READ(pin) esp3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#endif
/****************************************************************************
arch/xtensa/src/common/espressif/esp_i2c_slave.c
+11 -62
View File
@@ -54,16 +54,16 @@
#include "esp_i2c_slave.h"
#include "xtensa.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp32s3_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "esp32s2_irq.h"
#include "espressif/esp_gpio.h"
#include "espressif/esp_irq.h"
#include "esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -73,7 +73,7 @@
#include "hal/i2c_ll.h"
#include "soc/system_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/i2c_periph.h"
#include "hal/i2c_periph.h"
/****************************************************************************
* Pre-processor Definitions
@@ -85,48 +85,21 @@
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S3_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S3_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S3_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define esp_setup_irq esp32s3_setup_irq
#define esp_teardown_irq esp32s3_teardown_irq
#define esp_gpiowrite(pin, value) esp32s3_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32s3_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv) esp32s3_gpio_matrix_in(pin, \
idx, inv)
#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32S2_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32S2_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S2_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S2_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32S2_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_gpiowrite(pin, value) esp32s2_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32s2_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv, en_inv) esp32s2_gpio_matrix_in(pin, \
idx, inv, en_inv)
#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
idx, inv, en_inv)
#else
#define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32_I2C0_SCLPIN
#define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32_I2C0_SDAPIN
#define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32_I2C1_SCLPIN
#define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32_I2C1_SDAPIN
#define ESP_IRQ_I2C_EXT0 ESP32_IRQ_I2C_EXT0
#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#define ESP_IRQ_PRIORITY_DEFAULT 1
#define esp_setup_irq esp32_setup_irq
#define esp_teardown_irq esp32_teardown_irq
#define esp_gpiowrite(pin, value) esp32_gpiowrite(pin, value)
#define esp_configgpio(pin, attr) esp32_configgpio(pin, attr)
#define esp_gpio_matrix_in(pin, idx, inv) esp32_gpio_matrix_in(pin, \
idx, inv)
#define esp_gpio_matrix_out(pin, idx, inv) esp32_gpio_matrix_out(pin, \
idx, inv)
#endif
#define I2C_FIFO_FULL_THRESH_VAL 28
@@ -935,20 +908,13 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
/* Disable the previous IRQ */
up_disable_irq(config->irq);
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph, priv->cpuint);
esp_teardown_irq(config->periph, priv->cpuint);
}
priv->cpuint = esp_setup_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph,
priv->cpuint = esp_setup_irq(config->periph,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL);
ESP_IRQ_TRIGGER_LEVEL,
esp_i2c_slave_irq, priv);
if (priv->cpuint < 0)
{
/* Failed to allocate a CPU interrupt of this type. */
@@ -959,23 +925,6 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr)
return NULL;
}
ret = irq_attach(config->irq, esp_i2c_slave_irq, priv);
if (ret != OK)
{
/* Failed to attach IRQ, free the allocated CPU interrupt */
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
this_cpu(),
#endif
config->periph, priv->cpuint);
priv->cpuint = -ENOMEM;
priv->refs--;
nxmutex_unlock(&priv->lock);
return NULL;
}
/* Enable the CPU interrupt that is linked to the I2C device. */
up_enable_irq(config->irq);
arch/xtensa/src/common/espressif/esp_i2s.c
+29 -89
View File
@@ -39,34 +39,32 @@
#include <arch/irq.h>
#include "xtensa.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#include "esp_i2s.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#include "esp32s3_dma.h"
#include "hardware/esp32s3_dma.h"
#include "esp32s3_irq.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp32_dma.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#include "esp32s2_dma.h"
#include "esp32s2_irq.h"
#else
#include "esp32_gpio.h"
#include "esp32_dma.h"
#include "esp32_irq.h"
# include "espressif/esp_gpio.h"
# include "hardware/esp32s2_gpio_sigmap.h"
# include "esp32s2_dma.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "hardware/esp32s3_gpio_sigmap.h"
# include "esp32s3_dma.h"
# include "hardware/esp32s3_dma.h"
#endif
#include "hal/i2s_hal.h"
#include "hal/i2s_ll.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "hal/i2s_types.h"
#include "soc/gpio_sig_map.h"
#include "periph_ctrl.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "soc/gdma_reg.h"
# include "soc/gdma_periph.h"
# include "hal/gdma_periph.h"
# include "hal/gdma_ll.h"
#endif
@@ -82,49 +80,27 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_setup_irq esp32s3_setup_irq
#define esp_teardown_irq esp32s3_teardown_irq
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#define esp_gpiowrite esp32s3_gpiowrite
#define esp_dma_init esp32s3_dma_init
#define esp_dma_request esp32s3_dma_request
#define esp_dma_setup esp32s3_dma_setup
#define esp_dma_load esp32s3_dma_load
#define esp_dma_enable esp32s3_dma_enable
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32S3_DMA_BUFLEN_MAX
#define ESPRESSIF_DMA_PERIPH_I2S ESP32S3_DMA_PERIPH_I2S1
#define ESP_SOURCE2IRQ ESP32S3_PERIPH2IRQ
#define esp_dmadesc_s esp32s3_dmadesc_s
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#define esp_gpiowrite esp32s2_gpiowrite
#define esp_dma_setup esp32s2_dma_init
#define ESP_SOURCE2IRQ ESP32S2_PERIPH2IRQ
#define esp_dmadesc_s esp32s2_dmadesc_s
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32S2_DMA_DATALEN_MAX
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX
#define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX
#define I2S0_MCLK_OUT_IDX CLK_I2S_MUX_IDX
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#define esp_setup_irq esp32_setup_irq
#define esp_teardown_irq esp32_teardown_irq
#define esp_configgpio esp32_configgpio
#define esp_gpio_matrix_in esp32_gpio_matrix_in
#define esp_gpio_matrix_out esp32_gpio_matrix_out
#define esp_gpiowrite esp32_gpiowrite
#define esp_dma_setup esp32_dma_init
#define esp_dmadesc_s esp32_dmadesc_s
#define ESP_SOURCE2IRQ ESP32_PERIPH2IRQ
#define ESPRESSIF_DMA_BUFLEN_MAX ESP32_DMA_DATALEN_MAX
#define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX
#define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX
@@ -133,7 +109,6 @@
#define I2S1I_SD_IN_IDX I2S1I_DATA_IN15_IDX
#define I2S1_MCLK_OUT_IDX -1
#define ESP_IRQ_PRIORITY_DEFAULT 1
#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#endif
#if defined(CONFIG_ESPRESSIF_I2S0_DATA_BIT_WIDTH_8BIT) || \
@@ -343,7 +318,6 @@ typedef enum
struct esp_i2s_config_s
{
uint32_t port; /* I2S port */
periph_module_t module; /* I2S peripheral module */
uint32_t role; /* I2S port role (master or slave) */
uint8_t data_width; /* I2S sample data width */
uint32_t rate; /* I2S sample-rate */
@@ -588,7 +562,6 @@ i2s_hal_clock_info_t clk_info_i2s0 =
static const struct esp_i2s_config_s esp_i2s0_config =
{
.port = 0,
.module = PERIPH_I2S0_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S0_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -662,7 +635,6 @@ i2s_hal_clock_info_t clk_info_i2s1 =
static const struct esp_i2s_config_s esp_i2s1_config =
{
.port = 1,
.module = PERIPH_I2S1_MODULE,
#ifdef CONFIG_ESPRESSIF_I2S1_ROLE_MASTER
.role = I2S_ROLE_MASTER,
#else
@@ -1584,8 +1556,6 @@ static void i2s_configure(struct esp_i2s_s *priv)
/* Set peripheral clock and clear reset */
periph_module_enable(priv->config->module);
i2s_hal_init(priv->config->ctx, priv->config->port);
I2S_RCC_ATOMIC()
{
@@ -3094,9 +3064,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
{
periph =
gdma_periph_signals.groups[0].pairs[priv->dma_channel].tx_irq_id;
int cpuint = esp_setup_irq(priv->cpu,
periph, 1,
ESP_IRQ_TRIGGER_LEVEL);
ASSERT(this_cpu() == priv->cpu);
int cpuint = esp_setup_irq(periph, 1,
ESP_IRQ_TRIGGER_LEVEL,
i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
@@ -3104,15 +3076,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
}
priv->tx_irq = ESP_SOURCE2IRQ(periph);
ret = irq_attach(priv->tx_irq, i2s_interrupt, priv);
if (ret != OK)
{
i2serr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(priv->cpu,
periph,
cpuint);
return ret;
}
}
# endif /* I2S_HAVE_TX */
@@ -3121,9 +3084,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
{
periph =
gdma_periph_signals.groups[0].pairs[priv->dma_channel].rx_irq_id;
int cpuint = esp_setup_irq(priv->cpu,
periph, 1,
ESP_IRQ_TRIGGER_LEVEL);
ASSERT(this_cpu() == priv->cpu);
int cpuint = esp_setup_irq(periph, 1,
ESP_IRQ_TRIGGER_LEVEL,
i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
@@ -3131,15 +3096,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
}
priv->rx_irq = ESP_SOURCE2IRQ(periph);
ret = irq_attach(priv->rx_irq, i2s_interrupt, priv);
if (ret != OK)
{
i2serr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(priv->cpu,
periph,
cpuint);
return ret;
}
}
# endif /* I2S_HAVE_RX */
#else
@@ -3153,31 +3109,15 @@ static int i2s_dma_setup(struct esp_i2s_s *priv)
priv->cpu = this_cpu();
periph = i2s_periph_signal[priv->config->port].irq;
int cpuint = esp_setup_irq(
# ifndef CONFIG_ARCH_CHIP_ESP32S2
priv->cpu,
# endif
periph, 1,
ESP_IRQ_TRIGGER_LEVEL);
int cpuint = esp_setup_irq(periph,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL,
i2s_interrupt, priv);
if (cpuint < 0)
{
i2serr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
int irq = ESP_SOURCE2IRQ(periph);
ret = irq_attach(irq, i2s_interrupt, priv);
if (ret != OK)
{
i2serr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
priv->cpu,
#endif
periph,
cpuint);
return ret;
}
#endif
return OK;
arch/xtensa/src/common/espressif/esp_irq.c
+955
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_irq.h
+296
View File
@@ -0,0 +1,296 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_irq.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "esp_intr_types.h"
#include "esp_intr_alloc.h"
#include "soc/interrupts.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IRQ_UNMAPPED (intr_handle_t)NULL
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* CPU interrupt flags.
* esp_setup_irq() will check bit 1 for IRAM requirement and
* bit 0 for trigger type.
*
* OR'ed values of irq_trigger_e and irq_iram_e define interrupt type.
* | IRAM | TRIGGER |
* Bits | 1 | 0 |
*/
/* CPU interrupt trigger types */
typedef enum irq_trigger_e
{
ESP_IRQ_TRIGGER_LEVEL = 0, /* Level-triggered interrupts */
ESP_IRQ_TRIGGER_EDGE = 1, /* Edge-triggered interrupts */
} irq_trigger_t;
/* CPU interrupt IRAM enabled */
typedef enum irq_iram_e
{
ESP_IRQ_NON_IRAM = (0 << 1), /* Non-IRAM interrupt */
ESP_IRQ_IRAM = (1 << 1), /* IRAM interrupt */
} irq_iram_t;
/* CPU interrupt priority levels */
typedef enum irq_priority_e
{
ESP_IRQ_PRIORITY_1 = 1, /* Priority Level 1 */
ESP_IRQ_PRIORITY_2 = 2, /* Priority Level 2 */
ESP_IRQ_PRIORITY_3 = 3, /* Priority Level 3 */
ESP_IRQ_PRIORITY_4 = 4, /* Priority Level 4 */
ESP_IRQ_PRIORITY_5 = 5, /* Priority Level 5 */
ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */
} irq_priority_t;
/* Adapter from NuttX to Espressif's interrupt handler */
struct intr_adapter_from_nuttx
{
int (*func)(int irq, void *context, void *arg); /* Interrupt callback function */
int irq; /* Interrupt number */
void *context; /* Interrupt context */
void *arg; /* Interrupt private data */
};
struct intr_adapter_to_nuttx
{
void (*handler)(void *arg); /* Interrupt handler */
void *arg; /* Interrupt handler argument */
};
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_setup_irq
*
* Description:
* This function sets up the IRQ. It allocates a CPU interrupt of the given
* priority and type and attaches it to a given interrupt source.
*
* Input Parameters:
* source - The interrupt source from irq.h to be assigned to
* a CPU interrupt.
* priority - Interrupt priority.
* type - Interrupt trigger type.
* handler - Interrupt handler.
* arg - Interrupt handler argument.
*
* Returned Value:
* Allocated CPU interrupt on success, or a negated errno on failure.
*
****************************************************************************/
int esp_setup_irq(int source,
irq_priority_t priority,
int type,
xcpt_t handler,
void *arg);
int esp_setup_irq_with_flags(int source,
int flags,
xcpt_t handler,
void *arg);
int esp_setup_irq_intrstatus(int source,
irq_priority_t priority,
int type,
uint32_t intrstatusreg,
uint32_t intrstatusmask,
xcpt_t handler,
void *arg);
int esp_setup_irq_with_flags_intrstatus(int source,
int flags,
uint32_t intrstatusreg,
uint32_t intrstatusmask,
xcpt_t handler,
void *arg);
/****************************************************************************
* Name: esp_teardown_irq
*
* Description:
* This function undoes the operations done by esp_setup_irq.
* It detaches an interrupt source from a CPU interrupt and frees the
* CPU interrupt.
*
* Input Parameters:
* source - The interrupt source from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the interrupt source will
* be detached.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_teardown_irq(int source, int cpuint);
/****************************************************************************
* Name: esp_get_cpuint
*
* Description:
* This function returns the CPU interrupt associated with an IRQ
*
* Input Parameters:
* cpu - The CPU associated with the IRQ
* irq - The IRQ associated with a CPU interrupt
*
* Returned Value:
* The CPU interrupt associated with such IRQ or a negated errno value on
* failure.
*
****************************************************************************/
int esp_get_cpuint(int cpu, int irq);
/****************************************************************************
* Name: esp_set_handle
*
* Description:
* This function sets the handle associated with an IRQ
*
* Input Parameters:
* cpu - The CPU associated with the IRQ
* irq - The IRQ associated with a CPU interrupt
* handle - The handle to be associated with the IRQ
*
* Returned Value:
* OK on success; A negated errno value on failure.
*
****************************************************************************/
int esp_set_handle(int cpu, int irq, intr_handle_t handle);
/****************************************************************************
* Name: esp_get_handle
*
* Description:
* This function gets the handle associated with an IRQ
*
* Input Parameters:
* cpu - The CPU associated with the IRQ
* irq - The IRQ associated with a CPU interrupt
*
* Returned Value:
* The handle associated with the IRQ or IRQ_UNMAPPED if no handle is
* associated with the IRQ.
*
****************************************************************************/
intr_handle_t esp_get_handle(int cpu, int irq);
/****************************************************************************
* Name: esp_cpuint_initialize
*
* Description:
* Initialize CPU interrupts.
*
* Input Parameters:
* None.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
void esp_cpuint_initialize(void);
/****************************************************************************
* Name: esp_get_iram_interrupt_records
*
* Description:
* This function copies the vector that keeps track of the IRQs that ran
* when non-IRAM interrupts were disabled.
*
* Input Parameters:
*
* irq_count - A previously allocated pointer to store the counter of the
* interrupts that ran when non-IRAM interrupts were disabled.
* cpu - The CPU to retrieve the interrupt records for
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG
void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu);
#endif
/****************************************************************************
* Name: esp_dump_cpuint_map
*
* Description:
* Dump the contents of g_handle_map for debugging purposes.
* This function is useful when debugging unexpected interrupt handlers.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_dump_cpuint_map(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H */
arch/xtensa/src/common/espressif/esp_ledc.c
+20 -16
View File
@@ -37,15 +37,15 @@
#include "esp_ledc.h"
#include "xtensa.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp_gpio.h"
# include "hardware/esp32_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "hardware/esp32_gpio_sigmap.h"
# include "espressif/esp_gpio.h"
# include "hardware/esp32s2_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp_gpio.h"
# include "hardware/esp32s3_gpio_sigmap.h"
#endif
#include "esp_private/periph_ctrl.h"
@@ -61,8 +61,6 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
# define esp_configgpio esp32s3_configgpio
# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
# ifdef CONFIG_ESP32S3_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S3_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S3_LEDC_CHANNEL1_PIN
@@ -94,8 +92,6 @@
# endif /* CONFIG_ESP32S3_LEDC_TIM3 */
# endif /* CONFIG_ESP32S3_LEDC */
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# define esp_configgpio esp32s2_configgpio
# define esp_gpio_matrix_out esp32s2_gpio_matrix_out
# ifdef CONFIG_ESP32S2_LEDC
# define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S2_LEDC_CHANNEL0_PIN
# define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S2_LEDC_CHANNEL1_PIN
@@ -540,7 +536,6 @@ static bool ledc_ctx_create(void)
ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), LEDC_LOW_SPEED_MODE);
ledc_new_mode_obj->glb_clk = LEDC_SLOW_CLK_UNINIT;
p_ledc_obj = ledc_new_mode_obj;
periph_module_enable(PERIPH_LEDC_MODULE);
}
}
@@ -1235,7 +1230,7 @@ static int ledc_channel_output_enable(ledc_channel_t channel)
}
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, true);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, true);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
return OK;
}
@@ -1270,7 +1265,7 @@ static int ledc_channel_output_disable(ledc_channel_t channel)
ledc_hal_set_idle_level(&(p_ledc_obj->ledc_hal), channel, 0);
ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, false);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, false);
ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel);
leave_critical_section(flags);
return OK;
@@ -1532,10 +1527,19 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
if (p_ledc_obj != NULL)
{
periph_module_disable(PERIPH_LEDC_MODULE);
kmm_free(p_ledc_obj);
p_ledc_obj = NULL;
s_ledc_slow_clk_rc_fast_freq = 0;
LEDC_BUS_CLOCK_ATOMIC()
{
ledc_ll_enable_bus_clock(false);
ledc_ll_enable_reset_reg(true);
}
LEDC_FUNC_CLOCK_ATOMIC()
{
ledc_ll_enable_clock(LEDC_LL_GET_HW(), false);
}
}
else
{
arch/xtensa/src/common/espressif/esp_loader.c
+1 -1
View File
@@ -47,7 +47,7 @@
# include "bootloader_flash_priv.h"
#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
# include "bootloader_init.h"
# include "esp_rom_uart.h"
# include "esp_rom_serial_output.h"
# include "esp_rom_sys.h"
# include "esp_app_format.h"
#endif
arch/xtensa/src/common/espressif/esp_mcpwm.c
+72 -49
View File
@@ -46,21 +46,22 @@
#include "xtensa.h"
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "hardware/esp32_soc.h"
#include "esp32_gpio.h"
#include "esp32_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#elif CONFIG_ARCH_CHIP_ESP32S3
#include "hardware/esp32s3_soc.h"
#include "esp32s3_gpio.h"
#include "esp32s3_irq.h"
#include "esp_gpio.h"
#include "esp_irq.h"
#endif
#include "hal/mcpwm_hal.h"
#include "hal/mcpwm_ll.h"
#include "hal/mcpwm_types.h"
#include "soc/mcpwm_periph.h"
#include "hal/mcpwm_periph.h"
#include "periph_ctrl.h"
#include "esp_clk_tree.h"
#include "hal/clk_tree_hal.h"
#include "esp_private/esp_clk_tree_common.h"
#include "soc/clk_tree_defs.h"
#ifdef CONFIG_ESP_MCPWM
@@ -68,22 +69,10 @@
* Pre-processor Definitions
****************************************************************************/
#define MCPWM_DEV_CLK_PRESCALE 1
#define MCPWM_CAPTURE_DEFAULT_GROUP 0
#ifdef CONFIG_ARCH_CHIP_ESP32
# define esp_configgpio esp32_configgpio
# define esp_gpio_matrix_in esp32_gpio_matrix_in
# define esp_gpio_matrix_out esp32_gpio_matrix_out
# define esp_setup_irq esp32_setup_irq
# define esp_teardown_irq esp32_teardown_irq
# define ESP_CPUINT_LEVEL ESP32_CPUINT_LEVEL
#elif CONFIG_ARCH_CHIP_ESP32S3
# define esp_configgpio esp32s3_configgpio
# define esp_gpio_matrix_in esp32s3_gpio_matrix_in
# define esp_gpio_matrix_out esp32s3_gpio_matrix_out
# define esp_setup_irq esp32s3_setup_irq
# define esp_teardown_irq esp32s3_teardown_irq
# define ESP_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL
#endif
#ifdef CONFIG_ESP_MCPWM_MOTOR_BDC
/* Peak counter at 13330 in up-down mode allows frequencies at a prescale
* of: 2 kHz @ 2; 1.5 kHz @ 3; 1.2 kHz @ 4; 1 kHz @ 5.
@@ -154,6 +143,7 @@ struct mcpwm_dev_common_s
spinlock_t mcpwm_spinlock;
bool initialized; /* MCPWM periph. and HAL has been initialized */
bool isr_initialized; /* Shared ISR has been initialized */
int group_prescale;
};
#ifdef CONFIG_ESP_MCPWM_MOTOR
@@ -233,7 +223,7 @@ static void esp_mcpwm_group_start(void);
static int esp_mcpwm_capture_set_gpio(
struct mcpwm_cap_channel_lowerhalf_s *lower);
/* Upper-half functions required by capture driver */
/* Lower half methods required by capture driver */
static int esp_capture_start(struct cap_lowerhalf_s *lower);
static int esp_capture_stop(struct cap_lowerhalf_s *lower);
@@ -309,6 +299,7 @@ static struct mcpwm_dev_common_s g_mcpwm_common =
.group.group_id = 0,
.initialized = false,
.isr_initialized = false,
.group_prescale = MCPWM_DEV_CLK_PRESCALE,
};
/* Motor specific data structures */
@@ -419,8 +410,31 @@ static struct mcpwm_cap_channel_lowerhalf_s mcpwm_cap_ch2_lowerhalf =
static void esp_mcpwm_group_start(void)
{
periph_module_enable(PERIPH_PWM0_MODULE);
mcpwm_hal_init(&g_mcpwm_common.hal, &g_mcpwm_common.group);
mcpwm_hal_context_t *hal = &g_mcpwm_common.hal;
/* HAL and MCPWM Initialization */
PERIPH_RCC_ATOMIC()
{
mcpwm_ll_enable_bus_clock(g_mcpwm_common.group.group_id, true);
mcpwm_ll_reset_register(g_mcpwm_common.group.group_id);
mcpwm_ll_group_enable_clock(g_mcpwm_common.group.group_id, true);
}
mcpwm_hal_init(hal, &g_mcpwm_common.group);
esp_clk_tree_enable_src(
(soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true);
PERIPH_RCC_ATOMIC()
{
mcpwm_ll_group_set_clock_source(g_mcpwm_common.group.group_id,
MCPWM_CAPTURE_CLK_SRC_DEFAULT);
mcpwm_ll_group_set_clock_prescale(g_mcpwm_common.group.group_id,
g_mcpwm_common.group_prescale);
}
g_mcpwm_common.initialized = true;
}
@@ -465,7 +479,7 @@ static int esp_motor_setup(struct motor_lowerhalf_s *dev)
mtrinfo("State: %d\n", priv->state.state);
esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_F160M,
esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&base_clock);
@@ -1320,7 +1334,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower,
if (!enable)
{
esp_gpio_matrix_in(0x3a,
mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
gpio_faults[lower->fault_id].fault_sig,
false);
return OK;
@@ -1335,7 +1349,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower,
esp_gpio_matrix_in(
lower->fault_pin,
mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
gpio_faults[lower->fault_id].fault_sig,
false);
@@ -1397,13 +1411,13 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower,
esp_gpio_matrix_out(
lower->generator_pins[MCPWM_GENERATOR_0],
mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].generators[MCPWM_GENERATOR_0].pwm_sig,
false, false);
esp_gpio_matrix_out(
lower->generator_pins[MCPWM_GENERATOR_1],
mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].generators[MCPWM_GENERATOR_1].pwm_sig,
false, false);
@@ -1411,14 +1425,12 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower,
#ifdef CONFIG_ESP_MCPWM_TEST_LOOPBACK
esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH0_GPIO,
mcpwm_periph_signals.\
groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].\
generators[MCPWM_GENERATOR_0].pwm_sig,
0, 0);
esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH1_GPIO,
mcpwm_periph_signals.\
groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
operators[lower->channel_id].\
generators[MCPWM_GENERATOR_1].pwm_sig,
0, 0);
@@ -1554,6 +1566,9 @@ static int esp_capture_getduty(struct cap_lowerhalf_s *lower,
{
struct mcpwm_cap_channel_lowerhalf_s *priv = (
struct mcpwm_cap_channel_lowerhalf_s *)lower;
DEBUGASSERT(priv != NULL);
*duty = priv->duty;
cpinfo("Get duty called from channel %d\n", priv->channel_id);
return OK;
@@ -1582,6 +1597,9 @@ static int esp_capture_getfreq(struct cap_lowerhalf_s *lower,
{
struct mcpwm_cap_channel_lowerhalf_s *priv = (
struct mcpwm_cap_channel_lowerhalf_s *)lower;
DEBUGASSERT(priv != NULL);
*freq = priv->freq;
cpinfo("Get freq called from channel %d\n", priv->channel_id);
return OK;
@@ -1641,7 +1659,7 @@ static int esp_mcpwm_capture_set_gpio(
mcpwm_hal_context_t *hal = &lower->common->hal;
int ret;
ret = esp_configgpio(lower->gpio_pin, INPUT_FUNCTION | INPUT_PULLUP);
ret = esp_configgpio(lower->gpio_pin, INPUT | PULLUP);
if (ret < 0)
{
cperr("Failed configuring GPIO pin\n");
@@ -1650,7 +1668,7 @@ static int esp_mcpwm_capture_set_gpio(
esp_gpio_matrix_in(
lower->gpio_pin,
mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
captures[lower->channel_id].cap_sig,
false);
@@ -1681,26 +1699,22 @@ static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), void *arg)
{
int cpuint;
int ret;
int cpu = this_cpu();
DEBUGASSERT(fn);
cpuint = esp_setup_irq(cpu, mcpwm_periph_signals.groups[0].irq_id,
1, ESP_CPUINT_LEVEL);
cpuint = esp_setup_irq(soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\
irq_id,
1, ESP_IRQ_TRIGGER_LEVEL,
fn,
arg);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return -ENOMEM;
}
ret = irq_attach(mcpwm_periph_signals.groups[0].irq_id +
XTENSA_IRQ_FIRSTPERIPH, fn, arg);
if (ret < 0)
{
cperr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(cpu, mcpwm_periph_signals.groups[0].irq_id, cpuint);
return ret;
}
up_enable_irq(ESP_SOURCE2IRQ(
soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].irq_id));
return ret;
}
@@ -1989,6 +2003,7 @@ struct motor_lowerhalf_s *esp_motor_bdc_initialize(int channel,
struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
{
struct mcpwm_cap_channel_lowerhalf_s *lower = NULL;
uint32_t group_clock;
if (!g_mcpwm_common.initialized)
{
@@ -1997,8 +2012,7 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
if (!g_mcpwm_common.isr_initialized)
{
esp_mcpwm_isr_register(mcpwm_driver_isr_default,
&g_mcpwm_common);
esp_mcpwm_isr_register(mcpwm_driver_isr_default, &g_mcpwm_common);
g_mcpwm_common.isr_initialized = true;
}
@@ -2024,8 +2038,17 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin)
return NULL;
}
lower->clock = clk_hal_apb_get_freq_hz();
esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
&group_clock);
/* Set the clock to be used when calculating frequency */
lower->gpio_pin = pin;
lower->clock = group_clock / g_mcpwm_common.group_prescale;
/* Configure GPIO pin */
esp_mcpwm_capture_set_gpio(lower);
return (struct cap_lowerhalf_s *) lower;
arch/xtensa/src/common/espressif/esp_openeth.c
+3 -6
View File
@@ -514,8 +514,9 @@ int esp_openeth_initialize(void)
/* Setup interrupts */
priv->cpuint = OPENETH_SETUP_IRQ(0, OPENETH_PERIPH_MAC,
1, OPENETH_CPUINT_LEVEL);
priv->cpuint = OPENETH_SETUP_IRQ(OPENETH_PERIPH_MAC,
1, OPENETH_CPUINT_LEVEL,
openeth_isr_handler, priv);
if (priv->cpuint < 0)
{
nerr("ERROR: Failed allocate interrupt\n");
@@ -531,10 +532,6 @@ int esp_openeth_initialize(void)
"\x00\x02\x03\x04\x05\x06\x07\x08", ETH_ALEN);
openeth_set_addr(priv->dev.netdev.d_mac.ether.ether_addr_octet);
/* Attach the interrupt */
ret = irq_attach(OPENETH_IRQ_MAC, openeth_isr_handler, priv);
/* Register the device with the OS so that socket IOCTLs can be
* performed.
*/
arch/xtensa/src/common/espressif/esp_pcnt.c
+55 -74
View File
@@ -47,20 +47,20 @@
#include "esp_pcnt.h"
#include "chip.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_irq.h"
#include "esp32s3_gpio.h"
#include "esp_irq.h"
#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_irq.h"
#include "esp32s2_gpio.h"
#include "espressif/esp_irq.h"
#include "espressif/esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#include "esp32_irq.h"
#include "esp32_gpio.h"
#include "esp_irq.h"
#include "esp_gpio.h"
#endif
#include "hal/pcnt_hal.h"
#include "hal/pcnt_ll.h"
#include "periph_ctrl.h"
#include "soc/pcnt_periph.h"
#include "hal/pcnt_periph.h"
#include "soc/pcnt_reg.h"
#include "soc/pcnt_struct.h"
#include "soc/gpio_pins.h"
@@ -70,32 +70,23 @@
* Pre-processor Definitions
****************************************************************************/
#define PCNT_UNIT_COUNT SOC_PCNT_GROUPS * SOC_PCNT_UNITS_PER_GROUP
#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id/SOC_PCNT_CHANNELS_PER_UNIT)
#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (SOC_PCNT_CHANNELS_PER_UNIT * unit_id))
#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((SOC_PCNT_CHANNELS_PER_UNIT * unit_id) + chan_id)
#define PCNT_UNIT_COUNT PCNT_LL_GET(INST_NUM) * PCNT_LL_GET(UNITS_PER_INST)
#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id / PCNT_LL_GET(CHANS_PER_UNIT))
#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (PCNT_LL_GET(CHANS_PER_UNIT) * unit_id))
#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((PCNT_LL_GET(CHANS_PER_UNIT) * unit_id) + chan_id)
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_setup_irq esp32s3_setup_irq
#define esp_teardown_irq esp32s3_teardown_irq
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_setup_irq esp32s2_setup_irq
#define esp_teardown_irq esp32s2_teardown_irq
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF
#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#define esp_setup_irq esp32_setup_irq
#define esp_teardown_irq esp32_teardown_irq
#define esp_configgpio esp32_configgpio
#define esp_gpio_matrix_in esp32_gpio_matrix_in
#define ESP_IRQ_PRIORITY_DEFAULT 1
#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL
#endif
#if !SOC_RCC_IS_INDEPENDENT
# define PCNT_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
#else
# define PCNT_RCC_ATOMIC()
#endif
/****************************************************************************
@@ -136,7 +127,7 @@ struct esp_pcnt_priv_s
spinlock_t lock; /* Device specific lock. */
int (*cb)(int, void *, void *); /* User defined callback */
uint32_t accum_value; /* Accumulator value of overflowed PCNT unit */
bool channels[SOC_PCNT_CHANNELS_PER_UNIT]; /* Channel information of PCNT unit */
bool channels[PCNT_LL_GET(CHANS_PER_UNIT)]; /* Channel information of PCNT unit */
struct esp_pcnt_watch_point_priv_s watchers[PCNT_LL_WATCH_EVENT_MAX]; /* array of PCNT watchers */
};
@@ -148,8 +139,7 @@ static int esp_pcnt_open(struct cap_lowerhalf_s *dev);
static int esp_pcnt_close(struct cap_lowerhalf_s *dev);
static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
void *arg);
static int esp_pcnt_isr_register(int (*fn)(int, void *, void *),
int intr_alloc_flags);
static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg);
static int esp_pcnt_ioctl(struct cap_lowerhalf_s *dev, int cmd,
unsigned long arg);
static int esp_pcnt_unit_enable(struct cap_lowerhalf_s *dev);
@@ -405,13 +395,13 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
struct esp_pcnt_watch_event_data_s data;
irqstate_t flags;
for (unit_id = 0; unit_id < SOC_PCNT_UNITS_PER_GROUP; unit_id++)
for (unit_id = 0; unit_id < PCNT_LL_GET(UNITS_PER_INST); unit_id++)
{
if (intr_status & PCNT_LL_UNIT_WATCH_EVENT(unit_id))
break;
}
if (unit_id < SOC_PCNT_UNITS_PER_GROUP)
if (unit_id < PCNT_LL_GET(UNITS_PER_INST))
{
unit = &pcnt_units[unit_id];
pcnt_ll_clear_intr_status(ctx.dev, PCNT_LL_UNIT_WATCH_EVENT(unit_id));
@@ -461,7 +451,7 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
*
* Input Parameters:
* fn - Pointer to the ISR function.
* intr_alloc_flags - Flags for the interrupt allocation.
* arg - Pointer to the argument to be passed to the ISR.
*
* Returned Value:
* Returns OK on successful registration of the ISR; a negated errno value
@@ -469,44 +459,29 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context,
*
****************************************************************************/
static int esp_pcnt_isr_register(int (*fn)(int, void *, void *),
int intr_alloc_flags)
static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg)
{
struct intr_adapter_from_nuttx *adapter;
int cpuint;
#ifndef CONFIG_ARCH_CHIP_ESP32S2
int ret;
int cpu = this_cpu();
#endif
DEBUGASSERT(fn);
cpuint = esp_setup_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
cpu,
#endif
pcnt_periph_signals.groups[0].irq,
cpuint = esp_setup_irq(soc_pcnt_signals[0].irq_id,
ESP_IRQ_PRIORITY_DEFAULT,
ESP_IRQ_TRIGGER_LEVEL);
ESP_IRQ_TRIGGER_LEVEL,
fn,
arg);
if (cpuint < 0)
{
cperr("Failed to allocate a CPU interrupt.\n");
return ERROR;
}
ret = irq_attach((pcnt_periph_signals.groups[0].irq +
XTENSA_IRQ_FIRSTPERIPH),
fn,
0);
if (ret < 0)
{
cperr("Couldn't attach IRQ to handler.\n");
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
cpu,
#endif
pcnt_periph_signals.groups[0].irq, cpuint);
return ERROR;
}
up_enable_irq(pcnt_periph_signals.groups[0].irq + XTENSA_IRQ_FIRSTPERIPH);
up_enable_irq(soc_pcnt_signals[0].irq_id + XTENSA_IRQ_FIRSTPERIPH);
return OK;
}
@@ -878,8 +853,12 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit(
if (g_pcnt_refs++ == 0)
{
periph_module_enable(PERIPH_PCNT_MODULE);
periph_module_reset(PERIPH_PCNT_MODULE);
PCNT_RCC_ATOMIC()
{
pcnt_ll_enable_bus_clock(0, true);
pcnt_ll_reset_register(0);
}
pcnt_hal_init(&ctx, 0);
}
@@ -985,7 +964,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev)
return ERROR;
}
for (i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++)
for (i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++)
{
if (!priv->channels[i])
{
@@ -1009,12 +988,12 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev)
g_pcnt_refs--;
if (g_pcnt_refs == 0)
{
periph_module_disable(PERIPH_PCNT_MODULE);
esp_teardown_irq(
#ifndef CONFIG_ARCH_CHIP_ESP32S2
cpu,
#endif
pcnt_periph_signals.groups[0].irq, -ENOMEM);
PCNT_RCC_ATOMIC()
{
pcnt_ll_enable_bus_clock(0, false);
}
esp_teardown_irq(soc_pcnt_signals[0].irq_id, -ENOMEM);
}
spin_unlock_irqrestore(&priv->lock, flags);
@@ -1124,7 +1103,7 @@ int esp_pcnt_unit_add_watch_point(struct cap_lowerhalf_s *dev,
else
{
int thres_num = SOC_PCNT_THRES_POINT_PER_UNIT - 1;
int thres_num = PCNT_LL_GET(THRES_POINT_PER_UNIT) - 1;
switch (thres_num)
{
case 1:
@@ -1279,7 +1258,6 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
int gpio_mode;
int virt_gpio;
int ret_id = 0;
const pcnt_signal_conn_t *chan;
if (!config)
{
@@ -1299,7 +1277,7 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
return ERROR;
}
for (int i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++)
for (int i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++)
{
if (!priv->channels[i])
{
@@ -1318,13 +1296,13 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
(config->flags && ESP_PCNT_CHAN_IO_LOOPBACK ? OUTPUT_FUNCTION : 0);
virt_gpio = (config->flags && ESP_PCNT_CHAN_VIRT_LVL_IO_LVL) ?
GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT;
chan = &pcnt_periph_signals;
if (config->edge_gpio_num >= 0)
{
esp_configgpio(config->edge_gpio_num, gpio_mode);
esp_gpio_matrix_in(config->edge_gpio_num,
chan->groups[0].units[unit_id].channels[channel_id].pulse_sig,
soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
pulse_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN));
}
else
@@ -1332,7 +1310,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
/* using virtual IO */
esp_gpio_matrix_in(virt_gpio,
chan->groups[0].units[unit_id].channels[channel_id].pulse_sig,
soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
pulse_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN));
}
@@ -1340,7 +1319,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
{
esp_configgpio(config->level_gpio_num, gpio_mode);
esp_gpio_matrix_in(config->level_gpio_num,
chan->groups[0].units[unit_id].channels[channel_id].control_sig,
soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
ctl_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN));
}
else
@@ -1348,7 +1328,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev,
/* using virtual IO */
esp_gpio_matrix_in(virt_gpio,
chan->groups[0].units[unit_id].channels[channel_id].control_sig,
soc_pcnt_signals[0].units[unit_id].channels[channel_id].\
ctl_sig_id_matrix,
(config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN));
}
arch/xtensa/src/common/espressif/esp_pm.c
+306 -62
View File
@@ -31,24 +31,30 @@
#include <debug.h>
#include "esp_pm.h"
#include "esp_hr_timer.h"
#ifdef CONFIG_SCHED_TICKLESS
# include "esp_tickless.h"
# if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp32_tickless.h"
# elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# include "esp32s2_tickless.h"
# elif defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp32s3_tickless.h"
# endif
#endif
#include "esp_sleep.h"
#include "soc/rtc.h"
#include "esp_sleep_internal.h"
#include "esp_pmu.h"
#include "esp_attr.h"
#include "esp_private/pm_impl.h"
#ifdef CONFIG_PM_EXT1_WAKEUP
# include "driver/rtc_io.h"
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
# include "driver/gpio.h"
# include "hal/gpio_types.h"
# if defined(CONFIG_ARCH_CHIP_ESP32S3)
# include "esp32s3_gpio.h"
# elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# include "esp32s2_gpio.h"
#endif
# include "esp_gpio.h"
#endif
#ifdef CONFIG_PM_UART_WAKEUP
# include "driver/uart_wakeup.h"
@@ -60,11 +66,17 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_configgpio esp32s3_configgpio
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_configgpio esp32s2_configgpio
#ifdef CONFIG_PM_EXT0_WAKEUP
# define EXT0_WAIT_TIME_US 5000000
#endif
#ifdef CONFIG_PM_EXT1_WAKEUP
# define EXT1_WAIT_TIME_US 5000000
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
# define GPIO_WAIT_TIME_US 5000000
#endif
#ifdef CONFIG_PM_UART_WAKEUP
# define UART_WAIT_TIME_US 5000000
#endif
/****************************************************************************
@@ -92,7 +104,9 @@ const char *g_wakeup_reasons[] =
""
};
static _Atomic uint32_t pm_wakelock = 0;
static esp_sleep_wakeup_cause_t g_last_wakeup_reason =
ESP_SLEEP_WAKEUP_UNDEFINED;
static uint64_t g_last_wakeup_time = 0;
/****************************************************************************
* Private Functions
@@ -360,7 +374,60 @@ static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void)
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO30
io_mask |= BIT(30);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO31
io_mask |= BIT(31);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO32
io_mask |= BIT(32);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO33
io_mask |= BIT(33);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO34
io_mask |= BIT(34);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO35
io_mask |= BIT(35);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO36
io_mask |= BIT(36);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO37
io_mask |= BIT(37);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO38
io_mask |= BIT(38);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO39
io_mask |= BIT(39);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO40
io_mask |= BIT(40);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO41
io_mask |= BIT(41);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO42
io_mask |= BIT(42);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO43
io_mask |= BIT(43);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO44
io_mask |= BIT(44);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO45
io_mask |= BIT(45);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO46
io_mask |= BIT(46);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO47
io_mask |= BIT(47);
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO48
io_mask |= BIT(48);
#endif
return io_mask;
}
@@ -435,6 +502,161 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void)
}
#endif /* CONFIG_PM_UART_WAKEUP */
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
/****************************************************************************
* Name: esp_pm_skip_light_sleep
*
* Description:
* Callback for the power manager's "skip light sleep" hook. This function
* checks if the system should defer entering light sleep after waking up
* from any supported wakeup source (EXT0, EXT1, GPIO, UART). It compares
* the current time to the last wakeup time for each source. If the system
* is still within the configured guard window for any wakeup source, it
* returns true to skip light sleep and let peripheral activity finish. If
* the guard window has elapsed or there was no wakeup, it returns false
* and allows light sleep to proceed.
*
* Placed in IRAM because it runs in timing-critical power management
* decision paths.
*
* Input Parameters:
* None
*
* Returned Value:
* true - Skip light sleep (recent EXT0, EXT1, GPIO, or UART wakeup still
* within the configured guard window).
* false - Allow light sleep (no relevant wakeup or guard window elapsed).
*
****************************************************************************/
static bool IRAM_ATTR esp_pm_skip_light_sleep(void)
{
bool skip = false;
#if defined(CONFIG_PM_EXT0_WAKEUP) || \
defined(CONFIG_PM_EXT1_WAKEUP) || \
defined(CONFIG_PM_GPIO_WAKEUP) || \
defined(CONFIG_PM_UART_WAKEUP)
uint64_t current_time = esp_hr_timer_time_us();
#endif
#ifdef CONFIG_PM_EXT0_WAKEUP
if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT0 &&
current_time < (g_last_wakeup_time + EXT0_WAIT_TIME_US))
{
pwrinfo("EXT0 wakeup still within guard window\n");
skip = true;
}
#endif
#ifdef CONFIG_PM_EXT1_WAKEUP
if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT1 &&
current_time < (g_last_wakeup_time + EXT1_WAIT_TIME_US))
{
pwrinfo("EXT1 wakeup still within guard window\n");
skip = true;
}
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_GPIO &&
current_time < (g_last_wakeup_time + GPIO_WAIT_TIME_US))
{
pwrinfo("GPIO wakeup still within guard window\n");
skip = true;
}
#endif
#ifdef CONFIG_PM_UART_WAKEUP
if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_UART &&
current_time < (g_last_wakeup_time + UART_WAIT_TIME_US))
{
pwrinfo("UART wakeup still within guard window\n");
skip = true;
}
#endif
return skip;
}
/****************************************************************************
* Name: esp_pm_light_sleep_exit_cb
*
* Description:
* Store wakeup reason and timestamp on light sleep exit.
*
* Input Parameters:
* sleep_time_us - Actual sleep time in microseconds (unused).
* arg - User callback argument (unused).
*
* Returned Value:
* ESP_OK
*
****************************************************************************/
static esp_err_t IRAM_ATTR esp_pm_light_sleep_exit_cb(int64_t sleep_time_us,
void *arg)
{
esp_sleep_wakeup_cause_t wc;
uint64_t tw;
UNUSED(sleep_time_us);
UNUSED(arg);
wc = esp_sleep_get_wakeup_cause();
tw = esp_hr_timer_time_us();
esp_pm_wakeup_set_last_reason((int32_t)wc);
esp_pm_wakeup_set_last_time(tw);
return ESP_OK;
}
#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_pm_wakeup_set_last_reason
*
* Description:
* Store the sleep exit wakeup cause after light sleep.
*
* Input Parameters:
* reason - Value from esp_sleep_get_wakeup_cause().
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_wakeup_set_last_reason(int32_t reason)
{
g_last_wakeup_reason = reason;
}
/****************************************************************************
* Name: esp_pm_wakeup_set_last_time
*
* Description:
* Store the high-resolution timestamp (microseconds) for the last light
* sleep exit, together with the cause from
* esp_pm_wakeup_set_last_reason().
*
* Input Parameters:
* time_us - Time from esp_hr_timer_time_us() at exit from light sleep.
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_wakeup_set_last_time(uint64_t time_us)
{
g_last_wakeup_time = time_us;
}
/****************************************************************************
* Name: esp_pm_sleep_enable_timer_wakeup
*
@@ -449,15 +671,11 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void)
*
****************************************************************************/
static void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us)
void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us)
{
esp_sleep_enable_timer_wakeup(time_in_us);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_pm_light_sleep_start
*
@@ -601,59 +819,85 @@ void esp_pmsleep(uint64_t time_in_us)
esp_pm_deep_sleep_start();
}
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
/****************************************************************************
* Name: esp_pm_lockacquire
* Name: esp_pmconfigure
*
* Description:
* Take a power management lock
* Configure power manager.
*
* Input Parameters:
* None
* None.
*
* Returned Value:
* None
* Returns OK on success; a negated errno value on failure.
*
****************************************************************************/
void IRAM_ATTR esp_pm_lockacquire(void)
int esp_pmconfigure(void)
{
++pm_wakelock;
}
/****************************************************************************
* Name: esp_pm_lockrelease
*
* Description:
* Release the lock taken using esp_pm_lockacquire.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp_pm_lockrelease(void)
{
--pm_wakelock;
}
/****************************************************************************
* Name: esp_pm_lockstatus
*
* Description:
* Return power management lock status.
*
* Input Parameters:
* None
*
* Returned Value:
* Current pm_wakelock count
*
****************************************************************************/
uint32_t IRAM_ATTR esp_pm_lockstatus(void)
{
return pm_wakelock;
int ret;
esp_err_t err = ESP_OK;
#ifdef CONFIG_PM_EXT1_WAKEUP
int64_t ext1_mask;
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
int64_t gpio_mask;
#endif
esp_pm_config_t pm_config =
{
.max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
.min_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
.light_sleep_enable = true
#endif
};
ret = esp_pm_configure(&pm_config);
if (ret != OK)
{
return ret;
}
#ifdef CONFIG_PM_EXT0_WAKEUP
esp_pm_ext0_wakeup_prepare();
#endif
#ifdef CONFIG_PM_EXT1_WAKEUP
esp_pm_ext1_wakeup_prepare();
#endif
#ifdef CONFIG_PM_GPIO_WAKEUP
esp_pm_gpio_wakeup_prepare();
#endif
#ifdef CONFIG_PM_UART_WAKEUP
esp_pm_uart_wakeup_prepare();
#endif /* CONFIG_PM_UART_WAKEUP */
err = esp_pm_register_skip_light_sleep_callback(
esp_pm_skip_light_sleep);
if (err != ESP_OK)
{
pwrerr("Failed to register skip light sleep callback: %d\n", err);
return -ENOMEM;
}
esp_pm_sleep_cbs_register_config_t sleep_cbs =
{
.enter_cb = NULL,
.exit_cb = esp_pm_light_sleep_exit_cb,
.enter_cb_user_arg = NULL,
.exit_cb_user_arg = NULL,
.enter_cb_prior = 0,
.exit_cb_prior = 0,
};
err = esp_pm_light_sleep_register_cbs(&sleep_cbs);
if (err != ESP_OK)
{
pwrerr("Failed to register light sleep callbacks: %d\n", err);
return -ENOMEM;
}
return ret;
}
#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */
arch/xtensa/src/common/espressif/esp_pm.h
+39 -13
View File
@@ -44,11 +44,32 @@ extern "C"
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Types
****************************************************************************/
typedef bool (*skip_light_sleep_cb_t)(void);
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_pm_sleep_enable_timer_wakeup
*
* Description:
* Configure wakeup interval
*
* Input Parameters:
* time_in_us - Sleep duration in microseconds.
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp_pm_light_sleep_start
*
@@ -115,52 +136,57 @@ void esp_pmstandby(uint64_t time_in_us);
void esp_pmsleep(uint64_t time_in_us);
/****************************************************************************
* Name: esp_pm_lockacquire
* Name: esp_pmconfigure
*
* Description:
* Take a power management lock
* Configure power manager.
*
* Input Parameters:
* None
*
* Returned Value:
* None
* Returns OK on success; a negated errno value on failure.
*
****************************************************************************/
void esp_pm_lockacquire(void);
#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP
int esp_pmconfigure(void);
#endif
/****************************************************************************
* Name: esp_pm_lockrelease
* Name: esp_pm_wakeup_set_last_reason
*
* Description:
* Release the lock taken using esp_pm_lockacquire.
* Store the sleep exit wakeup cause after light sleep. Used with
* esp_pm_wakeup_set_last_time() so the skip-light-sleep hook can
* detect a recent UART wakeup.
*
* Input Parameters:
* None
* reason - Value from esp_sleep_get_wakeup_cause().
*
* Returned Value:
* None
*
****************************************************************************/
void esp_pm_lockrelease(void);
void esp_pm_wakeup_set_last_reason(int32_t reason);
/****************************************************************************
* Name: esp_pm_lockstatus
* Name: esp_pm_wakeup_set_last_time
*
* Description:
* Return power management lock status.
* Store the high-resolution timestamp (microseconds) aligned with
* the wakeup cause set by esp_pm_wakeup_set_last_reason().
*
* Input Parameters:
* None
* time_us - Time from esp_hr_timer_time_us() at exit from light sleep.
*
* Returned Value:
* Current pm_wakelock count
* None
*
****************************************************************************/
uint32_t esp_pm_lockstatus(void);
void esp_pm_wakeup_set_last_time(uint64_t time_us);
#endif /* CONFIG_PM */
arch/xtensa/src/common/espressif/esp_rmt.c
+222 -1756
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/common/espressif/esp_rmt.h
+21 -23
View File
@@ -20,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H
/****************************************************************************
* Included Files
@@ -67,6 +67,22 @@ extern "C"
#if defined(CONFIG_ESP_RMT)
/****************************************************************************
* Name: esp_rmt_rx_init
*
* Description:
* Initialize the selected RMT device in RX mode
*
* Input Parameters:
* rx_pin - The pin used for the RX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_rx_init(int rx_pin);
/****************************************************************************
* Name: esp_rmt_tx_init
*
@@ -74,32 +90,14 @@ extern "C"
* Initialize the selected RMT device in TX mode
*
* Input Parameters:
* ch - The RMT's channel that will be used
* pin - The pin used for the TX channel
* tx_pin - The pin used for the TX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin);
/****************************************************************************
* Name: esp_rmt_rx_init
*
* Description:
* Initialize the selected RMT device in RC mode
*
* Input Parameters:
* ch - The RMT's channel that will be used
* pin - The pin used for the RX channel
*
* Returned Value:
* Valid RMT device structure reference on success; NULL, otherwise.
*
****************************************************************************/
struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
struct rmt_dev_s *esp_rmt_tx_init(int tx_pin);
#endif
@@ -108,4 +106,4 @@ struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H */
arch/xtensa/src/common/espressif/esp_rtc.c
+895
View File
File diff suppressed because it is too large Load Diff
arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h → arch/xtensa/src/common/espressif/esp_rtc.h
+12 -15
View File
@@ -1,5 +1,7 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h
* arch/xtensa/src/common/espressif/esp_rtc.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,8 +20,8 @@
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H
/****************************************************************************
* Included Files
@@ -27,30 +29,25 @@
#include <nuttx/config.h>
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_rtc_driverinit
* Name: esp_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
* Initialize and register an RTC lower half driver.
*
* Input Parameters:
* None
* None.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
int esp32_rtc_driverinit(void);
int esp_rtc_driverinit(void);
#endif /* CONFIG_RTC_DRIVER */
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H */
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H */
arch/xtensa/src/common/espressif/esp_sdm.c
+27 -35
View File
@@ -42,40 +42,27 @@
#include <nuttx/spinlock.h>
#include "esp_sdm.h"
#include "hal/gpio_ll.h"
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#include "hardware/esp32s3_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#include "hardware/esp32s2_soc.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#include "esp32_gpio.h"
#include "hardware/esp32_soc.h"
#include "esp_gpio.h"
#endif
#include "esp_clk_tree.h"
#include "hal/sdm_hal.h"
#include "hal/sdm_ll.h"
#include "soc/sdm_periph.h"
#include "hal/sdm_periph.h"
#include "hal/sdm_caps.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define esp_configgpio esp32s3_configgpio
#define esp_gpio_matrix_in esp32s3_gpio_matrix_in
#define esp_gpio_matrix_out esp32s3_gpio_matrix_out
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define esp_configgpio esp32s2_configgpio
#define esp_gpio_matrix_in esp32s2_gpio_matrix_in
#define esp_gpio_matrix_out esp32s2_gpio_matrix_out
#elif defined(CONFIG_ARCH_CHIP_ESP32)
#define esp_configgpio esp32_configgpio
#define esp_gpio_matrix_in esp32_gpio_matrix_in
#define esp_gpio_matrix_out esp32_gpio_matrix_out
#endif
/****************************************************************************
* Private Types
****************************************************************************/
@@ -92,18 +79,18 @@ struct esp_sdm_channel_priv_s
struct esp_sdm_group_priv_s
{
int group_id; /* Group ID, index from 0 */
spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
sdm_hal_context_t hal; /* Common layer context */
soc_periph_sdm_clk_src_t clk_src; /* Clock source */
struct esp_sdm_channel_priv_s *channels[SOC_SDM_CHANNELS_PER_GROUP]; /* Array of SDM channels */
int group_id; /* Group ID, index from 0 */
spinlock_t spinlock; /* Spinlock for protecting concurrent operations */
sdm_hal_context_t hal; /* Common layer context */
soc_periph_sdm_clk_src_t clk_src; /* Clock source */
struct esp_sdm_channel_priv_s *channels[SDM_CAPS_GET(CHANS_PER_INST)]; /* Array of SDM channels */
};
struct esp_sdm_priv_s
{
rmutex_t lock; /* Lock for protecting concurrent operations */
struct esp_sdm_group_priv_s *groups[SOC_SDM_GROUPS]; /* SDM group pool */
int group_ref_counts[SOC_SDM_GROUPS]; /* Reference count used to protect group install/uninstall */
rmutex_t lock; /* Lock for protecting concurrent operations */
struct esp_sdm_group_priv_s *groups[SDM_CAPS_GET(INST_NUM)]; /* SDM group pool */
int group_ref_counts[SDM_CAPS_GET(INST_NUM)]; /* Reference count used to protect group install/uninstall */
};
/****************************************************************************
@@ -382,7 +369,7 @@ struct esp_sdm_channel_priv_s *esp_sdm_create_config_channel(
esp_configgpio(config.gpio_num, attr);
esp_gpio_matrix_out(config.gpio_num,
sigma_delta_periph_signals.channels[ret->chan_id].sd_sig,
soc_sdm_signals[group_id].channels[ret->chan_id].sig_id_matrix,
(config.flags && INVERT_OUT), false);
esp_clk_tree_src_get_freq_hz(g_esp_sdm.groups[ret->group_id]->clk_src,
@@ -431,7 +418,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
for (i = 0; i < SOC_SDM_GROUPS; i++)
for (i = 0; i < SDM_CAPS_GET(INST_NUM); i++)
{
nxrmutex_lock(&(g_esp_sdm.lock));
if (g_esp_sdm.groups[i] == NULL)
@@ -445,16 +432,21 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
else
{
sdm_hal_init_config_t hal_config =
{
.group_id = group_id,
};
g_esp_sdm.groups[i]->group_id = i;
g_esp_sdm.groups[i]->clk_src = SDM_CLK_SRC_DEFAULT;
group_id = i;
sdm_hal_init(&g_esp_sdm.groups[i]->hal, i);
sdm_hal_init(&g_esp_sdm.groups[i]->hal, &hal_config);
sdm_ll_enable_clock(g_esp_sdm.groups[i]->hal.dev, true);
ainfo("new group (%d) at %p\n", i, g_esp_sdm.groups[i]);
break;
}
}
else if (g_esp_sdm.group_ref_counts[i] < SOC_SDM_CHANNELS_PER_GROUP)
else if (g_esp_sdm.group_ref_counts[i] < SDM_CAPS_GET(CHANS_PER_INST))
{
group_id = i;
break;
@@ -462,7 +454,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
}
if (g_esp_sdm.group_ref_counts[group_id] >=
SOC_SDM_CHANNELS_PER_GROUP)
SDM_CAPS_GET(CHANS_PER_INST))
{
aerr("ERROR! No free slot available\n");
return NULL;
@@ -473,7 +465,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init(
nxrmutex_unlock(&(g_esp_sdm.lock));
flags = spin_lock_irqsave(&group->spinlock);
for (j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++)
for (j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++)
{
if (group->channels[j] == NULL)
{
@@ -541,7 +533,7 @@ int esp_sdm_create_channel(struct esp_sdm_chan_config_s config,
DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num));
for (i = 0; i < SOC_SDM_CHANNELS_PER_GROUP; i++)
for (i = 0; i < SDM_CAPS_GET(CHANS_PER_INST); i++)
{
if (group->channels[i] == NULL)
{
@@ -602,7 +594,7 @@ struct dac_dev_s *esp_sdminitialize(struct esp_sdm_chan_config_s config)
{
ret->ad_priv = (void *)sdm;
ret->ad_ops = &ops;
ret->ad_nchannel = SOC_SDM_CHANNELS_PER_GROUP;
ret->ad_nchannel = SDM_CAPS_GET(CHANS_PER_INST);
}
return (struct dac_dev_s *)ret;
arch/xtensa/src/common/espressif/esp_sha.c
+22 -1
View File
@@ -39,11 +39,19 @@
#include "esp_sha.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_crypto_lock_internal.h"
#include "soc/periph_defs.h"
#include "hal/sha_ll.h"
#include "hal/sha_hal.h"
#include "soc/soc_caps.h"
#include "rom/cache.h"
/* Crypto DMA, shared between AES and SHA */
#if SOC_AES_CRYPTO_DMA && SOC_SHA_CRYPTO_DMA
# include "hal/crypto_dma_ll.h"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -276,6 +284,7 @@ int esp_sha1_update(struct esp_sha1_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -500,6 +509,7 @@ int esp_sha256_update(struct esp_sha256_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -721,6 +731,7 @@ int esp_sha512_update(struct esp_sha512_context_s *ctx,
return ret;
}
sha_hal_set_mode(ctx->mode);
if (ctx->sha_state == ESP_SHA_STATE_INIT)
{
ctx->first_block = true;
@@ -852,7 +863,17 @@ int esp_sha_init(void)
{
if (!g_sha_inited)
{
periph_module_enable(PERIPH_SHA_MODULE);
SHA_RCC_ATOMIC()
{
sha_ll_enable_bus_clock(true);
sha_ll_reset_register();
#if SOC_SHA_CRYPTO_DMA
crypto_dma_ll_enable_bus_clock(true);
crypto_dma_ll_reset_register();
#endif
}
g_sha_inited = true;
}
else
arch/xtensa/src/common/espressif/esp_spi_bitbang.c
+12 -12
View File
@@ -43,13 +43,13 @@
#include <nuttx/spi/spi_bitbang.c>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#include "hardware/esp32s3_gpio_sigmap.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#include "esp32s2_gpio_sigmap.h"
#else
#include "esp32_gpio.h"
#include "esp_gpio.h"
#include "esp32_gpio_sigmap.h"
#endif
@@ -58,16 +58,17 @@
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#else
#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \
#else#if defined(CONFIG_ARCH_CHIP_ESP32)
#endif
#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr)
#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \
idx, inv, en_inv)
#endif
@@ -231,11 +232,10 @@ struct spi_dev_s *esp_spi_bitbang_init(void)
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, true);
GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_CLKPIN, true);
#if CONFIG_ESPRESSIF_SPI_SWCS
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, SIG_GPIO_OUT_IDX,
0, 0);
#endif
CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, OUTPUT_FUNCTION_1);
GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, SIG_GPIO_OUT_IDX,
0, 0);
arch/xtensa/src/common/espressif/esp_spi_bitbang.h
+8 -8
View File
@@ -47,11 +47,11 @@ extern "C"
#include <nuttx/spi/spi.h>
#include <nuttx/spi/spi_bitbang.h>
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#include "esp32s3_gpio.h"
#include "esp_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#include "esp32s2_gpio.h"
#include "espressif/esp_gpio.h"
#else
#include "esp32_gpio.h"
#include "esp_gpio.h"
#endif
/****************************************************************************
@@ -59,13 +59,13 @@ extern "C"
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_ESP32S3)
#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s3_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value)
#define GPIO_READ(pin) esp32s2_gpioread(pin)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp_gpioread(pin)
#else
#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value)
#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value)
#define GPIO_READ(pin) esp3_gpioread(pin)
#endif
arch/xtensa/src/common/espressif/esp_spiflash.c
+3 -175
View File
@@ -45,11 +45,11 @@
#include "bootloader_flash_priv.h"
#if defined(CONFIG_ARCH_CHIP_ESP32)
# include "esp32_irq.h"
# include "esp_irq.h"
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# include "esp32s2_irq.h"
# include "espressif/esp_irq.h"
#else
# include "esp32s3_irq.h"
# include "esp_irq.h"
#endif
/****************************************************************************
@@ -64,17 +64,6 @@
# error "SPIRAM requires legacy SPI Flash driver"
#endif
#if defined(CONFIG_ARCH_CHIP_ESP32)
# define esp_intr_noniram_enable esp32_irq_noniram_enable
# define esp_intr_noniram_disable esp32_irq_noniram_disable
#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
# define esp_intr_noniram_disable esp32s2_irq_noniram_disable
# define esp_intr_noniram_enable esp32s2_irq_noniram_enable
#else
# define esp_intr_noniram_enable esp32s3_irq_noniram_enable
# define esp_intr_noniram_disable esp32s3_irq_noniram_disable
#endif
#ifdef CONFIG_ESPRESSIF_EFUSE_VIRTUAL_KEEP_IN_FLASH
#define ENCRYPTION_IS_VIRTUAL (!efuse_hal_flash_encryption_enabled())
#else
@@ -493,126 +482,6 @@ static bool aligned_flash_erase(size_t addr, size_t size)
}
#endif /* CONFIG_ESP_FLASH_ENCRYPTION */
/****************************************************************************
* Name: spi_flash_op_block_task
*
* Description:
* Disable the non-IRAM interrupts on the other core (the one that isn't
* handling the SPI flash operation) and notify that the SPI flash
* operation can start. Wait on a busy loop until it's finished and then
* re-enable the non-IRAM interrupts.
*
* Input Parameters:
* argc - Not used.
* argv - Not used.
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned to
* indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_SMP
static int spi_flash_op_block_task(int argc, char *argv[])
{
struct tcb_s *tcb = this_task();
int cpu = this_cpu();
for (; ; )
{
DEBUGASSERT((1 << cpu) & tcb->affinity);
/* Wait for a request from the other CPU to suspend interrupts
* and cache on this CPU.
*/
nxsem_wait(&g_cpu_prepare_sem[cpu]);
sched_lock();
esp_intr_noniram_disable();
s_flash_op_complete = false;
s_flash_op_can_start = true;
while (!s_flash_op_complete)
{
/* Wait for a request to restore interrupts and cache on this CPU.
* This indicates SPI Flash operation is complete.
*/
}
esp_intr_noniram_enable();
sched_unlock();
}
return OK;
}
/****************************************************************************
* Name: spiflash_init_spi_flash_op_block_task
*
* Description:
* Starts a kernel thread that waits for a semaphore indicating that a SPI
* flash operation is going to take place in the other CPU.
*
* Input Parameters:
* cpu - The CPU core that will run the created task to wait on a busy
* loop while the SPI flash operation finishes
*
* Returned Value:
* 0 (OK) on success; A negated errno value on failure.
*
****************************************************************************/
static int spiflash_init_spi_flash_op_block_task(int cpu)
{
FAR struct tcb_s *tcb;
int ret;
char *argv[2];
char arg1[32];
cpu_set_t cpuset;
snprintf(arg1, sizeof(arg1), "%p", &cpu);
argv[0] = arg1;
argv[1] = NULL;
/* Allocate a TCB for the new task. */
tcb = kmm_zalloc(sizeof(struct tcb_s));
if (!tcb)
{
serr("ERROR: Failed to allocate TCB\n");
return -ENOMEM;
}
/* Setup the task type */
tcb->flags = TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_FREE_TCB;
/* Initialize the task */
ret = nxtask_init(tcb, "spiflash_op",
SCHED_PRIORITY_MAX,
NULL, SPIFLASH_OP_TASK_STACKSIZE,
spi_flash_op_block_task, argv, environ, NULL);
if (ret < OK)
{
kmm_free(tcb);
return ret;
}
/* Set the affinity */
CPU_ZERO(&cpuset);
CPU_SET(cpu, &cpuset);
tcb->affinity = cpuset;
/* Activate the task */
nxtask_activate(tcb);
return ret;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -770,44 +639,3 @@ int esp_spiflash_erase(uint32_t address, uint32_t length)
return ret;
}
/****************************************************************************
* Name: esp_spiflash_init
*
* Description:
* Initialize ESP SPI flash driver.
* SPI Flash actual chip initialization initial is done by esp_start on
* STARTUP_FN hook.
*
* Input Parameters:
* None.
*
* Returned Value:
* OK if success or a negative value if fail.
*
****************************************************************************/
int esp_spiflash_init(void)
{
int ret = OK;
int cpu;
#ifdef CONFIG_SMP
sched_lock();
for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++)
{
ret = spiflash_init_spi_flash_op_block_task(cpu);
if (ret != OK)
{
return ret;
}
}
sched_unlock();
#else
UNUSED(cpu);
#endif
return ret;
}
arch/xtensa/src/common/espressif/esp_spiflash.h
-16
View File
@@ -106,22 +106,6 @@ int esp_spiflash_erase(uint32_t address, uint32_t length);
int esp_spiflash_write(uint32_t address, const void *buffer,
uint32_t length);
/****************************************************************************
* Name: esp_spiflash_init
*
* Description:
* Initialize ESP SPI flash driver.
*
* Input Parameters:
* None.
*
* Returned Value:
* OK if success or a negative value if fail.
*
****************************************************************************/
int esp_spiflash_init(void);
#ifdef __cplusplus
}
#endif
arch/xtensa/src/common/espressif/esp_temperature_sensor.c
+4 -8
View File
@@ -61,8 +61,7 @@
#include "hal/regi2c_ctrl.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/temperature_sensor_types.h"
#include "soc/temperature_sensor_periph.h"
#include "esp_efuse_rtc_calib.h"
#include "hal/temperature_sensor_periph.h"
#include "hal/adc_ll.h"
/****************************************************************************
@@ -105,7 +104,6 @@ struct esp_temp_priv_s
const temperature_sensor_attribute_t *tsens_attribute; /* Attribute struct of the common layer */
struct esp_temp_sensor_config_t cfg; /* Configuration struct of the common layer */
temperature_sensor_clk_src_t clk_src; /* Clock source to use */
int module; /* Peripheral module */
int refs; /* Reference count */
mutex_t lock; /* Mutual exclusion mutex */
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -197,7 +195,6 @@ struct esp_temp_priv_s esp_temp_priv =
0
},
.clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT,
.module = PERIPH_TEMPSENSOR_MODULE,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifdef CONFIG_ESPRESSIF_TEMP_UORB
@@ -321,11 +318,10 @@ static int temperature_sensor_choose_best_range(struct esp_temp_priv_s *priv)
static int temperature_sensor_read_delta_t(void)
{
if (esp_efuse_rtc_calib_get_tsens_val(&g_delta_t) != OK)
g_delta_t = temperature_sensor_ll_load_calib_param();
if (g_delta_t == 0)
{
snwarn("Calibration failed");
g_delta_t = 0;
return ERROR;
snwarn("No calibration param in eFuse");
}
sninfo("delta_T = %f", g_delta_t);
arch/xtensa/src/common/espressif/esp_timer_adapter.c
+492
View File
@@ -0,0 +1,492 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_timer_adapter.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <nuttx/kmalloc.h>
#include <nuttx/spinlock.h>
#include "esp_timer.h"
#include "esp_timer_adapter.h"
#include "esp_private/esp_timer_private.h"
#include "esp_timer_impl.h"
/****************************************************************************
* Private Types
****************************************************************************/
/* HR timer data structure wrapping HAL esp_timer (internal definition) */
struct esp_hr_timer_s
{
esp_timer_handle_t hal_timer; /* HAL timer handle */
uint64_t timeout; /* Timeout value */
uint64_t alarm; /* Timeout period */
void (*callback)(void *arg); /* Callback function */
void *arg; /* Private data */
uint16_t flags; /* Supported features */
enum esp_hr_timer_state_e state; /* Timer state */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void esp_hr_timer_callback_wrapper(void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
static spinlock_t g_hr_timer_lock = SP_UNLOCKED;
static bool g_hr_timer_initialized = false;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp_hr_timer_callback_wrapper
*
* Description:
* Adapter callback used by esp_timer to dispatch to the upper-layer timer
* callback and update the timer state.
*
* Input Parameters:
* arg - Pointer to struct esp_hr_timer_s.
*
* Returned Value:
* None.
*
****************************************************************************/
static void esp_hr_timer_callback_wrapper(void *arg)
{
struct esp_hr_timer_s *timer = (struct esp_hr_timer_s *)arg;
if (timer && timer->callback)
{
timer->state = HR_TIMER_TIMEOUT;
timer->callback(timer->arg);
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp_hr_timer_create
*
* Description:
* Create a high-resolution timer instance and initialize it from the
* provided arguments.
*
* Input Parameters:
* args - Timer creation arguments.
* timer_handle - Location where the created timer handle is returned.
*
* Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
int esp_hr_timer_create(const struct esp_hr_timer_args_s *args,
struct esp_hr_timer_s **timer_handle)
{
struct esp_hr_timer_s *timer;
esp_timer_create_args_t hal_args;
esp_err_t ret;
if (args == NULL || timer_handle == NULL || args->callback == NULL)
{
return -EINVAL;
}
timer = kmm_zalloc(sizeof(struct esp_hr_timer_s));
if (timer == NULL)
{
return -ENOMEM;
}
timer->callback = args->callback;
timer->arg = args->arg;
timer->flags = HR_TIMER_NOFLAGS;
timer->state = HR_TIMER_IDLE;
hal_args.callback = esp_hr_timer_callback_wrapper;
hal_args.arg = timer;
hal_args.dispatch_method = ESP_TIMER_TASK;
hal_args.name = args->name ? args->name : "nuttx_hr";
hal_args.skip_unhandled_events = args->skip_unhandled_events;
ret = esp_timer_create(&hal_args, &timer->hal_timer);
if (ret != ESP_OK)
{
kmm_free(timer);
return -EINVAL;
}
*timer_handle = timer;
return OK;
}
/****************************************************************************
* Name: esp_hr_timer_start
*
* Description:
* Start a high-resolution timer in one-shot or periodic mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - Timeout period in microseconds.
* repeat - True for periodic mode, false for one-shot mode.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start(struct esp_hr_timer_s *timer,
uint64_t timeout,
bool repeat)
{
esp_err_t ret;
if (timer == NULL)
{
return ERROR;
}
timer->timeout = timeout;
if (repeat)
{
timer->flags |= HR_TIMER_REPEAT;
ret = esp_timer_start_periodic(timer->hal_timer, timeout);
}
else
{
timer->flags &= ~HR_TIMER_REPEAT;
ret = esp_timer_start_once(timer->hal_timer, timeout);
}
if (ret == ESP_OK)
{
timer->state = HR_TIMER_READY;
return OK;
}
return ERROR;
}
/****************************************************************************
* Name: esp_hr_timer_start_once
*
* Description:
* Start a high-resolution timer in one-shot mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - One-shot timeout in microseconds.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout)
{
return esp_hr_timer_start(timer, timeout, false);
}
/****************************************************************************
* Name: esp_hr_timer_start_periodic
*
* Description:
* Start a high-resolution timer in periodic mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - Period interval in microseconds.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer,
uint64_t timeout)
{
return esp_hr_timer_start(timer, timeout, true);
}
/****************************************************************************
* Name: esp_hr_timer_stop
*
* Description:
* Stop a running high-resolution timer.
*
* Input Parameters:
* timer - Timer instance to stop.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_stop(struct esp_hr_timer_s *timer)
{
esp_err_t ret;
if (timer == NULL)
{
return ERROR;
}
ret = esp_timer_stop(timer->hal_timer);
if (ret == ESP_OK)
{
timer->state = HR_TIMER_IDLE;
return OK;
}
return ERROR;
}
/****************************************************************************
* Name: esp_hr_timer_stop_nolock
*
* Description:
* Stop a running high-resolution timer without taking any adapter lock.
*
* Input Parameters:
* timer - Timer instance to stop.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_stop_nolock(struct esp_hr_timer_s *timer)
{
/* esp_timer already handles its own locking */
return esp_hr_timer_stop(timer);
}
/****************************************************************************
* Name: esp_hr_timer_delete
*
* Description:
* Delete a timer instance and release associated resources.
*
* Input Parameters:
* timer - Timer instance to delete.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_delete(struct esp_hr_timer_s *timer)
{
esp_err_t ret;
if (timer == NULL)
{
return ERROR;
}
timer->state = HR_TIMER_DELETE;
ret = esp_timer_delete(timer->hal_timer);
if (ret == ESP_OK)
{
kmm_free(timer);
return OK;
}
return ERROR;
}
/****************************************************************************
* Name: esp_hr_timer_time_us
*
* Description:
* Return the current high-resolution timer time in microseconds.
*
* Input Parameters:
* None.
*
* Returned Value:
* Current timer time in microseconds.
*
****************************************************************************/
uint64_t esp_hr_timer_time_us(void)
{
return esp_timer_impl_get_time();
}
/****************************************************************************
* Name: esp_hr_timer_get_alarm
*
* Description:
* Return the timestamp of the next scheduled timer alarm.
*
* Input Parameters:
* None.
*
* Returned Value:
* Absolute time in microseconds for the next alarm.
*
****************************************************************************/
uint64_t esp_hr_timer_get_alarm(void)
{
return esp_timer_get_next_alarm();
}
/****************************************************************************
* Name: esp_hr_timer_calibration
*
* Description:
* Apply a timer calibration adjustment.
* The HAL esp_timer backend does not support calibration, so this is a
* no-op.
*
* Input Parameters:
* time_us - Calibration adjustment in microseconds.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_calibration(uint64_t time_us)
{
/* HAL esp_timer doesn't support calibration */
}
/****************************************************************************
* Name: esp_hr_timer_set
*
* Description:
* Set the high-resolution timer counter to a specific timestamp.
*
* Input Parameters:
* new_us - New timer value in microseconds.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_set(uint64_t new_us)
{
/* Use HAL function to set timer */
esp_timer_private_set(new_us);
}
/****************************************************************************
* Name: esp_hr_timer_lock
*
* Description:
* Acquire the adapter lock used to serialize timer operations.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_lock(void)
{
spin_lock(&g_hr_timer_lock);
}
/****************************************************************************
* Name: esp_hr_timer_unlock
*
* Description:
* Release the adapter lock used to serialize timer operations.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_unlock(void)
{
spin_unlock(&g_hr_timer_lock);
}
/****************************************************************************
* Name: esp_hr_timer_init
*
* Description:
* Initialize the timer adapter and the underlying ESP timer subsystem.
*
* Input Parameters:
* None.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_init(void)
{
esp_err_t ret;
if (g_hr_timer_initialized)
{
return OK;
}
/* Initialize the timer subsystem */
ret = esp_timer_init();
if (ret == ESP_OK)
{
g_hr_timer_initialized = true;
return OK;
}
return ERROR;
}
arch/xtensa/src/common/espressif/esp_timer_adapter.h
+324
View File
@@ -0,0 +1,324 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_timer_adapter.h
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H
#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define HR_TIMER_NOFLAGS (0) /* Timer supports no feature */
#define HR_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */
/****************************************************************************
* Public Types
****************************************************************************/
/* HR Timer state (simplified for adapter) */
enum esp_hr_timer_state_e
{
HR_TIMER_IDLE, /* Timer is not counting */
HR_TIMER_READY, /* Timer is counting */
HR_TIMER_TIMEOUT, /* Timer timed out */
HR_TIMER_DELETE /* Timer is to be deleted */
};
/* Forward declaration - opaque type */
struct esp_hr_timer_s;
/* HR Timer creation arguments data structure */
struct esp_hr_timer_args_s
{
void (*callback)(void *arg); /* Callback function */
void *arg; /* Private data */
const char *name; /* Timer name */
bool skip_unhandled_events; /* Skip unhandled events for periodic timers */
};
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp_hr_timer_create
*
* Description:
* Create a high-resolution timer instance and initialize it from the
* provided arguments.
*
* Input Parameters:
* args - Timer creation arguments.
* timer_handle - Location where the created timer handle is returned.
*
* Returned Value:
* OK on success; a negated errno value on failure.
*
****************************************************************************/
int esp_hr_timer_create(const struct esp_hr_timer_args_s *args,
struct esp_hr_timer_s **timer_handle);
/****************************************************************************
* Name: esp_hr_timer_start
*
* Description:
* Start a high-resolution timer in one-shot or periodic mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - Timeout period in microseconds.
* repeat - True for periodic mode, false for one-shot mode.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start(struct esp_hr_timer_s *timer,
uint64_t timeout,
bool repeat);
/****************************************************************************
* Name: esp_hr_timer_start_once
*
* Description:
* Start a high-resolution timer in one-shot mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - One-shot timeout in microseconds.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout);
/****************************************************************************
* Name: esp_hr_timer_start_periodic
*
* Description:
* Start a high-resolution timer in periodic mode.
*
* Input Parameters:
* timer - Timer instance to start.
* timeout - Period interval in microseconds.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer,
uint64_t timeout);
/****************************************************************************
* Name: esp_hr_timer_stop
*
* Description:
* Stop a running high-resolution timer.
*
* Input Parameters:
* timer - Timer instance to stop.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_stop(struct esp_hr_timer_s *timer);
/****************************************************************************
* Name: esp_hr_timer_stop_nolock
*
* Description:
* Stop a running high-resolution timer without taking any adapter lock.
*
* Input Parameters:
* timer - Timer instance to stop.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_stop_nolock(struct esp_hr_timer_s *timer);
/****************************************************************************
* Name: esp_hr_timer_delete
*
* Description:
* Delete a timer instance and release associated resources.
*
* Input Parameters:
* timer - Timer instance to delete.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_delete(struct esp_hr_timer_s *timer);
/****************************************************************************
* Name: esp_hr_timer_time_us
*
* Description:
* Return the current high-resolution timer time in microseconds.
*
* Input Parameters:
* None.
*
* Returned Value:
* Current timer time in microseconds.
*
****************************************************************************/
uint64_t esp_hr_timer_time_us(void);
/****************************************************************************
* Name: esp_hr_timer_get_alarm
*
* Description:
* Return the timestamp of the next scheduled timer alarm.
*
* Input Parameters:
* None.
*
* Returned Value:
* Absolute time in microseconds for the next alarm.
*
****************************************************************************/
uint64_t esp_hr_timer_get_alarm(void);
/****************************************************************************
* Name: esp_hr_timer_calibration
*
* Description:
* Apply a timer calibration adjustment.
* The ESP timer backend does not support calibration, so this operation
* is a no-op.
*
* Input Parameters:
* time_us - Calibration adjustment in microseconds.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_calibration(uint64_t time_us);
/****************************************************************************
* Name: esp_hr_timer_set
*
* Description:
* Set the high-resolution timer counter to a specific timestamp.
*
* Input Parameters:
* new_us - New timer value in microseconds.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_set(uint64_t new_us);
/****************************************************************************
* Name: esp_hr_timer_lock
*
* Description:
* Acquire the adapter lock used to serialize timer operations.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_lock(void);
/****************************************************************************
* Name: esp_hr_timer_unlock
*
* Description:
* Release the adapter lock used to serialize timer operations.
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_hr_timer_unlock(void);
/****************************************************************************
* Name: esp_hr_timer_init
*
* Description:
* Initialize the timer adapter and the underlying ESP timer subsystem.
*
* Input Parameters:
* None.
*
* Returned Value:
* OK on success; ERROR on failure.
*
****************************************************************************/
int esp_hr_timer_init(void);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H */
arch/xtensa/src/common/espressif/esp_ulp.mk
+8 -1
View File
@@ -36,6 +36,14 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)ulp
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include
@@ -68,7 +76,6 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)c
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_core$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include
ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include
# Linker scripts
arch/xtensa/src/common/espressif/esp_wireless.c
+27 -179
View File
@@ -38,25 +38,24 @@
#include "hardware/esp32_dport.h"
#include "hardware/esp32_emac.h"
#include "hardware/esp32_soc.h"
#include "esp32_irq.h"
#include "esp_irq.h"
#include "esp32_partition.h"
#elif CONFIG_ARCH_CHIP_ESP32S2
#include "hardware/esp32s2_efuse.h"
#include "hardware/esp32s2_rtccntl.h"
#include "soc/efuse_reg.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_syscon.h"
#include "hardware/esp32s2_system.h"
#include "esp32s2_irq.h"
#include "espressif/esp_irq.h"
/* #include "esp32s2_partition.h" */
#elif CONFIG_ARCH_CHIP_ESP32S3
#include "hardware/esp32s3_efuse.h"
#include "hardware/esp32s3_rtccntl.h"
#include "soc/efuse_reg.h"
#include "hardware/esp32s3_soc.h"
#include "hardware/esp32s3_syscon.h"
#include "hardware/esp32s3_system.h"
#include "esp32s3_irq.h"
#include "esp_irq.h"
#include "esp32s3_partition.h"
#endif
#include "esp_hr_timer.h"
#include "esp_private/phy.h"
#ifdef CONFIG_ESPRESSIF_WIFI
@@ -85,26 +84,16 @@
# define SWI_PERIPH ESP32_PERIPH_CPU_CPU2
# define esp_partition_read esp32_partition_read
# define esp_partition_write esp32_partition_write
# define esp_setup_irq esp32_setup_irq
# define esp_teardown_irq esp32_teardown_irq
#elif CONFIG_ARCH_CHIP_ESP32S2
# define SWI_IRQ ESP32S2_IRQ_INT_FROM_CPU2
# define SWI_PERIPH ESP32S2_PERIPH_INT_FROM_CPU2
# define esp_partition_read esp32s2_partition_read
# define esp_partition_write esp32s2_partition_write
# define esp_setup_irq esp32s2_setup_irq
# define esp_teardown_irq esp32s2_teardown_irq
#elif CONFIG_ARCH_CHIP_ESP32S3
# define SWI_IRQ ESP32S3_IRQ_INT_FROM_CPU2
# define SWI_PERIPH ESP32S3_PERIPH_INT_FROM_CPU2
# define esp_partition_read esp32s3_partition_read
# define esp_partition_write esp32s3_partition_write
# define rt_timer_create esp32s3_rt_timer_create
# define rt_timer_start esp32s3_rt_timer_start
# define rt_timer_stop esp32s3_rt_timer_stop
# define rt_timer_delete esp32s3_rt_timer_delete
# define esp_setup_irq esp32s3_setup_irq
# define esp_teardown_irq esp32s3_teardown_irq
#endif
/****************************************************************************
@@ -302,13 +291,13 @@ static inline void phy_digital_regs_load(void)
* Wireless software interrupt callback function.
*
* Parameters:
* cpuint - CPU interrupt index
* context - Context data from the ISR
* arg - NULL
* irq - The IRQ number;
* context - The interrupt context;
* arg - Parameter for the interrupt handler
*
* Returned Value:
* Zero (OK) is returned on success. A negated errno value is returned on
* failure.
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
@@ -941,137 +930,6 @@ int esp_phy_update_country_info(const char *country)
return OK;
}
/****************************************************************************
* Name: esp_timer_create
*
* Description:
* Create timer with given arguments
*
* Input Parameters:
* create_args - Timer arguments data pointer
* out_handle - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_timer_create(const esp_timer_create_args_t *create_args,
esp_timer_handle_t *out_handle)
{
int ret;
struct rt_timer_args_s rt_timer_args;
struct rt_timer_s *rt_timer;
rt_timer_args.arg = create_args->arg;
rt_timer_args.callback = create_args->callback;
ret = rt_timer_create(&rt_timer_args, &rt_timer);
if (ret != 0)
{
wlerr("Failed to create rt_timer error=%d\n", ret);
return ret;
}
*out_handle = (esp_timer_handle_t)rt_timer;
return 0;
}
/****************************************************************************
* Name: esp_timer_start_once
*
* Description:
* Start timer with one shot mode
*
* Input Parameters:
* timer - Timer handle pointer
* timeout_us - Timeout value by micro second
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_start(rt_timer, timeout_us, false);
return 0;
}
/****************************************************************************
* Name: esp_timer_start_periodic
*
* Description:
* Start timer with periodic mode
*
* Input Parameters:
* timer - Timer handle pointer
* period - Timeout value by micro second
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_start(rt_timer, period, true);
return 0;
}
/****************************************************************************
* Name: esp_timer_stop
*
* Description:
* Stop timer
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_timer_stop(esp_timer_handle_t timer)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_stop(rt_timer);
return 0;
}
/****************************************************************************
* Name: esp_timer_delete
*
* Description:
* Delete timer and free resource
*
* Input Parameters:
* timer - Timer handle pointer
*
* Returned Value:
* 0 if success or -1 if fail
*
****************************************************************************/
int esp_timer_delete(esp_timer_handle_t timer)
{
struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer;
rt_timer_delete(rt_timer);
return 0;
}
/****************************************************************************
* Name: esp_init_semcache
*
@@ -1274,11 +1132,24 @@ int esp_wireless_init(void)
}
#ifdef CONFIG_ARCH_CHIP_ESP32
priv->cpuint = esp_setup_irq(0, SWI_PERIPH, 1, ESP32_CPUINT_LEVEL);
priv->cpuint = esp_setup_irq(SWI_PERIPH,
1,
ESP_IRQ_TRIGGER_LEVEL,
esp_swi_irq,
NULL);
#elif CONFIG_ARCH_CHIP_ESP32S2
priv->cpuint = esp_setup_irq(SWI_PERIPH, ESP32S2_INT_PRIO_DEF, 0);
priv->cpuint = esp_setup_irq(SWI_PERIPH,
ESP32S2_INT_PRIO_DEF,
ESP_IRQ_TRIGGER_LEVEL,
esp_swi_irq,
NULL);
#elif CONFIG_ARCH_CHIP_ESP32S3
priv->cpuint = esp_setup_irq(0, SWI_PERIPH, ESP32S3_INT_PRIO_DEF, 0);
ASSERT(this_cpu() == 0);
priv->cpuint = esp_setup_irq(SWI_PERIPH,
ESP32S3_INT_PRIO_DEF,
ESP_IRQ_TRIGGER_LEVEL,
esp_swi_irq,
NULL);
#endif
if (priv->cpuint < 0)
{
@@ -1291,22 +1162,6 @@ int esp_wireless_init(void)
return ret;
}
ret = irq_attach(SWI_IRQ, esp_swi_irq, NULL);
if (ret < 0)
{
#ifdef CONFIG_ARCH_CHIP_ESP32
esp_teardown_irq(0, SWI_PERIPH, priv->cpuint);
#elif CONFIG_ARCH_CHIP_ESP32S2
esp_teardown_irq(SWI_PERIPH, priv->cpuint);
#elif CONFIG_ARCH_CHIP_ESP32S3
esp_teardown_irq(0, SWI_PERIPH, priv->cpuint);
#endif
leave_critical_section(flags);
wlerr("ERROR: Failed to attach IRQ ret=%d\n", ret);
return ret;
}
list_initialize(&priv->sc_list);
list_initialize(&priv->qc_list);
#ifdef CONFIG_ARCH_CHIP_ESP32
@@ -1349,14 +1204,7 @@ int esp_wireless_deinit(void)
if (priv->ref == 0)
{
up_disable_irq(SWI_IRQ);
irq_detach(SWI_IRQ);
#ifdef CONFIG_ARCH_CHIP_ESP32
esp_teardown_irq(0, SWI_PERIPH, priv->cpuint);
#elif CONFIG_ARCH_CHIP_ESP32S2
esp_teardown_irq(SWI_PERIPH, priv->cpuint);
#elif CONFIG_ARCH_CHIP_ESP32S3
esp_teardown_irq(0, SWI_PERIPH, priv->cpuint);
#endif
}
}
arch/xtensa/src/common/espressif/esp_wireless.h
+1 -9
View File
@@ -33,16 +33,8 @@
#include <nuttx/config.h>
#include <nuttx/list.h>
#ifdef CONFIG_ARCH_CHIP_ESP32
#include "xtensa_attr.h"
#include "esp32_rt_timer.h"
#elif CONFIG_ARCH_CHIP_ESP32S2
#include "esp_attr.h"
#include "esp32s2_rt_timer.h"
#elif CONFIG_ARCH_CHIP_ESP32S3
#include "esp_attr.h"
#include "esp32s3_rt_timer.h"
#endif
#include "esp_hr_timer.h"
#ifdef CONFIG_ESPRESSIF_WIFI
# include "os.h"
arch/xtensa/src/common/espressif/esp_wlan_netdev.c
+2 -2
View File
@@ -970,14 +970,14 @@ void IRAM_ATTR esp_wifi_tx_done_cb(uint8_t ifidx,
bool txstatus)
{
#ifdef ESP_WLAN_HAS_STA
if (ifidx == ESP_IF_WIFI_STA)
if (ifidx == WIFI_IF_STA)
{
netdev_lower_txdone(&g_wlan_sta.dev);
}
#endif
#ifdef ESP_WLAN_HAS_SOFTAP
if (ifidx == ESP_IF_WIFI_AP)
if (ifidx == WIFI_IF_AP)
{
netdev_lower_txdone(&g_wlan_softap.dev);
}
arch/xtensa/src/common/espressif/esp_ws2812.c
+28 -7
View File
@@ -35,6 +35,8 @@
#include "hal/rmt_types.h"
#include "soc/soc.h"
#include "esp_private/rmt.h"
#include "driver/rmt_common.h"
#include "esp_rmt.h"
@@ -67,6 +69,21 @@ struct rgbw_led_s
};
};
struct rmt_dev_lowerhalf_s
{
/* The following block is part of the upper-half device struct */
const struct rmt_ops_s *ops;
struct circbuf_s *circbuf;
sem_t *recvsem;
int minor;
/* The following is private to the ESP32 RMT driver */
rmt_channel_handle_t handle;
rmt_encoder_handle_t encoder;
};
struct esp_ws2812_dev_s
{
struct rmt_dev_s *rmt;
@@ -151,15 +168,19 @@ static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev,
uint16_t t0l;
uint16_t t1h;
uint16_t t1l;
uint32_t clock_period_ps;
uint32_t resolution_hz;
uint32_t rmt_period_ps;
esp_err_t ret;
struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev->rmt;
#if SOC_RMT_CHANNEL_CLK_INDEPENDENT
clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor];
#else
clock_period_ps = 1000000000000 / g_rmt_source_clock_hz;
#endif
rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV;
ret = rmt_get_channel_resolution(priv->handle, &resolution_hz);
if (ret != ESP_OK)
{
lederr("esp_ws2812 map_byte_to_words failed: %d\n", ret);
return 0;
}
rmt_period_ps = 1000000000000 / resolution_hz;
/* Calculate the RMT period to encode WS2812 frames */
arch/xtensa/src/common/espressif/esp_xtensa_intr.c
+153
View File
@@ -0,0 +1,153 @@
/****************************************************************************
* arch/xtensa/src/common/espressif/esp_xtensa_intr.c
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/kmalloc.h>
#include <arch/xtensa/xtensa_specregs.h>
#include "xtensa.h"
#include "esp_rom_sys.h"
#include "esp_attr.h"
#include "platform/os.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef XCHAL_NUM_INTERRUPTS
# define XCHAL_NUM_INTERRUPTS 32
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/* Handler table entry structure - must match HAL's xt_handler_table_entry */
typedef struct xt_handler_table_entry
{
void *handler;
void *arg;
} xt_handler_table_entry;
/****************************************************************************
* Public Data
****************************************************************************/
/* Interrupt handler table - exported as _xt_interrupt_table for HAL
* compatibility. The HAL's xtensa_intr.c expects this to be defined
* externally (originally in assembly).
*/
xt_handler_table_entry
_xt_interrupt_table[XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS];
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xt_ints_on
*
* Description:
* Enables a set of interrupts.
*
* Input Parameters:
* mask - Bit mask of interrupts to be enabled.
*
* Returned Value:
* None.
*
****************************************************************************/
void xt_ints_on(unsigned int mask)
{
uint32_t intenable;
__asm__ __volatile__("rsr %0, intenable" : "=r"(intenable));
intenable |= mask;
__asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable));
}
/****************************************************************************
* Name: xt_ints_off
*
* Description:
* Disables a set of interrupts.
*
* Input Parameters:
* mask - Bit mask of interrupts to be disabled.
*
* Returned Value:
* None.
*
****************************************************************************/
void xt_ints_off(unsigned int mask)
{
uint32_t intenable;
__asm__ __volatile__("rsr %0, intenable" : "=r"(intenable));
intenable &= ~mask;
__asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable));
}
/****************************************************************************
* Name: esp_xtensa_intr_init
*
* Description:
* Initialize the interrupt handler table by setting all handlers to the
* default unhandled interrupt handler (provided by HAL's xtensa_intr.c).
*
* Input Parameters:
* None.
*
* Returned Value:
* None.
*
****************************************************************************/
void esp_xtensa_intr_init(void)
{
int i;
for (i = 0; i < (XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS); i++)
{
/* Calling xt_set_interrupt_handler with f=NULL sets the handler
* to xt_unhandled_interrupt (defined in HAL's xtensa_intr.c)
*/
xt_set_interrupt_handler(i, NULL, (void *)(uintptr_t)i);
}
}
arch/xtensa/src/esp32/Kconfig
+19 -32
View File
@@ -196,9 +196,13 @@ config ESP32_XTAL_26MHz
endchoice # On-board Crystal Frequency
config ESP32_RT_TIMER
bool "Real-time Timer"
bool "Real-Time Timer"
default n
select ESP32_TIMER0
select ESPRESSIF_HR_TIMER
---help---
Deprecated: Use ESPRESSIF_HR_TIMER instead.
This option is kept for backward compatibility and automatically
selects the common ESPRESSIF_HR_TIMER configuration.
config ESP32_RUN_IRAM
bool "Run from IRAM"
@@ -336,7 +340,7 @@ config ESP32_I2S0
bool "I2S 0"
default n
select ARCH_DMA
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select ESPRESSIF_I2S0
if ESP32_I2S0
@@ -466,7 +470,7 @@ config ESP32_I2S1
bool "I2S 1"
default n
select ARCH_DMA
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select ESPRESSIF_I2S1
if ESP32_I2S1
@@ -618,7 +622,7 @@ config ESP32_SPI2
bool "SPI 2"
default n
select ESP32_SPI
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select SPI
select ESPRESSIF_SPI_PERIPH
@@ -626,7 +630,7 @@ config ESP32_SPI3
bool "SPI 3"
default n
select ESP32_SPI
select ESP32_GPIO_IRQ
select ESPRESSIF_GPIO_IRQ
select SPI
select ESPRESSIF_SPI_PERIPH
@@ -829,12 +833,16 @@ menu "Interrupt Configuration"
config ESP32_IRAM_ISR_DEBUG
bool "Enable debugging of the IRAM-enabled interrupts"
default n
select ESPRESSIF_IRAM_ISR_DEBUG
---help---
This option enables keeping track of the IRAM-enabled interrupts by
registering its execution when non-IRAM interrupts are disabled. It
keeps track of the IRQ executed and register how many times since
boot it was executed.
This option is kept for backwards compatibility and automatically
selects CONFIG_ESPRESSIF_IRAM_ISR_DEBUG.
endmenu # Interrupt Configuration
menu "Memory Configuration"
@@ -893,9 +901,11 @@ endmenu # Memory Configuration
config ESP32_GPIO_IRQ
bool "GPIO pin interrupts"
select ESPRESSIF_GPIO_IRQ
default n
---help---
Enable support for interrupting GPIO pins
This is a deprecated Kconfig macro. Its kept for retrocompatibility only.
Use "CONFIG_ESPRESSIF_GPIO_IRQ" instead.
config ESP32_RTCIO_IRQ
bool "RTC IO interrupts"
@@ -2204,26 +2214,6 @@ endif
endmenu # PHY
menu "Real-Time Timer"
depends on ESP32_RT_TIMER
config ESP32_RT_TIMER_TASK_NAME
string "Timer task name"
default "rt_timer"
config ESP32_RT_TIMER_TASK_PRIORITY
int "Timer task priority"
default 223
---help---
Priority level of the RT Timer task.
Must be lower than the SCHED_HPWORKPRIORITY.
config ESP32_RT_TIMER_TASK_STACK_SIZE
int "Timer task stack size"
default 2048
endmenu # Real-Time Timer
if ESP32_TIMER
menu "Timer/counter Configuration"
@@ -2879,12 +2869,9 @@ endmenu # Application Image Configuration
config ESP32_AUTO_SLEEP
bool "Auto-sleep"
default n
select PM
select ESP32_RT_TIMER
select ESP32_TIMER0
select ESP32_TICKLESS
select ESPRESSIF_AUTO_SLEEP
---help---
Enable ESP32 Auto-sleep
This is a deprecated option. Use ESPRESSIF_AUTO_SLEEP instead.
config ESP32_TICKLESS
bool "Enable ESP32 tickless OS"
arch/xtensa/src/esp32/Make.defs
+7 -22
View File
@@ -32,9 +32,9 @@ endif
# Required ESP32 files (arch/xtensa/src/esp32)
CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c
CHIP_CSRCS = esp32_allocateheap.c
CHIP_CSRCS += esp32_systemreset.c esp32_resetcause.c
CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_rtc_gpio.c
CHIP_CSRCS += esp32_region.c esp32_rtc_gpio.c
CHIP_CSRCS += esp32_user.c esp32_libc_stubs.c
CHIP_CSRCS += esp32_dma.c
@@ -55,13 +55,6 @@ else
CHIP_CSRCS += esp32_timerisr.c
endif
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp32_pminitialize.c
endif
CHIP_CSRCS += esp32_pm.c
endif
ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y)
CHIP_CSRCS += esp32_imm.c
endif
@@ -164,10 +157,6 @@ ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y)
CHIP_CSRCS += esp32_textheap.c
endif
ifeq ($(CONFIG_ESP32_RT_TIMER),y)
CHIP_CSRCS += esp32_rt_timer.c
endif
ifeq ($(CONFIG_ESP32_TOUCH),y)
CHIP_CSRCS += esp32_touch.c
endif
@@ -184,13 +173,6 @@ ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y)
CHIP_CSRCS += esp32_crypto.c
endif
ifeq ($(CONFIG_ESP32_RTC),y)
CHIP_CSRCS += esp32_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32_rtc_lowerhalf.c
endif
endif
ifeq ($(CONFIG_ESP32_OPENETH),y)
CHIP_CSRCS += esp_openeth.c
endif
@@ -212,7 +194,7 @@ endif
ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty
ifndef ESP_HAL_3RDPARTY_VERSION
ESP_HAL_3RDPARTY_VERSION = b9472bd56b916cced7447e25c2b2e1390d7e0d90
ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7
endif
ifndef ESP_HAL_3RDPARTY_URL
@@ -252,13 +234,16 @@ chip/$(ESP_HAL_3RDPARTY_REPO):
$(Q) echo "Cloning Espressif HAL for 3rd Party Platforms"
$(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO)
ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y)
$(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..."
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true
$(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}"
$(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION)
endif
# Silent preprocessor warnings
CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion
CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations
# Enable strict volatile bitfield access
arch/xtensa/src/esp32/chip.h
+3 -3
View File
@@ -32,7 +32,7 @@
#if defined(CONFIG_ESP32_OPENETH) && !defined(__ASSEMBLY__)
#include "hardware/esp32_soc.h"
#include "esp32_irq.h"
#include "esp_irq.h"
#endif
/****************************************************************************
@@ -41,9 +41,9 @@
#if defined(CONFIG_ESP32_OPENETH)
#define OPENETH_PERIPH_MAC ESP32_PERIPH_EMAC
#define OPENETH_CPUINT_LEVEL ESP32_CPUINT_LEVEL
#define OPENETH_CPUINT_LEVEL ESP_IRQ_TRIGGER_LEVEL
#define OPENETH_IRQ_MAC ESP32_IRQ_EMAC
#define OPENETH_SETUP_IRQ esp32_setup_irq
#define OPENETH_SETUP_IRQ esp_setup_irq
#define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM
#endif
arch/xtensa/src/esp32/esp32_ble_adapter.c
+80 -126
View File
@@ -52,12 +52,12 @@
#include "hardware/esp32_dport.h"
#include "hardware/wdev_reg.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "utils/memory_reserve.h"
#include "esp32_rt_timer.h"
#include "esp_hr_timer.h"
#include "espressif/esp_wireless.h"
#include "espressif/esp_wifi_utils.h"
#include "esp32_irq.h"
#include "esp_irq.h"
#include "esp_bt.h"
#include "esp_log.h"
@@ -128,12 +128,6 @@
# define BLE_TASK_EVENT_QUEUE_LEN 8
#endif
#ifdef CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS
# define NR_IRQSTATE_FLAGS CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS
#else
# define NR_IRQSTATE_FLAGS 3
#endif
#define RTC_CLK_CAL_FRACT 19 /* Number of fractional bits in values returned by rtc_clk_cal */
/****************************************************************************
@@ -297,10 +291,31 @@ struct irqstate_list_s
irqstate_t flags;
};
typedef struct shared_vector_desc_t shared_vector_desc_t;
typedef struct vector_desc_t vector_desc_t;
typedef struct intr_handle_data_t
{
vector_desc_t *vector_desc;
shared_vector_desc_t *shared_vector_desc;
} intr_handle_data_t;
struct vector_desc_t
{
int flags: 16;
unsigned int cpu: 1;
unsigned int intno: 5;
int source: 16;
shared_vector_desc_t *shared_vec_info;
vector_desc_t *next;
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
extern vector_desc_t *get_desc_for_int(int intno, int cpu);
/****************************************************************************
* Functions to be registered to struct osi_funcs_s
****************************************************************************/
@@ -313,7 +328,6 @@ struct irqstate_list_s
*/
static xt_handler ble_set_isr(int n, xt_handler f, void *arg);
static void ints_on(unsigned int mask);
static void IRAM_ATTR interrupt_disable(void);
static void IRAM_ATTR interrupt_restore(void);
static void IRAM_ATTR task_yield_from_isr(void);
@@ -409,7 +423,6 @@ static void IRAM_ATTR cause_sw_intr(void *arg);
static void btdm_slp_tmr_customer_callback(void * arg);
static void IRAM_ATTR btdm_slp_tmr_callback(void *arg);
#endif
static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg);
static void btdm_wakeup_request_callback(void * arg);
static void btdm_controller_mem_init(void);
static uint32_t btdm_config_mask_load(void);
@@ -507,7 +520,7 @@ static struct osi_funcs_s g_osi_funcs_ro =
{
._version = OSI_VERSION,
._set_isr = ble_set_isr,
._ints_on = ints_on,
._ints_on = xt_ints_on,
._interrupt_disable = interrupt_disable,
._interrupt_restore = interrupt_restore,
._task_yield = task_yield_from_isr,
@@ -683,11 +696,9 @@ static DRAM_ATTR bool g_btdm_allow_light_sleep;
/* BT interrupt private data */
static sq_queue_t g_ble_int_flags_free;
irqstate_t g_ble_int_flags;
static sq_queue_t g_ble_int_flags_used;
static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS];
static int g_ble_int_count = 0;
/* Cached queue control variables */
@@ -827,75 +838,55 @@ static inline void btdm_check_and_init_bb(void)
static xt_handler ble_set_isr(int n, xt_handler f, void *arg)
{
int ret;
uint32_t tmp;
struct irq_adpt_s *adapter;
int irq = esp32_getirq(0, n);
wlinfo("n=%d f=%p arg=%p irq=%d\n", n, f, arg, irq);
if (g_irqvector[irq].handler &&
g_irqvector[irq].handler != irq_unexpected_isr)
{
wlinfo("irq=%d has been set handler=%p\n", irq,
g_irqvector[irq].handler);
return NULL;
}
tmp = sizeof(struct irq_adpt_s);
adapter = kmm_malloc(tmp);
if (!adapter)
{
wlerr("Failed to alloc %" PRIu32 " memory\n", tmp);
DEBUGPANIC();
return NULL;
}
adapter->func = f;
adapter->arg = arg;
ret = irq_attach(irq, esp_int_adpt_cb, adapter);
if (ret)
{
wlerr("Failed to attach IRQ %d\n", irq);
DEBUGPANIC();
return NULL;
}
return NULL;
}
/****************************************************************************
* Name: ints_on
*
* Description:
* Enable BLE interrupt
*
* Input Parameters:
* mask - Mask used to indicate the bits to enable interrupt.
*
* Returned Value:
* None
*
****************************************************************************/
static void ints_on(unsigned int mask)
{
uint32_t bit;
intr_handle_t handle;
int irq;
for (int i = 0; i < 32; i++)
switch (n)
{
bit = 1 << i;
if (bit & mask)
case 5:
{
irq = esp32_getirq(0, i);
DEBUGVERIFY(esp32_irq_set_iram_isr(irq));
up_enable_irq(irq);
wlinfo("Enabled bit %d\n", irq);
irq = ESP_SOURCE2IRQ(ETS_RWBT_INTR_SOURCE);
}
break;
case 7:
{
irq = ETS_INTERNAL_SW0_INTR_SOURCE + \
ETS_INTERNAL_INTR_SOURCE_OFF;
}
break;
case 8:
{
irq = ESP_SOURCE2IRQ(ETS_BT_BB_INTR_SOURCE);
}
break;
default:
{
wlerr("ERROR: Invalid interrupt number %d\n", n);
return NULL;
}
}
UNUSED(irq);
wlinfo("n=%d f=%p arg=%p irq=%d\n", n, f, arg, irq);
handle = kmm_calloc(1, sizeof(intr_handle_data_t));
if (handle == NULL)
{
wlerr("Failed to kmm_calloc\n");
return NULL;
}
handle->vector_desc = get_desc_for_int(n, this_cpu());
/* Register the handle - it contains all needed information (cpuint, cpu) */
esp_set_handle(this_cpu(), irq, handle);
xt_set_interrupt_handler(n, (xt_handler)f, arg);
return NULL;
}
/****************************************************************************
@@ -917,13 +908,12 @@ static void IRAM_ATTR interrupt_disable(void)
{
struct irqstate_list_s *irqstate;
irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free);
if (g_ble_int_count == 0)
{
g_ble_int_flags = enter_critical_section();
}
ASSERT(irqstate != NULL);
irqstate->flags = enter_critical_section();
sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used);
g_ble_int_count++;
}
/****************************************************************************
@@ -945,13 +935,12 @@ static void IRAM_ATTR interrupt_restore(void)
{
struct irqstate_list_s *irqstate;
irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used);
g_ble_int_count--;
ASSERT(irqstate != NULL);
leave_critical_section(irqstate->flags);
sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free);
if (g_ble_int_count == 0)
{
leave_critical_section(g_ble_int_flags);
}
}
/****************************************************************************
@@ -2567,31 +2556,6 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg)
}
#endif
/****************************************************************************
* Name: esp_int_adpt_cb
*
* Description:
* BT interrupt adapter callback function
*
* Input Parameters:
* irq - Number of the IRQ that generated the interrupt
* context - Interrupt register state save info (not used)
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* OK
*
****************************************************************************/
static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg)
{
struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg;
adapter->func(adapter->arg);
return OK;
}
/****************************************************************************
* Name: btdm_wakeup_request_callback
*
@@ -2905,17 +2869,7 @@ int esp32_bt_controller_init(void)
return -EIO;
}
/* Initialize list of interrupt flags to enable chained critical sections
* to return successfully.
*/
sq_init(&g_ble_int_flags_free);
sq_init(&g_ble_int_flags_used);
for (i = 0; i < NR_IRQSTATE_FLAGS; i++)
{
sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free);
}
g_ble_int_count = 0;
#ifdef CONFIG_ESPRESSIF_SPIFLASH

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