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arch/xtensa: register Wi-Fi IRQs in non_iram mask for SPI flash
Wi-Fi used a locally allocated vector_desc, so those CPU interrupt lines were never recorded in the HAL non_iram_int_mask. During SPI flash, esp_intr_noniram_disable() therefore did not mask them, and Wi-Fi ISRs could still run with the cache off. Now, Wi-Fi IRQs are treated as non-IRAM and get masked while flash/cache is suspended. Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
This commit is contained in:
committed by
Xiang Xiao
parent
e8bcbbc5d3
commit
8fb8c2dca5
@@ -49,6 +49,7 @@
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#include "esp32_wifi_adapter.h"
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#include "esp_hr_timer.h"
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#include "esp_irq.h"
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#include "esp_intr_alloc.h"
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#include "esp_cpu.h"
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#include "espressif/esp_wireless.h"
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#include "espressif/esp_wifi_utils.h"
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@@ -1752,7 +1753,9 @@ static bool wifi_env_is_chip(void)
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* Name: set_intr_wrapper
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*
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* Description:
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* Do nothing
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* Route the Wi-Fi interrupt source and attach a handle that uses the HAL
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* global vector descriptor list. Mark the CPU line as non-IRAM so
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* esp_intr_noniram_disable() masks it while SPI flash holds the cache off.
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*
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* Input Parameters:
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* cpu_no - The CPU which the interrupt number belongs.
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@@ -1770,6 +1773,7 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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{
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intr_handle_t handle;
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int irq = ESP_SOURCE2IRQ(intr_source);
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esp_err_t err;
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wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32
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", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n",
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@@ -1785,11 +1789,25 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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}
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handle->vector_desc = get_desc_for_int(intr_num, cpu_no);
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if (handle->vector_desc == NULL)
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{
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wlerr("get_desc_for_int failed\n");
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kmm_free(handle);
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return;
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}
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handle->vector_desc->source = intr_source;
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handle->shared_vector_desc = NULL;
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/* Register the handle - it contains all needed information (cpuint, cpu) */
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esp_set_handle(cpu_no, irq, handle);
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err = esp_intr_set_in_iram(handle, false);
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if (err != OK)
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{
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wlerr("esp_intr_set_in_iram failed: %d\n", err);
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}
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}
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/****************************************************************************
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@@ -44,6 +44,7 @@
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#include "xtensa.h"
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#include "esp_attr.h"
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#include "esp_irq.h"
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#include "esp_intr_alloc.h"
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#include "esp_cpu.h"
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#include "hardware/esp32s2_system.h"
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#include "soc/rtc_cntl_reg.h"
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@@ -95,6 +96,12 @@ struct vector_desc_t
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vector_desc_t *next;
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};
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/* From esp_hw_support/intr_alloc.c: returns a pointer to a HAL-owned
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* vector descriptor for some intno and cpu.
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*/
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extern vector_desc_t *get_desc_for_int(int intno, int cpu);
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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@@ -1604,7 +1611,9 @@ static bool wifi_env_is_chip(void)
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* Name: set_intr_wrapper
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*
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* Description:
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* Do nothing
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* Route the Wi-Fi interrupt source and attach a handle that uses the HAL
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* global vector descriptor list. Mark the CPU line as non-IRAM so
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* esp_intr_noniram_disable() masks it while SPI flash holds the cache off.
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*
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* Input Parameters:
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* cpu_no - The CPU which the interrupt number belongs.
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@@ -1622,6 +1631,7 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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{
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intr_handle_t handle;
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int irq = ESP_SOURCE2IRQ(intr_source);
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esp_err_t err;
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wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32
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", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n",
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@@ -1636,24 +1646,26 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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return;
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}
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handle->vector_desc = kmm_calloc(1, sizeof(vector_desc_t));
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handle->vector_desc = get_desc_for_int(intr_num, cpu_no);
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if (handle->vector_desc == NULL)
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{
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wlerr("Failed to kmm_calloc\n");
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wlerr("get_desc_for_int failed\n");
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kmm_free(handle);
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return;
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}
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handle->vector_desc->intno = intr_num;
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handle->vector_desc->cpu = cpu_no;
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handle->vector_desc->source = intr_source;
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handle->vector_desc->shared_vec_info = NULL;
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handle->vector_desc->next = NULL;
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handle->shared_vector_desc = NULL;
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/* Register the handle - it contains all needed information (cpuint, cpu) */
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esp_set_handle(cpu_no, irq, handle);
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err = esp_intr_set_in_iram(handle, false);
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if (err != OK)
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{
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wlerr("esp_intr_set_in_iram failed: %d\n", err);
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}
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}
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/****************************************************************************
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@@ -44,6 +44,7 @@
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#include "xtensa.h"
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#include "esp_attr.h"
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#include "esp_irq.h"
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#include "esp_intr_alloc.h"
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#include "esp_cpu.h"
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#include "hardware/esp32s3_system.h"
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#include "soc/rtc_cntl_reg.h"
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@@ -267,6 +268,10 @@ static int coex_schm_flexible_period_set_wrapper(uint8_t period);
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static uint8_t coex_schm_flexible_period_get_wrapper(void);
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static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx);
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/* From esp_hw_support/intr_alloc.c: returns a pointer to a HAL-owned
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* vector descriptor for some intno and cpu.
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*/
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extern vector_desc_t *get_desc_for_int(int intno, int cpu);
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/****************************************************************************
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@@ -1738,7 +1743,9 @@ static bool wifi_env_is_chip(void)
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* Name: set_intr_wrapper
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*
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* Description:
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* Do nothing
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* Route the Wi-Fi interrupt source and attach a handle that uses the HAL
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* global vector descriptor list. Mark the CPU line as non-IRAM so
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* esp_intr_noniram_disable() masks it while SPI flash holds the cache off.
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*
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* Input Parameters:
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* cpu_no - The CPU which the interrupt number belongs.
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@@ -1756,6 +1763,7 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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{
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intr_handle_t handle;
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int irq = ESP_SOURCE2IRQ(intr_source);
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esp_err_t err;
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wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32
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", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n",
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@@ -1771,12 +1779,25 @@ static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source,
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}
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handle->vector_desc = get_desc_for_int(intr_num, cpu_no);
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if (handle->vector_desc == NULL)
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{
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wlerr("get_desc_for_int failed\n");
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kmm_free(handle);
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return;
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}
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handle->vector_desc->source = intr_source;
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handle->shared_vector_desc = NULL;
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/* Register the handle - it contains all needed information (cpuint, cpu) */
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esp_set_handle(cpu_no, irq, handle);
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err = esp_intr_set_in_iram(handle, false);
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if (err != OK)
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{
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wlerr("esp_intr_set_in_iram failed: %d\n", err);
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}
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}
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/****************************************************************************
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