* NuttX supports ESP32-P4 >= v3.0 by default.
* In order to run on older chips configuration tuning is required.
* Without configutation tune boot loop happens on older chips.
* Added note on WaveShare ESP32-P4-Nano board that is almost identical
to existing ESP32-P4-Function-EV-Board board, so configs are compatible,
but it has v1.3 chip, thus config tune is required as documented above.
* Added cross-file reference label to esp32p4-function-ev-board.
Signed-off-by: Tomasz 'CeDeROM' CEDRO <tomek@cedro.info>
This commit describes ethernet support on ESP32-P4 SoC and its
ESP32-P4-Function-EV-Board v1.5.2.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Adds a configuration that combines the `nimble` example with a SMARTFS
file system configured in the chip's flash.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Updated the `rmt` defconfig description for the Espressif's SoCs.
Use the `irtest` testing app (instead of the deprecated `rmtchar`)
to test the RMT peripheral.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
This commit adds an entry for the ESP32-P4-Function-EV-Board's
`psram_usrheap` defconfig on docs.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Document the new mkpasswd-based password generation system and its
integration with the build process.
Changes:
* Add comprehensive mkpasswd tool documentation to components/tools
* Update SIM board docs to explain generated passwd workflow
* Update ESP32-C3-legacy board docs for passwd generation
* Update RX65N board docs with credential handling guidance
* Document how to configure and use BOARD_ETC_ROMFS_PASSWD_* options
* Explain security benefits of build-time generation vs static files
* Update all doc examples from default username "admin" to "root"
BREAKING CHANGE: Boards using static /etc/passwd files in ETC_ROMFS
must migrate to the new build-time generation workflow documented in
Documentation/components/tools/index.rst. The old static passwd files
are no longer present in migrated boards; boards that relied on them
will fail to build until credentials are configured via Kconfig.
Signed-off-by: Abhishek Mishra <mishra.abhishek2808@gmail.com>
This commit documents the power management defconfig for the
ESP32-P4-Function-EV-Board.
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Remove the CONFIG_K210_WITH_QEMU option and associated conditional
code paths. The reasons for removal are:
* Simplifies code path for real hardware by removing QEMU workarounds
* The current QEMU target uses sifive_u machine, which is not designed
for K210 emulation
* For RISC-V QEMU simulation, the qemu-rv (rv-virt) target is a better
choice
* Renode can be used as an alternative for K210 simulation if needed
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add WDT driver for K210 with support for both WDT0 and WDT1 peripherals.
This includes:
- Add k210_wdt.c and k210_wdt.h driver files with interrupt-based
watchdog timer functionality
- Add hardware register definitions in k210_wdt.h
- Add K210_WDT, K210_WDT0, K210_WDT1 Kconfig options
- Add memory map definitions for WDT0 (0x50400000) and WDT1 (0x50410000)
- Reorder WDT IRQ definitions (IRQ 21, 22) before UART0 (IRQ 33) in irq.h
- Add WDT initialization in board bringup for maix-bit
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Add sysctl driver for K210 SoC providing clock and reset control:
- Clock enable/disable with two-stage APB/peripheral enable pattern
- Peripheral reset control with proper timing
- Clock frequency query for PLL, CPU, APB buses, and peripherals
- PLL frequency calculation and CPU frequency configuration
The sysctl driver is built unconditionally for K210 boards as it
provides essential clock and reset control functionality.
Add Kconfig option:
- K210_CPU_FREQ: Target CPU frequency in Hz (default 400MHz)
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit adds documentation entries for ESP32-P4 chip and its
board (ESP32-P4 Function-EV-Board).
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Documentation mentioned xiao-esp32c3 which is incorrect. The actual board name in the codebase is esp32c3-xiao. This commit fixes the board name in the documentation to match the directory structure.
Add new RISC-V 64-bit QEMU configuration with:
- 64-bit RISC-V (RV64) architecture support
- RISC-V Vector Extension (RVV/V-extension) enabled
- LVGL graphics framework integration
- VirtIO GPU and input device support
- NSH shell with built-in applications
This configuration enables developers to build and test LVGL graphical
applications on 64-bit RISC-V targets with Vector extension support,
providing a foundation for future SIMD optimization work.
Includes:
- defconfig: Complete configuration file with all necessary options
- Updated index.rst: Build and run instructions with QEMU launch command
Signed-off-by: rongyichang <rongyichang@xiaomi.com>
The secure CPU variant of vexriscv immediately panics after bring up.
However, the linux CPU variant of the vexriscv core does work successfully.
Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>
Updates the docs to the new esp32c3-devkit naming, after deprecating support
for now esp32c3-legacy.
Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
Migrated legacy README.txt documentation to RST format which aligns with
the standard template for board documentation.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
Migrated legacy README.txt documentation to RST format following the
standard board documentation template.
Signed-off-by: Matteo Golin <matteo.golin@gmail.com>
This commit adds an entry on Documentation regarding ESP32-C3,
ESP32-C6 and ESP32-H2 boards that implement the `buttons` defconfig
Signed-off-by: Tiago Medicci Serrano <tiago.medicci@espressif.com>
Tiago Medicci Serrano
Eren Terzioglu
Tomasz 'CeDeROM' CEDRO
Matteo Golin
Filipe Cavalcanti
Daniel Monteiro
Abhishek Mishra
simbit18
Huang Qi
aviralgarg05
rongyichang
Justin Erenkrantz
haitomatic