risc-v/litex: For vexriscv, point docs at linux CPU variant instead of secure.

The secure CPU variant of vexriscv immediately panics after bring up.

However, the linux CPU variant of the vexriscv core does work successfully.

Signed-off-by: Justin Erenkrantz <justin@erenkrantz.com>

Documentation/platforms/risc-v/litex/boards/arty_a7/README.txt

@@ -6,7 +6,7 @@
    and flash to arty_a7 board
 
   $ cd litex-boards/litex_boards/targets
-  $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=secure --build --load --flash
+  $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=linux --build --load --flash
 
 3. Configure and build NuttX
 

Documentation/platforms/risc-v/litex/boards/arty_a7/index.rst

@@ -72,7 +72,7 @@ Flashing
 .. code:: console
 
    $ cd litex-boards/litex_boards/targets
-   $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=secure --build --load --flash
+   $ ./digilent_arty.py --with-ethernet --with-sdcard --uart-baudrate 1000000 --cpu-type=vexriscv --cpu-variant=linux --build --load --flash
 
 
 2. Next, set up a TFTP server on your host machine, copy ``nuttx.bin`` to your

Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst

@@ -4,6 +4,15 @@ Vexriscv Core
 
 The vexriscv core only supports standard "Flat builds", consisting of a single binary.
 
+Configuration
+-------------
+
+For vexriscv, the linux CPU variant is required.  Please consult the appropriate board
+documentation for flashing gateware.
+
+If you use the secure CPU variant, you may encounter a kernel panic on startup - please see
+https://github.com/apache/nuttx/pull/17494 for an example.
+
 Building
 --------