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arch/risc-v/mpfs: Add MSS CAN driver.
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Refactor to  become lower half driver.

Signed-off-by: Hai To <hai.to@tii.ae>
This commit is contained in:
haitomatic
2025-10-17 06:09:40 +00:00
committed by Alan C. Assis
parent 967238ba2c
commit e7ad870f18
3 changed files with 355 additions and 746 deletions
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1
Documentation/platforms/risc-v/mpfs/boards/icicle/index.rst
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@@ -84,6 +84,7 @@ The following peripherals are configured:
- UART0-4
- CorePWM (nb. needs the FPGA IP installed to work)
- CoreSPI (nb. needs the FPGA IP installed to work)
- CAN0 & CAN1 (work with flat mode but there is still rare frame corruption issue in protected mode)
The following applications are available:
- TelnetD (at address 10.0.0.2)

1099
arch/risc-v/src/mpfs/mpfs_can.c
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File diff suppressed because it is too large Load Diff

1
boards/risc-v/mpfs/icicle/configs/hwtest/defconfig
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@@ -79,7 +79,6 @@ CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NETINIT_NOMAC=y
CONFIG_NETUTILS_TELNETC=y
CONFIG_NETUTILS_TELNETD=y
CONFIG_NET_CAN=y
CONFIG_NET_ETH_PKTSIZE=1478
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_IGMP=y