* Add BananaPi BPI-F3 BSP support
Add RISC-V supervisor support to the rv64/gnu port and
provide a complete board support package for the BananaPi BPI-F3
(SpacemiT K1 SoC, X60 cores).
Port changes (risc-v64/gnu):
- Guard all CSR accesses with TX_RISCV_SMODE to select S-mode registers
(sstatus/sepc/sie/sret) vs M-mode (mstatus/mepc/mie/mret) in
context_save, context_restore, schedule, system_return,
interrupt_control, and stack_build.
- Add S-mode TX_INT_ENABLE/TX_DISABLE and inline TX_RESTORE macros
to tx_port.h.
- Add TX_RISCV_SMODE CMake option to CMakeLists.txt.
BananaPi BPI-F3 BSP (example_build/bananapi-f3):
- Boot flow: FSBL → OpenSBI (M-mode) → U-Boot (S-mode) → ThreadX
- S-mode trap handler with context save/restore integration
- SBI legacy ecall timer at 10 Hz (24 MHz timebase)
- PLIC driver with S-mode context, stale-IRQ drain, and callbacks
- PXA-compatible UART0 console (115200 8N1)
- Linker script at 0x200000 load address
Tested on risc-v board, BananaPi BPI-F3 hardware.
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
* Fixed S-mode context restore and PLIC spurious IRQ handling
- tx_thread_context_restore.S (non-nested path): set SPIE(0x20) alongside
SPP(0x100) so sret re-enables interrupts in the restored thread.
- tx_thread_context_restore.S (both S-mode paths): use FS=Dirty (0x6000)
instead of FS=Initial (0x2000) to match tx_thread_schedule.S and prevent
FP register corruption across context switches.
- plic.c (plic_irq_intr): return early when plic_claim() yields 0 (no
pending interrupt) to avoid completing a spurious IRQ ID 0, which is
undefined behavior per the PLIC spec.
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
---------
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
Co-authored-by: Frédéric Desbiens <frederic.desbiens@eclipse-foundation.org>
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
This update adapts the ThreadX low-level kernel routines
for RV32, including:
- startup and initialization logic
- context save/restore implementations
- interrupt control and scheduler entry
- thread stack build and system return paths
- timer interrupt handling
- made it complient as per new risc-v64/gnu
& threadx style
- added reademe for risc-v32/gnu port
These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
This update adapts the ThreadX low-level kernel routines
for RV32, including:
- startup and initialization logic
- context save/restore implementations
- interrupt control and scheduler entry
- thread stack build and system return paths
- timer interrupt handling
- made it complient as per new risc-v64/gnu
& threadx style
- added reademe for risc-v32/gnu port
These changes provide full low-level support needed to run
ThreadX on RISC-V32 targets.
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
This commit introduces the complete example build environment for the
RISC-V32/GNU port targeting the QEMU virt machine. It includes basic BSP
components, startup code, drivers, linker script, and a minimal ThreadX
demo application.
Signed-off-by: Akif Ejaz <akif.ejaz@10xengineers.ai>
