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[n32] 增加多个BSP支持 (#6543)

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add bsp n32g43xcl-stb,n32g45xcl-stb,n32g45xml-stb,n32g45xrl-stb,n32g457qel-stb,n32l40xcl-stb,n32l43xml-stb,n32l43xrl-stb,n32l436_evb,n32wb45xl-evb
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NationsHuanghanbin
2022-10-20 09:40:14 +08:00
committed by GitHub
parent 88179b75a1
commit afe6c0386d
815 changed files with 415374 additions and 3717 deletions
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_common_tables.h
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_const_structs.h
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/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/arm_math.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armcc.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_armclang.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_compiler.h
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_gcc.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_iccarm.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/cmsis_version.h
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/core_cm4.h
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/core/mpu_armv7.h
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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x.h
+7744
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_conf.h
+84
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_conf.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_CONF_H__
#define __N32G43X_CONF_H__
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
#include "n32g43x_adc.h"
#include "n32g43x_can.h"
#include "n32g43x_comp.h"
#include "n32g43x_crc.h"
#include "n32g43x_dac.h"
#include "n32g43x_dbg.h"
#include "n32g43x_dma.h"
#include "n32g43x_exti.h"
#include "n32g43x_flash.h"
#include "n32g43x_gpio.h"
#include "n32g43x_i2c.h"
#include "n32g43x_iwdg.h"
#include "n32g43x_opamp.h"
#include "n32g43x_pwr.h"
#include "n32g43x_rcc.h"
#include "n32g43x_rtc.h"
#include "n32g43x_spi.h"
#include "n32g43x_tim.h"
#include "n32g43x_usart.h"
#include "n32g43x_lpuart.h"
#include "n32g43x_wwdg.h"
#include "n32g43x_tsc.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT 1 */
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function which reports
* the name of the source file and the source line number of the call
* that failed. If expr is true, it returns no value.
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((const uint8_t*)#expr, (const uint8_t*)__FILE__, __LINE__))
void assert_failed(const uint8_t* expr, const uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* __N32G43X_CONF_H__ */
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/n32g43x_flash.ld
+182
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/**
****************************************************************************
Copyright (c) 2019, Nations Technologies Inc.
All rights reserved.
****************************************************************************
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the disclaimer below.
Nations' name may not be used to endorse or promote products derived from
this software without specific prior written permission.
DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
**/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20008000; /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x800; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(4);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(4);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x.s
+371
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; ****************************************************************************
; Copyright (c) 2019, Nations Technologies Inc.
;
; All rights reserved.
; ****************************************************************************
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; - Redistributions of source code must retain the above copyright notice,
; this list of conditions and the disclaimer below.
;
; Nations' name may not be used to endorse or promote products derived from
; this software without specific prior written permission.
;
; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
; DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; ****************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001500
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000300
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; RTC Tamper interrupt or Timestamp through EXTI line 19 interrupt
DCD RTC_WKUP_IRQHandler ; RTC_WKUP
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA_Channel1_IRQHandler ; DMA Channel 1
DCD DMA_Channel2_IRQHandler ; DMA Channel 2
DCD DMA_Channel3_IRQHandler ; DMA Channel 3
DCD DMA_Channel4_IRQHandler ; DMA Channel 4
DCD DMA_Channel5_IRQHandler ; DMA Channel 5
DCD DMA_Channel6_IRQHandler ; DMA Channel 6
DCD DMA_Channel7_IRQHandler ; DMA Channel 7
DCD DMA_Channel8_IRQHandler ; DMA Channel 8
DCD ADC_IRQHandler ; ADC
DCD USB_HP_IRQHandler ; USB High Priority
DCD USB_LP_IRQHandler ; USB Low Priority
DCD COMP_1_2_IRQHandler ; COMP1 & COMP2 through EXTI line 21/22
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD LPUART_IRQHandler ; LPUART
DCD TIM5_IRQHandler ; TIM5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD CAN_TX_IRQHandler ; CAN TX
DCD CAN_RX0_IRQHandler ; CAN RX0
DCD CAN_RX1_IRQHandler ; CAN RX1
DCD CAN_SCE_IRQHandler ; CAN SCE
DCD LPUART_WKUP_IRQHandler ; LPUART_WKUP
DCD LPTIM_WKUP_IRQHandler ; LPTIM_WKUP
DCD 0 ; Reserved
DCD SAC_IRQHandler ; SAC
DCD MMU_IRQHandler ; MMU
DCD TSC_IRQHandler ; TSC
DCD RAMC_PERR_IRQHandler ; RAMC ERR
DCD TIM9_IRQHandler ; TIM9
DCD UCDR_IRQHandler ; UCDR ERR
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA_Channel1_IRQHandler [WEAK]
EXPORT DMA_Channel2_IRQHandler [WEAK]
EXPORT DMA_Channel3_IRQHandler [WEAK]
EXPORT DMA_Channel4_IRQHandler [WEAK]
EXPORT DMA_Channel5_IRQHandler [WEAK]
EXPORT DMA_Channel6_IRQHandler [WEAK]
EXPORT DMA_Channel7_IRQHandler [WEAK]
EXPORT DMA_Channel8_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT USB_HP_IRQHandler [WEAK]
EXPORT USB_LP_IRQHandler [WEAK]
EXPORT COMP_1_2_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT LPUART_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT CAN_TX_IRQHandler [WEAK]
EXPORT CAN_RX0_IRQHandler [WEAK]
EXPORT CAN_RX1_IRQHandler [WEAK]
EXPORT CAN_SCE_IRQHandler [WEAK]
EXPORT LPUART_WKUP_IRQHandler [WEAK]
EXPORT LPTIM_WKUP_IRQHandler [WEAK]
EXPORT SAC_IRQHandler [WEAK]
EXPORT MMU_IRQHandler [WEAK]
EXPORT TSC_IRQHandler [WEAK]
EXPORT RAMC_PERR_IRQHandler [WEAK]
EXPORT TIM9_IRQHandler [WEAK]
EXPORT UCDR_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA_Channel1_IRQHandler
DMA_Channel2_IRQHandler
DMA_Channel3_IRQHandler
DMA_Channel4_IRQHandler
DMA_Channel5_IRQHandler
DMA_Channel6_IRQHandler
DMA_Channel7_IRQHandler
DMA_Channel8_IRQHandler
ADC_IRQHandler
USB_HP_IRQHandler
USB_LP_IRQHandler
COMP_1_2_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
LPUART_IRQHandler
TIM5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
CAN_TX_IRQHandler
CAN_RX0_IRQHandler
CAN_RX1_IRQHandler
CAN_SCE_IRQHandler
LPUART_WKUP_IRQHandler
LPTIM_WKUP_IRQHandler
SAC_IRQHandler
MMU_IRQHandler
TSC_IRQHandler
RAMC_PERR_IRQHandler
TIM9_IRQHandler
UCDR_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_EWARM.s
+523
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bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/startup/startup_n32g43x_gcc.s
+450
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@@ -0,0 +1,450 @@
/**
****************************************************************************
Copyright (c) 2019, Nations Technologies Inc.
All rights reserved.
****************************************************************************
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice,
this list of conditions and the disclaimer below.
Nations' name may not be used to endorse or promote products derived from
this software without specific prior written permission.
DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
****************************************************************************
**/
/**
******************************************************************************
* @file startup_n32g43x_gcc.s
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl entry
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detection */
.word TAMPER_IRQHandler /* Tamper */
.word RTC_WKUP_IRQHandler /* RTC Wakeup */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA_Channel5_IRQHandler /* DMA1 Channel 5 */
.word DMA_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA_Channel7_IRQHandler /* DMA1 Channel 7 */
.word DMA_Channel8_IRQHandler /* DMA1 Channel 8 */
.word ADC_IRQHandler /* ADC */
.word USB_HP_IRQHandler /* USB High Priority */
.word USB_LP_IRQHandler /* USB Low Priority */
.word COMP_1_2_IRQHandler /* COMP1 & COMP2 through EXTI line 21/22 */
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.word TIM1_BRK_IRQHandler /* TIM1 Break */
.word TIM1_UP_IRQHandler /* TIM1 Update */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.word TIM8_BRK_IRQHandler /* TIM8 Break */
.word TIM8_UP_IRQHandler /* TIM8 Update */
.word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word LPUART_IRQHandler /* LPUART */
.word TIM5_IRQHandler /* TIM5 */
.word TIM6_IRQHandler /* TIM6 */
.word TIM7_IRQHandler /* TIM7 */
.word CAN_TX_IRQHandler /* CAN TX */
.word CAN_RX0_IRQHandler /* CAN RX0 */
.word CAN_RX1_IRQHandler /* CAN RX1 */
.word CAN_SCE_IRQHandler /* CAN SCE */
.word LPUART_WKUP_IRQHandler /* LPUART_WKUP */
.word LPTIM_WKUP_IRQHandler /* LPTIM_WKUP */
.word LCD_IRQHandler /* LCD */
.word SAC_IRQHandler /* SAC */
.word MMU_IRQHandler /* MMU */
.word TSC_IRQHandler /* TSC */
.word RAMC_PERR_IRQHandler /* RAMC ERR */
.word TIM9_IRQHandler /* TIM9 */
.word UCDR_IRQHandler /* UCDR ERR */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak TAMPER_IRQHandler
.thumb_set TAMPER_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA_Channel1_IRQHandler
.thumb_set DMA_Channel1_IRQHandler,Default_Handler
.weak DMA_Channel2_IRQHandler
.thumb_set DMA_Channel2_IRQHandler,Default_Handler
.weak DMA_Channel3_IRQHandler
.thumb_set DMA_Channel3_IRQHandler,Default_Handler
.weak DMA_Channel4_IRQHandler
.thumb_set DMA_Channel4_IRQHandler,Default_Handler
.weak DMA_Channel5_IRQHandler
.thumb_set DMA_Channel5_IRQHandler,Default_Handler
.weak DMA_Channel6_IRQHandler
.thumb_set DMA_Channel6_IRQHandler,Default_Handler
.weak DMA_Channel7_IRQHandler
.thumb_set DMA_Channel7_IRQHandler,Default_Handler
.weak DMA_Channel8_IRQHandler
.thumb_set DMA_Channel8_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak USB_HP_IRQHandler
.thumb_set USB_HP_IRQHandler,Default_Handler
.weak USB_LP_IRQHandler
.thumb_set USB_LP_IRQHandler,Default_Handler
.weak COMP_1_2_IRQHandler
.thumb_set COMP_1_2_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTCAlarm_IRQHandler
.thumb_set RTCAlarm_IRQHandler,Default_Handler
.weak USBWakeUp_IRQHandler
.thumb_set USBWakeUp_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak LPUART_IRQHandler
.thumb_set LPUART_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak TIM6_IRQHandler
.thumb_set TIM6_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak CAN_TX_IRQHandler
.thumb_set CAN_TX_IRQHandler,Default_Handler
.weak CAN_RX0_IRQHandler
.thumb_set CAN_RX0_IRQHandler,Default_Handler
.weak CAN_RX1_IRQHandler
.thumb_set CAN_RX1_IRQHandler,Default_Handler
.weak CAN_SCE_IRQHandler
.thumb_set CAN_SCE_IRQHandler,Default_Handler
.weak LPUART_WKUP_IRQHandler
.thumb_set LPUART_WKUP_IRQHandler,Default_Handler
.weak LPTIM_WKUP_IRQHandler
.thumb_set LPTIM_WKUP_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak SAC_IRQHandler
.thumb_set SAC_IRQHandler,Default_Handler
.weak MMU_IRQHandler
.thumb_set MMU_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak RAMC_PERR_IRQHandler
.thumb_set RAMC_PERR_IRQHandler,Default_Handler
.weak TIM9_IRQHandler
.thumb_set TIM9_IRQHandler,Default_Handler
.weak UCDR_IRQHandler
.thumb_set UCDR_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.c
+615
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File diff suppressed because it is too large Load Diff
bsp/n32/libraries/N32G43x_Firmware_Library/CMSIS/device/system_n32g43x.h
+59
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@@ -0,0 +1,59 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file system_n32g43x.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __SYSTEM_N32G43X_H__
#define __SYSTEM_N32G43X_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup N32G43X_System
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_N32G43X_H__ */
bsp/n32/libraries/N32G43x_Firmware_Library/SConscript
+63
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@@ -0,0 +1,63 @@
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split('''
CMSIS/device/system_n32g43x.c
n32g43x_std_periph_driver/src/n32g43x_gpio.c
n32g43x_std_periph_driver/src/n32g43x_rcc.c
n32g43x_std_periph_driver/src/n32g43x_exti.c
n32g43x_std_periph_driver/src/misc.c
''')
if GetDepend(['RT_USING_SERIAL']):
src += ['n32g43x_std_periph_driver/src/n32g43x_usart.c']
if GetDepend(['RT_USING_I2C']):
src += ['n32g43x_std_periph_driver/src/n32g43x_i2c.c']
if GetDepend(['RT_USING_SPI']):
src += ['n32g43x_std_periph_driver/src/n32g43x_spi.c']
if GetDepend(['RT_USING_CAN']):
src += ['n32g43x_std_periph_driver/src/n32g43x_can.c']
if GetDepend(['RT_USING_ADC']):
src += ['n32g43x_std_periph_driver/src/n32g43x_adc.c']
if GetDepend(['RT_USING_DAC']):
src += ['n32g43x_std_periph_driver/src/n32g43x_dac.c']
if GetDepend(['RT_USING_HWTIMER']):
src += ['n32g43x_std_periph_driver/src/n32g43x_tim.c']
if GetDepend(['RT_USING_RTC']):
src += ['n32g43x_std_periph_driver/src/n32g43x_rtc.c']
src += ['n32g43x_std_periph_driver/src/n32g43x_pwr.c']
src += ['n32g43x_std_periph_driver/src/n32g43x_flash.c']
if GetDepend(['RT_USING_WDT']):
src += ['n32g43x_std_periph_driver/src/n32g43x_iwdg.c']
src += ['n32g43x_std_periph_driver/src/n32g43x_wwdg.c']
if GetDepend(['RT_USING_BSP_USB']):
path += [cwd + '/n32g43x_usbfs_driver/inc']
src += [cwd + '/n32g43x_usbfs_driver/src']
path = [
cwd + '/CMSIS/device',
cwd + '/CMSIS/core',
cwd + '/n32g43x_std_periph_driver/inc',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_aes.h
+119
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@@ -0,0 +1,119 @@
/*****************************************************************************
* NationS Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2020, NationS Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* NationS's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/*****************************************************************************
* File Name: n32g43x_aes.h
* Function: Declaring AES algorithm library API
* version: V1.2.0
* Author: zhang.zhenshan
* date: 2020-4-8
* ****************************************************************************/
#ifndef __N32G43X_AES_H__
#define __N32G43X_AES_H__
#include <stdint.h>
#define AES_ECB (0x11111111)
#define AES_CBC (0x22222222)
#define AES_CTR (0x33333333)
#define AES_ENC (0x44444444)
#define AES_DEC (0x55555555)
enum
{
AES_Crypto_OK = 0x0, //AES opreation success
AES_Init_OK = 0x0, //AES Init opreation success
AES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC nor CTR)
AES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
AES_Crypto_ParaNull, // the part of input(output/iv) Null
AES_Crypto_LengthError, // if Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
//if Working mode is CTR,the length of input message cannot be zero; othets: return AES_Crypto_LengthError
AES_Crypto_KeyLengthError, //the keyWordLen must be 4 or 6 or 8; othets:return AES_Crypto_KeyLengthError
AES_Crypto_UnInitError, //AES uninitialized
};
typedef struct
{
uint32_t *in; // the part of input to be encrypted or decrypted
uint32_t *iv; // the part of initial vector
uint32_t *out; // the part of out
uint32_t *key; // the part of key
uint32_t keyWordLen; // the length(by word) of key
uint32_t inWordLen; // the length(by word) of plaintext or cipher
uint32_t En_De; // 0x44444444- encrypt, 0x55555555 - decrypt
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC, 0x33333333 - CTR
}AES_PARM;
/**
* @brief AES_Init
* @return AES_Init_OK, AES Init success; othets: AES Init fail
* @note
*/
uint32_t AES_Init(AES_PARM *parm);
/**
* @brief AES crypto
* @param[in] parm pointer to AES context and the detail please refer to struct AES_PARM in AES.h
* @return AES_Crypto_OK, AES crypto success; othets: AES crypto fail(reference to the definition by enum variation)
* @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. If Working mode is ECB or CBC,the length of input message must be 4 times and cannot be zero;
* if Working mode is CTR,the length of input message cannot be zero;
* 5. If the input is in byte, make sure align by word.
*/
uint32_t AES_Crypto(AES_PARM *parm);
/**
* @brief AES close
* @return none
* @note if you want to close AES algorithm, this function can be recalled.
*/
void AES_Close(void);
/**
* @brief Get AES lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get AES lib information
*/
void AES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_algo_common.h
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/*****************************************************************************
* NationS Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2020, NationS Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* NationS's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/*****************************************************************************
* File Name: Common.h
* Function: Defining the public functions used by other algorithm lib
* version: V1.2.0
* Author: huang.jinshang
* date: 2020-01-06
* ****************************************************************************/
#ifndef _N32G43X_ALGO_COMMON_H_
#define _N32G43X_ALGO_COMMON_H_
#include <stdint.h>
enum{
Cpy_OK=0,//copy success
SetZero_OK = 0,//set zero success
XOR_OK = 0, //XOR success
Reverse_OK = 0, //Reverse success
Cmp_EQUAL = 0, //Two big number are equal
Cmp_UNEQUAL = 1, //Two big number are not equal
};
/**
* @brief disturb the sequence order
* @param[in] order pointer to the sequence to be disturbed
* @param[in] rand pointer to random number
* @param[in] the length of order
* @return RandomSort_OK: disturb order success; Others: disturb order fail;
* @note
*/
uint32_t RandomSort(uint8_t *order, const uint8_t *rand, uint32_t len);
/**
* @brief Copy data by byte
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
* @param[in] byte length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src cannot be same
*/
uint32_t Cpy_U8( uint8_t *dst, uint8_t *src, uint32_t byteLen);
/**
* @brief Copy data by word
* @param[in] dst pointer to destination data
* @param[in] src pointer to source data
* @param[in] word length
* @return Cpy_OK: success; others: fail.
* @note 1. dst and src must be aligned by word
*/
uint32_t Cpy_U32( uint32_t *dst, const uint32_t *src, uint32_t wordLen);
/**
* @brief XOR
* @param[in] a pointer to one data to be XORed
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
* @note
*/
uint32_t XOR_U8(uint8_t *a, uint8_t *b, uint8_t *c, uint32_t byteLen);
/**
* @brief XORed two u32 arrays
* @param[in] a pointer to one data to be XORed
* @param[in] b pointer to another data to be XORed
* @param[in] the length of order
* @return XOR_OK: operation success; Others: operation fail;
* @note
*/
uint32_t XOR_U32(uint32_t *a,uint32_t *b,uint32_t *c,uint32_t wordLen);
/**
* @brief set zero by byte
* @param[in] dst pointer to the address to be set zero
* @param[in] byte length
* @return SetZero_OK: success; others: fail.
* @note
*/
uint32_t SetZero_U8(uint8_t *dst, uint32_t byteLen);
/**
* @brief set zero by word
* @param[in] dst pointer to the address to be set zero
* @param[in] word length
* @return SetZero_OK: success; others: fail.
* @note
*/
uint32_t SetZero_U32(uint32_t *dst, uint32_t wordLen);
/**
* @brief reverse byte order of every word, the words stay the same
* @param[in] dst pointer to the destination address
* @param[in] src pointer to the source address
* @param[in] word length
* @return Reverse_OK: success; others: fail.
* @note 1.dst and src can be same
*/
uint32_t ReverseBytesInWord_U32(uint32_t *dst, const uint32_t *src, uint32_t wordLen);
/**
* @brief compare two big number
* @param[in] a pointer to one big number
* @param[in] word length of a
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
*
*/
int32_t Cmp_U32(const uint32_t *a, uint32_t aWordLen, const uint32_t *b, uint32_t bWordLen);
/**
* @brief compare two big number
* @param[in] a pointer to one big number
* @param[in] word length of a
* @param[in] b pointer to another big number
* @param[in] word length of b
* @return Cmp_UNEQUAL:a!=b;Cmp_EQUAL: a==b.
*
*/
int32_t Cmp_U8(const uint8_t *a, uint32_t aByteLen, const uint8_t *b, uint32_t bByteLen);
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_des.h
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/*****************************************************************************
* Nations Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2020, Nations Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY Nations "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL Nations BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/*****************************************************************************
* File Name: Dn32g43x_des.h
* Function: Declaring DES algorithm library API
* version: V1.2.0
* Author: zhang.zhenshan
* date: 2020-4-8
* ****************************************************************************/
#ifndef _N32G43X_DES_H_
#define _N32G43X_DES_H_
#include <stdint.h>
#define DES_ECB (0x11111111)
#define DES_CBC (0x22222222)
#define DES_ENC (0x33333333)
#define DES_DEC (0x44444444)
#define DES_KEY (0x55555555)
#define TDES_2KEY (0x66666666)
#define TDES_3KEY (0x77777777)
enum DES
{
DES_Crypto_OK = 0x0, //DES/TDES opreation success
DES_Init_OK = 0x0, //DES/TDES Init opreation success
DES_Crypto_ModeError = 0x5a5a5a5a, //Working mode error(Neither ECB nor CBC)
DES_Crypto_EnOrDeError, //En&De error(Neither encryption nor decryption)
DES_Crypto_ParaNull, // the part of input(output/iv) Null
DES_Crypto_LengthError, //the length of input message must be 2 times and cannot be zero
DES_Crypto_KeyError, //keyMode error(Neither DES_KEY nor TDES_2KEY nor TDES_3KEY)
DES_Crypto_UnInitError, //DES/TDES uninitialized
};
typedef struct
{
uint32_t *in; // the part of input to be encrypted or decrypted
uint32_t *iv; // the part of initial vector
uint32_t *out; // the part of out
uint32_t *key; // the part of key
uint32_t inWordLen; // the length(by word) of plaintext or cipher
uint32_t En_De; // 0x33333333- encrypt, 0x44444444 - decrypt
uint32_t Mode; // 0x11111111 - ECB, 0x22222222 - CBC
uint32_t keyMode; //TDES key mode: 0x55555555-key,0x66666666-2key, 0x77777777-3key
}DES_PARM;
/**
* @brief DES_Init
* @return DES_Init_OK, DES/TDES Init success; othets: DES/TDES Init fail
* @note
*/
uint32_t DES_Init(DES_PARM *parm);
/**
* @brief DES crypto
* @param[in] parm pointer to DES/TDES context and the detail please refer to struct DES_PARM in DES.h
* @return DES_Crypto_OK, DES/TDES crypto success; othets: DES/TDES crypto fail(reference to the definition by enum variation)
* @note 1.Please refer to the demo in user guidance before using this function
* 2.Input and output can be the same buffer
* 3. IV can be NULL when ECB mode
* 4. The word lengrh of message must be as times as 2.
* 5. If the input is in byte, make sure align by word.
*/
uint32_t DES_Crypto(DES_PARM *parm);
/**
* @brief DES close
* @return none
* @note if you want to close DES algorithm, this function can be recalled.
*/
void DES_Close(void);
/**
* @brief Get DES/TDES lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get DES/TDES lib information
*/
void DES_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_hash.h
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/*****************************************************************************
* Nationz Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2020, Nationz Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nationz's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/*****************************************************************************
* File Name: HASH.h
* Function: Declaring HASH algorithm library API
* version: V1.2.0
* Author: zhang.zhenshan
* date: 2020-4-8
* ****************************************************************************/
#ifndef _N32G43X_HASH_H_
#define _N32G43X_HASH_H_
#include <stdint.h>
#define ALG_SHA1 (uint16_t)(0x0004)
#define ALG_SHA224 (uint16_t)(0x000A)
#define ALG_SHA256 (uint16_t)(0x000B)
//#define ALG_MD5 (u16)(0x000C)
#define ALG_SM3 (uint16_t)(0x0012)
enum
{
HASH_SEQUENCE_TRUE = 0x0105A5A5,//save IV
HASH_SEQUENCE_FALSE = 0x010A5A5A, //not save IV
HASH_Init_OK = 0,//hash init success
HASH_Start_OK = 0,//hash update success
HASH_Update_OK = 0,//hash update success
HASH_Complete_OK = 0,//hash complete success
HASH_Close_OK = 0,//hash close success
HASH_ByteLenPlus_OK = 0,//byte length plus success
HASH_PadMsg_OK = 0,//message padding success
HASH_ProcMsgBuf_OK = 0, //message processing success
SHA1_Hash_OK = 0,//sha1 operation success
SM3_Hash_OK = 0,//sm3 operation success
SHA224_Hash_OK = 0,//sha224 operation success
SHA256_Hash_OK = 0,//sha256 operation success
//MD5_Hash_OK = 0,//MD5 operation success
HASH_Init_ERROR = 0x01044400,//hash init error
HASH_Start_ERROR, //hash start error
HASH_Update_ERROR, //hash update error
HASH_ByteLenPlus_ERROR,//hash byte plus error
};
struct _HASH_CTX_;
typedef struct
{
const uint16_t HashAlgID;//choice hash algorithm
const uint32_t * const K, KLen;//K and word length of K
const uint32_t * const IV, IVLen;//IV and word length of IV
const uint32_t HASH_SACCR, HASH_HASHCTRL;//relate registers
const uint32_t BlockByteLen, BlockWordLen; //byte length of block, word length of block
const uint32_t DigestByteLen, DigestWordLen; //byte length of digest,word length of digest
const uint32_t Cycle; //interation times
uint32_t (* const ByteLenPlus)(uint32_t *, uint32_t); //function pointer
uint32_t (* const PadMsg)(struct _HASH_CTX_ *); //function pointer
}HASH_ALG;
typedef struct _HASH_CTX_
{
const HASH_ALG *hashAlg;//pointer to HASH_ALG
uint32_t sequence; // TRUE if the IV should be saved
uint32_t IV[16];
uint32_t msgByteLen[4];
uint8_t msgBuf[128+4];
uint32_t msgIdx;
}HASH_CTX;
extern const HASH_ALG HASH_ALG_SHA1[1];
extern const HASH_ALG HASH_ALG_SHA224[1];
extern const HASH_ALG HASH_ALG_SHA256[1];
//extern const HASH_ALG HASH_ALG_MD5[1];
extern const HASH_ALG HASH_ALG_SM3[1];
/**
* @brief Hash init
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Init_OK, Hash init success; othets: Hash init fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Init(HASH_CTX *ctx);
/**
* @brief Hash start
* @param[in] ctx pointer to HASH_CTX struct
* @return HASH_Start_OK, Hash start success; othets: Hash start fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init() should be recalled before use this function
*/
uint32_t HASH_Start(HASH_CTX *ctx);
/**
* @brief Hash update
* @param[in] ctx pointer to HASH_CTX struct
* @param[in] in pointer to message
* @param[out] out pointer tohash result,digest
* @return HASH_Update_OK, Hash update success; othets: Hash update fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init() and HASH_Start() should be recalled before use this function
*/
uint32_t HASH_Update(HASH_CTX *ctx, uint8_t *in, uint32_t byteLen);
/**
* @brief Hash complete
* @param[in] ctx pointer to HASH_CTX struct
* @param[out] out pointer tohash result,digest
* @return HASH_Complete_OK, Hash complete success; othets: Hash complete fail
* @note 1.Please refer to the demo in user guidance before using this function
* 2.HASH_Init(), HASH_Start() and HASH_Update() should be recalled before use this function
*/
uint32_t HASH_Complete(HASH_CTX *ctx, uint8_t *out);
/**
* @brief Hash close
* @return HASH_Close_OK, Hash close success; othets: Hash close fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t HASH_Close(void);
/**
* @brief SM3 Hash for 256bits digest
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SM3_Hash_OK, SM3 hash success; othets: SM3 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SM3_Hash(uint8_t *in,uint32_t byteLen, uint8_t* out);
/**
* @brief SHA1 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA1_Hash_OK, SHA1 hash success; othets: SHA1 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA1_Hash(uint8_t*in, uint32_t byteLen, uint8_t*out);
/**
* @brief SHA224 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA224_Hash_OK, SHA224 hash success; othets: SHA224 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA224_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief SHA256 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[out] out pointer tohash result,digest
* @return SHA256_Hash_OK, SHA256 hash success; othets: SHA256 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
uint32_t SHA256_Hash(uint8_t* in,uint32_t byteLen, uint8_t* out);
/**
* @brief MD5 Hash
* @param[in] in pointer to message
* @param[in] byte length of in
* @param[in] out pointer tohash result,digest
* @return MD5_Hash_OK, MD5 hash success; othets: MD5 hash fail
* @note 1.Please refer to the demo in user guidance before using this function
*/
//u32 MD5_Hash(u8* in,u32 byteLen, u8* out);
/**
* @brief Get HASH lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
*/
void HASH_Version(uint8_t*type, uint8_t*customer, uint8_t date[3], uint8_t *version);
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_algo_lib/inc/n32g43x_rng.h
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/*****************************************************************************
* NationS Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2020, NationS Corporation
*
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* NationS's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONZ BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/*****************************************************************************
* File Name: n32g43x_rng.h
* Function: Declaring RNG algorithm library API
* version: V1.2.0
* Author: zhang.zhenshan
* date: 2020-4-8
* ****************************************************************************/
#ifndef _N32G43X_RNG_H_
#define _N32G43X_RNG_H_
#include <stdint.h>
enum{
RNG_OK = 0x5a5a5a5a,
LENError = 0x311ECF50, //RNG generation of key length error
ADDRNULL = 0x7A9DB86C, // This address is empty
};
//u32 RNG_init(void);
/**
* @brief Get pseudo random number
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
* @param[in] the seed, can be NULL
* @return RNG_OK:get random number success; othets: get random number fail
* @note
*/
uint32_t GetPseudoRand_U32(uint32_t *rand, uint32_t wordLen,uint32_t seed[2]);
/**
* @brief Get true random number
* @param[out] rand pointer to random number
* @param[in] the wordlen of random number
* @return RNG_OK:get random number success; othets: get random number fail
* @note
*/
uint32_t GetTrueRand_U32(uint32_t *rand, uint32_t wordLen);
/**
* @brief Get RNG lib version
* @param[out] type pointer one byte type information represents the type of the lib, like Commercial version.\
* @Bits 0~4 stands for Commercial (C), Security (S), Normal (N), Evaluation (E), Test (T), Bits 5~7 are reserved. e.g. 0x09 stands for CE version.
* @param[out] customer pointer one byte customer information represents customer ID. for example, 0x00 stands for standard version, 0x01 is for Tianyu customized version...
* @param[out] date pointer array which include three bytes date information. If the returned bytes are 18,9,13,this denotes September 13,2018
* @param[out] version pointer one byte version information represents develop version of the lib. e.g. 0x12 denotes version 1.2.
* @return none
* @1.You can recall this function to get RSA lib information
*/
void RNG_Version(uint8_t *type, uint8_t *customer, uint8_t date[3], uint8_t *version);
#endif
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/misc.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file misc.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __MISC_H__
#define __MISC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @{
*/
/** @addtogroup MISC_Exported_Types
* @{
*/
/**
* @brief NVIC Init Structure definition
*/
typedef struct
{
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete N32G43x Devices IRQ Channels list, please
refer to n32g43x.h file) */
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
in NVIC_IRQChannel. This parameter can be a value
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitType;
/**
* @}
*/
/** @addtogroup NVIC_Priority_Table
* @{
*/
/**
@code
The table below gives the allowed values of the pre-emption priority and subpriority according
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
============================================================================================================================
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
============================================================================================================================
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption
priority | | | 4 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption
priority | | | 3 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption
priority | | | 2 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption
priority | | | 1 bits for subpriority
----------------------------------------------------------------------------------------------------------------------------
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption
priority | | | 0 bits for subpriority
============================================================================================================================
@endcode
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Constants
* @{
*/
/** @addtogroup Vector_Table_Base
* @{
*/
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
/**
* @}
*/
/** @addtogroup System_Low_Power
* @{
*/
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
/**
* @}
*/
/** @addtogroup Preemption_Priority_Group
* @{
*/
#define NVIC_PriorityGroup_0 \
((uint32_t)0x700) /*!< 0 bits for pre-emption priority \
4 bits for subpriority */
#define NVIC_PriorityGroup_1 \
((uint32_t)0x600) /*!< 1 bits for pre-emption priority \
3 bits for subpriority */
#define NVIC_PriorityGroup_2 \
((uint32_t)0x500) /*!< 2 bits for pre-emption priority \
2 bits for subpriority */
#define NVIC_PriorityGroup_3 \
((uint32_t)0x400) /*!< 3 bits for pre-emption priority \
1 bits for subpriority */
#define NVIC_PriorityGroup_4 \
((uint32_t)0x300) /*!< 4 bits for pre-emption priority \
0 bits for subpriority */
#define IS_NVIC_PRIORITY_GROUP(GROUP) \
(((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) \
|| ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
/**
* @}
*/
/** @addtogroup SysTick_clock_source
* @{
*/
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) \
(((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Exported_Functions
* @{
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitType* NVIC_InitStruct);
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd);
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_adc.h
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bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_comp.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_comp.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_COMP_H__
#define __N32G43X_COMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
#include <stdbool.h>
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/** @addtogroup COMP_Exported_Constants
* @{
*/
typedef enum
{
COMP1 = 0,
COMP2 = 1,
} COMPX;
// COMPx_CTRL
#define COMP1_CTRL_PWRMODE_MASK (0x01L << 21)
#define COMP1_CTRL_INPDAC_MASK (0x01L << 20)
#define COMP_CTRL_OUT_MASK (0x01L << 19)
#define COMP_CTRL_BLKING_MASK (0x03L << 16)
typedef enum
{
COMP_CTRL_BLKING_NO = (0x0L << 16),
COMP_CTRL_BLKING_TIM1_OC5 = (0x1L << 16),
COMP_CTRL_BLKING_TIM8_OC5 = (0x2L << 16),
} COMP_CTRL_BLKING;
#define COMPx_CTRL_HYST_MASK (0x03L << 14)
typedef enum
{
COMP_CTRL_HYST_NO = (0x0L << 14),
COMP_CTRL_HYST_LOW = (0x1L << 14),
COMP_CTRL_HYST_MID = (0x2L << 14),
COMP_CTRL_HYST_HIGH = (0x3L << 14),
} COMP_CTRL_HYST;
#define COMP_POL_MASK (0x01L << 13)
#define COMP_CTRL_OUTSEL_MASK (0x0FL << 9)
typedef enum
{
// comp1 out trig
COMP1_CTRL_OUTSEL_NC = (0x0L << 9),
COMP1_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
COMP1_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
COMP1_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
COMP1_CTRL_OUTSEL_TIM2_IC1 = (0x4L << 9),
COMP1_CTRL_OUTSEL_TIM2_OCrefclear = (0x5L << 9),
COMP1_CTRL_OUTSEL_TIM3_IC1 = (0x6L << 9),
COMP1_CTRL_OUTSEL_TIM3_OCrefclear = (0x7L << 9),
COMP1_CTRL_OUTSEL_TIM4_OCrefclear = (0x8L << 9),
COMP1_CTRL_OUTSEL_TIM5_IC1 = (0x9L << 9),
COMP1_CTRL_OUTSEL_TIM8_IC1 = (0xAL << 9),
COMP1_CTRL_OUTSEL_TIM8_OCrefclear = (0xBL << 9),
COMP1_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
COMP1_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
COMP1_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
COMP1_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
// comp2 out trig
COMP2_CTRL_OUTSEL_NC = (0x0L << 9),
COMP2_CTRL_OUTSEL_TIM1_BKIN = (0x1L << 9),
COMP2_CTRL_OUTSEL_TIM1_OCrefclear = (0x2L << 9),
COMP2_CTRL_OUTSEL_TIM1_IC1 = (0x3L << 9),
COMP2_CTRL_OUTSEL_TIM2_OCrefclear = (0x4L << 9),
COMP2_CTRL_OUTSEL_TIM3_OCrefclear = (0x5L << 9),
COMP2_CTRL_OUTSEL_TIM4_IC1 = (0x6L << 9),
COMP2_CTRL_OUTSEL_TIM4_OCrefclear = (0x7L << 9),
COMP2_CTRL_OUTSEL_TIM5_IC1 = (0x8L << 9),
COMP2_CTRL_OUTSEL_TIM8_IC1 = (0x9L << 9),
COMP2_CTRL_OUTSEL_TIM8_OCrefclear = (0xAL << 9),
COMP2_CTRL_OUTSEL_TIM9_IC1 = (0xBL << 9),
COMP2_CTRL_OUTSEL_TIM9_OCrefclear = (0xCL << 9),
COMP2_CTRL_OUTSEL_TIM8_BKIN = (0xDL << 9),
COMP2_CTRL_OUTSEL_TIM1_BKIN_TIM8_BKIN = (0xEL << 9),
COMP2_CTRL_OUTSEL_LPTIM_ETR = (0xFL << 9),
} COMP_CTRL_OUTTRIG;
#define COMP_CTRL_INPSEL_MASK (0x0FL<<5)
typedef enum {
//comp1 inp sel
COMP1_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
COMP1_CTRL_INPSEL_PA0 = ((uint32_t)0x00000100),
COMP1_CTRL_INPSEL_PA2 = ((uint32_t)0x00000140),
COMP1_CTRL_INPSEL_PA12 = ((uint32_t)0x00000160),
COMP1_CTRL_INPSEL_PB3 = ((uint32_t)0x00000180),
COMP1_CTRL_INPSEL_PB4 = ((uint32_t)0x000001A0),
COMP1_CTRL_INPSEL_PB10 = ((uint32_t)0x000001C0),
COMP1_CTRL_INPSEL_PD5 = ((uint32_t)0x000001E0),
COMP1_CTRL_INPSEL_PA1_DAC1 = ((uint32_t)0x00000120),
//comp2 inp sel
COMP2_CTRL_INPSEL_FLOAT = ((uint32_t)0x00000000),
COMP2_CTRL_INPSEL_PA1_DAC1_PA4= ((uint32_t)0x00000100),
COMP2_CTRL_INPSEL_PA3 = ((uint32_t)0x00000120),
COMP2_CTRL_INPSEL_PA6 = ((uint32_t)0x00000140),
COMP2_CTRL_INPSEL_PA7 = ((uint32_t)0x00000160),
COMP2_CTRL_INPSEL_PA11 = ((uint32_t)0x00000180),
COMP2_CTRL_INPSEL_PA15 = ((uint32_t)0x000001A0),
COMP2_CTRL_INPSEL_PB7 = ((uint32_t)0x000001C0),
COMP2_CTRL_INPSEL_PD7 = ((uint32_t)0x000001E0),
}COMP_CTRL_INPSEL;
#define COMP_CTRL_INMSEL_MASK (0x07L<<1)
typedef enum {
//comp1 inm sel
COMP1_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x00000002),
COMP1_CTRL_INMSEL_PA0 = ((uint32_t)0x00000004),
COMP1_CTRL_INMSEL_PA5 = ((uint32_t)0x00000006),
COMP1_CTRL_INMSEL_PB5 = ((uint32_t)0x00000008),
COMP1_CTRL_INMSEL_PD4 = ((uint32_t)0x0000000A),
COMP1_CTRL_INMSEL_VREF_VC1 = ((uint32_t)0x0000000C),
COMP1_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
COMP1_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
//comp2 inm sel
COMP2_CTRL_INMSEL_PA2 = ((uint32_t)0x00000002),
COMP2_CTRL_INMSEL_PA5 = ((uint32_t)0x00000004),
COMP2_CTRL_INMSEL_PA6 = ((uint32_t)0x00000006),
COMP2_CTRL_INMSEL_PB3 = ((uint32_t)0x00000008),
COMP2_CTRL_INMSEL_PD6 = ((uint32_t)0x0000000A),
COMP2_CTRL_INMSEL_DAC1_PA4 = ((uint32_t)0x0000000C),
COMP2_CTRL_INMSEL_VREF_VC2 = ((uint32_t)0x0000000E),
COMP2_CTRL_INMSEL_NC = ((uint32_t)0x00000000),
}COMP_CTRL_INMSEL;
#define COMP_CTRL_EN_MASK (0x01L << 0)
//COMPx_FILC
#define COMP_FILC_SAMPW_MASK (0x1FL<<6)//Low filter sample window size. Number of samples to monitor is SAMPWIN+1.
#define COMP_FILC_THRESH_MASK (0x1FL<<1)//For proper operation, the value of THRESH must be greater than SAMPWIN / 2.
#define COMP_FILC_FILEN_MASK (0x01L<<0)//Filter enable.
//COMPx_FILP
#define COMP_FILP_CLKPSC_MASK (0xFFFFL)//Prescale number .
//COMP_WINMODE @addtogroup COMP_WINMODE_CMPMD
#define COMP_WINMODE_CMP12MD (0x01L <<0)//1: Comparators 1 and 2 can be used in window mode.
//COMP_INTEN @addtogroup COMP_INTEN_CMPIEN
#define COMP_INTEN_CMPIEN_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
#define COMP_INTEN_CMP2IEN (0x01L << 1)
#define COMP_INTEN_CMP1IEN (0x01L << 0)
//COMP_INTSTS @addtogroup COMP_INTSTS_CMPIS
#define COMP_INTSTS_INTSTS_MSK (0x3L << 0) // This bit control Interrput enable of COMP.
#define COMP_INTSTS_CMP2IS (0x01L << 1)
#define COMP_INTSTS_CMP1IS (0x01L << 0)
//COMP_VREFSCL @addtogroup COMP_VREFSCL
#define COMP_VREFSCL_VV2TRM_MSK (0x3FL << 8) // Vref2 Voltage scaler triming value.
#define COMP_VREFSCL_VV2EN_MSK (0x01L << 7)
#define COMP_VREFSCL_VV1TRM_MSK (0x3FL << 1) // Vref1 Voltage scaler triming value.
#define COMP_VREFSCL_VV1EN_MSK (0x01L << 0)
//COMP_LOCK @addtogroup COMP_LOCK
#define COMP_LOCK_CMP2LK (0x1L << 1) // Vref1 Voltage scaler triming value.
#define COMP_LOCK_CMP1LK (0x1L << 0)
//COMP_LPCKSEL @addtogroup COMP_LPCKSEL
#define COMP_LKCKSEL_LPCLKSEL (0x1L << 0)
//COMP_OSEL @addtogroup COMP_OSEL
#define COMP_OSEL_CMP2XO (0x1L << 0)
/**
* @}
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
// ctrl
bool LowPoweMode; // only COMP1 have this bit
bool InpDacConnect; // only COMP1 have this bit
COMP_CTRL_BLKING Blking; /*see @ref COMP_CTRL_BLKING */
COMP_CTRL_HYST Hyst;
bool PolRev; // out polarity reverse
COMP_CTRL_OUTTRIG OutTrig;
COMP_CTRL_INPSEL InpSel;
COMP_CTRL_INMSEL InmSel;
bool En;
// filter
uint8_t SampWindow; // 5bit
uint8_t Thresh; // 5bit ,need > SampWindow/2
bool FilterEn;
// filter psc
uint16_t ClkPsc;
} COMP_InitType;
/** @addtogroup COMP_Exported_Functions
* @{
*/
void COMP_DeInit(void);
void COMP_StructInit(COMP_InitType* COMP_InitStruct);
void COMP_Init(COMPX COMPx, COMP_InitType* COMP_InitStruct);
void COMP_Enable(COMPX COMPx, FunctionalState en);
void COMP_SetInpSel(COMPX COMPx, COMP_CTRL_INPSEL VpSel);
void COMP_SetInmSel(COMPX COMPx, COMP_CTRL_INMSEL VmSel);
void COMP_SetOutTrig(COMPX COMPx, COMP_CTRL_OUTTRIG OutTrig);
uint32_t COMP_GetIntSts(void); // return see @COMP_INTSTS_CMPIS
void COMP_SetRefScl(uint8_t Vv2Trim, bool Vv2En, uint8_t Vv1Trim, bool Vv1En); // parma range see @COMP_VREFSCL
FlagStatus COMP_GetOutStatus(COMPX COMPx);
FlagStatus COMP_GetIntStsOneComp(COMPX COMPx);
void COMP_SetLock(uint32_t Lock); // see @COMP_LOCK_CMPLK
void COMP_SetIntEn(uint32_t IntEn); // see @COMP_INTEN_CMPIEN
void COMP_CMP2XorOut(bool En);
void COMP_StopOrLowpower32KClkSel(bool En);
void COMP_WindowModeEn(bool En);
void COMP_SetFilterPrescaler(COMPX COMPx , uint16_t FilPreVal);
void COMP_SetFilterControl(COMPX COMPx , uint8_t FilEn, uint8_t TheresNum , uint8_t SampPW);
void COMP_SetHyst(COMPX COMPx , COMP_CTRL_HYST HYST);
void COMP_SetBlanking(COMPX COMPx , COMP_CTRL_BLKING BLK);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__N32G43X_ADC_H */
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_crc.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_crc.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_CRC_H__
#define __N32G43X_CRC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/** @addtogroup CRC_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup CRC_Exported_Functions
* @{
*/
void CRC32_ResetCrc(void);
uint32_t CRC32_CalcCrc(uint32_t Data);
uint32_t CRC32_CalcBufCrc(uint32_t pBuffer[], uint32_t BufferLength);
uint32_t CRC32_GetCrc(void);
void CRC32_SetIDat(uint8_t IDValue);
uint8_t CRC32_GetIDat(void);
uint16_t CRC16_CalcBufCrc(uint8_t pBuffer[], uint32_t BufferLength);
uint16_t CRC16_CalcCRC(uint8_t Data);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43X_CRC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dac.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_dac.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_DAC_H__
#define __N32G43X_DAC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/** @addtogroup DAC_Exported_Types
* @{
*/
/**
* @brief DAC Init structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t WaveGen; /*!< Specifies whether DAC channel noise waves or triangle waves
are generated, or whether no wave is generated.
This parameter can be a value of @ref DAC_wave_generation */
uint32_t
LfsrUnMaskTriAmp; /*!< Specifies the LFSR mask for noise wave generation or
the maximum amplitude triangle generation for the DAC channel.
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
uint32_t BufferOutput; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
} DAC_InitType;
/**
* @}
*/
/** @addtogroup DAC_Exported_Constants
* @{
*/
/** @addtogroup DAC_trigger_selection
* @{
*/
#define DAC_TRG_NONE \
((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register \
has been loaded, and not by external trigger */
#define DAC_TRG_T6_TRGO \
((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T8_TRGO \
((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel \
only in High-density devices*/
#define DAC_TRG_T7_TRGO \
((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T5_TRGO \
((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T2_TRGO \
((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_T4_TRGO \
((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel \
*/
#define DAC_TRG_EXT_IT9 \
((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRG_SOFTWARE ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) \
(((TRIGGER) == DAC_TRG_NONE) || ((TRIGGER) == DAC_TRG_T6_TRGO) || ((TRIGGER) == DAC_TRG_T8_TRGO) \
|| ((TRIGGER) == DAC_TRG_T7_TRGO) || ((TRIGGER) == DAC_TRG_T5_TRGO) || ((TRIGGER) == DAC_TRG_T2_TRGO) \
|| ((TRIGGER) == DAC_TRG_T4_TRGO) || ((TRIGGER) == DAC_TRG_EXT_IT9) || ((TRIGGER) == DAC_TRG_SOFTWARE))
/**
* @}
*/
/** @addtogroup DAC_wave_generation
* @{
*/
#define DAC_WAVEGEN_NONE ((uint32_t)0x00000000)
#define DAC_WAVEGEN_NOISE ((uint32_t)0x00000040)
#define DAC_WAVEGEN_TRIANGLE ((uint32_t)0x00000080)
#define IS_DAC_GENERATE_WAVE(WAVE) \
(((WAVE) == DAC_WAVEGEN_NONE) || ((WAVE) == DAC_WAVEGEN_NOISE) || ((WAVE) == DAC_WAVEGEN_TRIANGLE))
/**
* @}
*/
/** @addtogroup DAC_lfsrunmask_triangleamplitude
* @{
*/
#define DAC_UNMASK_LFSRBIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_UNMASK_LFSRBITS1_0 \
((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS2_0 \
((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS3_0 \
((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS4_0 \
((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS5_0 \
((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS6_0 \
((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS7_0 \
((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS8_0 \
((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS9_0 \
((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation \
*/
#define DAC_UNMASK_LFSRBITS10_0 \
((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_UNMASK_LFSRBITS11_0 \
((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIAMP_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIAMP_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIAMP_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIAMP_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIAMP_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIAMP_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIAMP_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIAMP_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIAMP_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIAMP_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIAMP_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIAMP_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) \
(((VALUE) == DAC_UNMASK_LFSRBIT0) || ((VALUE) == DAC_UNMASK_LFSRBITS1_0) || ((VALUE) == DAC_UNMASK_LFSRBITS2_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS3_0) || ((VALUE) == DAC_UNMASK_LFSRBITS4_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS5_0) || ((VALUE) == DAC_UNMASK_LFSRBITS6_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS7_0) || ((VALUE) == DAC_UNMASK_LFSRBITS8_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS9_0) || ((VALUE) == DAC_UNMASK_LFSRBITS10_0) \
|| ((VALUE) == DAC_UNMASK_LFSRBITS11_0) || ((VALUE) == DAC_TRIAMP_1) || ((VALUE) == DAC_TRIAMP_3) \
|| ((VALUE) == DAC_TRIAMP_7) || ((VALUE) == DAC_TRIAMP_15) || ((VALUE) == DAC_TRIAMP_31) \
|| ((VALUE) == DAC_TRIAMP_63) || ((VALUE) == DAC_TRIAMP_127) || ((VALUE) == DAC_TRIAMP_255) \
|| ((VALUE) == DAC_TRIAMP_511) || ((VALUE) == DAC_TRIAMP_1023) || ((VALUE) == DAC_TRIAMP_2047) \
|| ((VALUE) == DAC_TRIAMP_4095))
/**
* @}
*/
/** @addtogroup DAC_output_buffer
* @{
*/
#define DAC_BUFFOUTPUT_ENABLE ((uint32_t)0x00000002)
#define DAC_BUFFOUTPUT_DISABLE ((uint32_t)0x00000000)
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_BUFFOUTPUT_ENABLE) || ((STATE) == DAC_BUFFOUTPUT_DISABLE))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_data_alignment
* @{
*/
#define DAC_ALIGN_R_12BIT ((uint32_t)0x00000000)
#define DAC_ALIGN_L_12BIT ((uint32_t)0x00000004)
#define DAC_ALIGN_R_8BIT ((uint32_t)0x00000008)
#define IS_DAC_ALIGN(ALIGN) \
(((ALIGN) == DAC_ALIGN_R_12BIT) || ((ALIGN) == DAC_ALIGN_L_12BIT) || ((ALIGN) == DAC_ALIGN_R_8BIT))
/**
* @}
*/
/** @addtogroup DAC_wave_generation
* @{
*/
#define DAC_WAVE_NOISE ((uint32_t)0x00000040)
#define DAC_WAVE_TRIANGLE ((uint32_t)0x00000080)
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || ((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
*/
/** @addtogroup DAC_data
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
void DAC_DeInit(void);
void DAC_Init(DAC_InitType* DAC_InitStruct);
void DAC_ClearStruct(DAC_InitType* DAC_InitStruct);
void DAC_Enable(FunctionalState Cmd);
void DAC_DmaEnable(FunctionalState Cmd);
void DAC_SoftTrgEnable(FunctionalState Cmd);
void DAC_SoftwareTrgEnable(FunctionalState Cmd);
void DAC_WaveGenerationEnable(uint32_t DAC_Wave, FunctionalState Cmd);
void DAC_SetChData(uint32_t DAC_Align, uint16_t Data);
uint16_t DAC_GetOutputDataVal(void);
#ifdef __cplusplus
}
#endif
#endif /*__N32G43X_DAC_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dbg.h
+124
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_dbg.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43x_DBG_H__
#define __N32G43x_DBG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup DBG
* @{
*/
/** @addtogroup DBGMCU_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Constants
* @{
*/
#define DBG_SLEEP ((uint32_t)0x00000001)
#define DBG_STOP ((uint32_t)0x00000002)
#define DBG_STDBY ((uint32_t)0x00000004)
#define DBG_IWDG_STOP ((uint32_t)0x00000100)
#define DBG_WWDG_STOP ((uint32_t)0x00000200)
#define DBG_TIM1_STOP ((uint32_t)0x00000400)
#define DBG_TIM2_STOP ((uint32_t)0x00000800)
#define DBG_TIM3_STOP ((uint32_t)0x00001000)
#define DBG_TIM4_STOP ((uint32_t)0x00002000)
#define DBG_CAN_STOP ((uint32_t)0x00004000)
#define DBG_I2C1SMBUS_TIMEOUT ((uint32_t)0x00008000)
#define DBG_I2C2SMBUS_TIMEOUT ((uint32_t)0x00010000)
#define DBG_TIM8_STOP ((uint32_t)0x00020000)
#define DBG_TIM5_STOP ((uint32_t)0x00040000)
#define DBG_TIM6_STOP ((uint32_t)0x00080000)
#define DBG_TIM7_STOP ((uint32_t)0x00100000)
#define DBG_TIM9_STOP ((uint32_t)0x00200000)
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH)&0xFFC000F8) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup DBGMCU_Exported_Functions
* @{
*/
void GetUCID(uint8_t *UCIDbuf);
void GetUID(uint8_t *UIDbuf);
void GetDBGMCU_ID(uint8_t *DBGMCU_IDbuf);
uint32_t DBG_GetRevNum(void);
uint32_t DBG_GetDevNum(void);
void DBG_ConfigPeriph(uint32_t DBG_Periph, FunctionalState Cmd);
uint32_t DBG_GetFlashSize(void);
uint32_t DBG_GetSramSize(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43x_DBG_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_dma.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_dma.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_DMA_H__
#define __N32G43X_DMA_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @addtogroup DMA_Exported_Types
* @{
*/
/**
* @brief DMA Init structure definition
*/
typedef struct
{
uint32_t PeriphAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
uint32_t MemAddr; /*!< Specifies the memory base address for DMAy Channelx. */
uint32_t Direction; /*!< Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t BufSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in PeriphDataSize
or MemDataSize members depending in the transfer direction. */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t PeriphDataSize; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t MemDataSize; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t CircularMode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t Mem2Mem; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitType;
/**
* @}
*/
/** @addtogroup DMA_Exported_Constants
* @{
*/
#define IS_DMA_ALL_PERIPH(PERIPH) \
(((PERIPH) == DMA_CH1) || ((PERIPH) == DMA_CH2) || ((PERIPH) == DMA_CH3) || ((PERIPH) == DMA_CH4) \
|| ((PERIPH) == DMA_CH5) || ((PERIPH) == DMA_CH6) || ((PERIPH) == DMA_CH7) || ((PERIPH) == DMA_CH8))
/** @addtogroup DMA_data_transfer_direction
* @{
*/
#define DMA_DIR_PERIPH_DST ((uint32_t)0x00000010)
#define DMA_DIR_PERIPH_SRC ((uint32_t)0x00000000)
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PERIPH_DST) || ((DIR) == DMA_DIR_PERIPH_SRC))
/**
* @}
*/
/** @addtogroup DMA_peripheral_incremented_mode
* @{
*/
#define DMA_PERIPH_INC_ENABLE ((uint32_t)0x00000040)
#define DMA_PERIPH_INC_DISABLE ((uint32_t)0x00000000)
#define IS_DMA_PERIPH_INC_STATE(STATE) (((STATE) == DMA_PERIPH_INC_ENABLE) || ((STATE) == DMA_PERIPH_INC_DISABLE))
/**
* @}
*/
/** @addtogroup DMA_memory_incremented_mode
* @{
*/
#define DMA_MEM_INC_ENABLE ((uint32_t)0x00000080)
#define DMA_MEM_INC_DISABLE ((uint32_t)0x00000000)
#define IS_DMA_MEM_INC_STATE(STATE) (((STATE) == DMA_MEM_INC_ENABLE) || ((STATE) == DMA_MEM_INC_DISABLE))
/**
* @}
*/
/** @addtogroup DMA_peripheral_data_size
* @{
*/
#define DMA_PERIPH_DATA_SIZE_BYTE ((uint32_t)0x00000000)
#define DMA_PERIPH_DATA_SIZE_HALFWORD ((uint32_t)0x00000100)
#define DMA_PERIPH_DATA_SIZE_WORD ((uint32_t)0x00000200)
#define IS_DMA_PERIPH_DATA_SIZE(SIZE) \
(((SIZE) == DMA_PERIPH_DATA_SIZE_BYTE) || ((SIZE) == DMA_PERIPH_DATA_SIZE_HALFWORD) \
|| ((SIZE) == DMA_PERIPH_DATA_SIZE_WORD))
/**
* @}
*/
/** @addtogroup DMA_memory_data_size
* @{
*/
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) \
(((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) \
|| ((SIZE) == DMA_MemoryDataSize_Word))
/**
* @}
*/
/** @addtogroup DMA_circular_normal_mode
* @{
*/
#define DMA_MODE_CIRCULAR ((uint32_t)0x00000020)
#define DMA_MODE_NORMAL ((uint32_t)0x00000000)
#define IS_DMA_MODE(MODE) (((MODE) == DMA_MODE_CIRCULAR) || ((MODE) == DMA_MODE_NORMAL))
/**
* @}
*/
/** @addtogroup DMA_priority_level
* @{
*/
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)0x00003000)
#define DMA_PRIORITY_HIGH ((uint32_t)0x00002000)
#define DMA_PRIORITY_MEDIUM ((uint32_t)0x00001000)
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000)
#define IS_DMA_PRIORITY(PRIORITY) \
(((PRIORITY) == DMA_PRIORITY_VERY_HIGH) || ((PRIORITY) == DMA_PRIORITY_HIGH) \
|| ((PRIORITY) == DMA_PRIORITY_MEDIUM) || ((PRIORITY) == DMA_PRIORITY_LOW))
/**
* @}
*/
/** @addtogroup DMA_memory_to_memory
* @{
*/
#define DMA_M2M_ENABLE ((uint32_t)0x00004000)
#define DMA_M2M_DISABLE ((uint32_t)0x00000000)
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_ENABLE) || ((STATE) == DMA_M2M_DISABLE))
/**
* @}
*/
/** @addtogroup DMA_interrupts_definition
* @{
*/
#define DMA_INT_TXC ((uint32_t)0x00000002)
#define DMA_INT_HTX ((uint32_t)0x00000004)
#define DMA_INT_ERR ((uint32_t)0x00000008)
#define IS_DMA_CONFIG_INT(IT) ((((IT)&0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
#define DMA_INT_GLB1 ((uint32_t)0x00000001)
#define DMA_INT_TXC1 ((uint32_t)0x00000002)
#define DMA_INT_HTX1 ((uint32_t)0x00000004)
#define DMA_INT_ERR1 ((uint32_t)0x00000008)
#define DMA_INT_GLB2 ((uint32_t)0x00000010)
#define DMA_INT_TXC2 ((uint32_t)0x00000020)
#define DMA_INT_HTX2 ((uint32_t)0x00000040)
#define DMA_INT_ERR2 ((uint32_t)0x00000080)
#define DMA_INT_GLB3 ((uint32_t)0x00000100)
#define DMA_INT_TXC3 ((uint32_t)0x00000200)
#define DMA_INT_HTX3 ((uint32_t)0x00000400)
#define DMA_INT_ERR3 ((uint32_t)0x00000800)
#define DMA_INT_GLB4 ((uint32_t)0x00001000)
#define DMA_INT_TXC4 ((uint32_t)0x00002000)
#define DMA_INT_HTX4 ((uint32_t)0x00004000)
#define DMA_INT_ERR4 ((uint32_t)0x00008000)
#define DMA_INT_GLB5 ((uint32_t)0x00010000)
#define DMA_INT_TXC5 ((uint32_t)0x00020000)
#define DMA_INT_HTX5 ((uint32_t)0x00040000)
#define DMA_INT_ERR5 ((uint32_t)0x00080000)
#define DMA_INT_GLB6 ((uint32_t)0x00100000)
#define DMA_INT_TXC6 ((uint32_t)0x00200000)
#define DMA_INT_HTX6 ((uint32_t)0x00400000)
#define DMA_INT_ERR6 ((uint32_t)0x00800000)
#define DMA_INT_GLB7 ((uint32_t)0x01000000)
#define DMA_INT_TXC7 ((uint32_t)0x02000000)
#define DMA_INT_HTX7 ((uint32_t)0x04000000)
#define DMA_INT_ERR7 ((uint32_t)0x08000000)
#define DMA_INT_GLB8 ((uint32_t)0x10000000)
#define DMA_INT_TXC8 ((uint32_t)0x20000000)
#define DMA_INT_HTX8 ((uint32_t)0x40000000)
#define DMA_INT_ERR8 ((uint32_t)0x80000000)
#define IS_DMA_CLR_INT(IT) ((IT) != 0x00)
#define IS_DMA_GET_IT(IT) \
(((IT) == DMA_INT_GLB1) || ((IT) == DMA_INT_TXC1) || ((IT) == DMA_INT_HTX1) || ((IT) == DMA_INT_ERR1) \
|| ((IT) == DMA_INT_GLB2) || ((IT) == DMA_INT_TXC2) || ((IT) == DMA_INT_HTX2) || ((IT) == DMA_INT_ERR2) \
|| ((IT) == DMA_INT_GLB3) || ((IT) == DMA_INT_TXC3) || ((IT) == DMA_INT_HTX3) || ((IT) == DMA_INT_ERR3) \
|| ((IT) == DMA_INT_GLB4) || ((IT) == DMA_INT_TXC4) || ((IT) == DMA_INT_HTX4) || ((IT) == DMA_INT_ERR4) \
|| ((IT) == DMA_INT_GLB5) || ((IT) == DMA_INT_TXC5) || ((IT) == DMA_INT_HTX5) || ((IT) == DMA_INT_ERR5) \
|| ((IT) == DMA_INT_GLB6) || ((IT) == DMA_INT_TXC6) || ((IT) == DMA_INT_HTX6) || ((IT) == DMA_INT_ERR6) \
|| ((IT) == DMA_INT_GLB7) || ((IT) == DMA_INT_TXC7) || ((IT) == DMA_INT_HTX7) || ((IT) == DMA_INT_ERR7) \
|| ((IT) == DMA_INT_GLB8) || ((IT) == DMA_INT_TXC8) || ((IT) == DMA_INT_HTX8) || ((IT) == DMA_INT_ERR8))
/**
* @}
*/
/** @addtogroup DMA_flags_definition
* @{
*/
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA_FLAG_GL8 ((uint32_t)0x10000000)
#define DMA_FLAG_TC8 ((uint32_t)0x20000000)
#define DMA_FLAG_HT8 ((uint32_t)0x40000000)
#define DMA_FLAG_TE8 ((uint32_t)0x80000000)
#define IS_DMA_CLEAR_FLAG(FLAG) ((FLAG) != 0x00)
#define IS_DMA_GET_FLAG(FLAG) \
(((FLAG) == DMA_FLAG_GL1) || ((FLAG) == DMA_FLAG_TC1) || ((FLAG) == DMA_FLAG_HT1) || ((FLAG) == DMA_FLAG_TE1) \
|| ((FLAG) == DMA_FLAG_GL2) || ((FLAG) == DMA_FLAG_TC2) || ((FLAG) == DMA_FLAG_HT2) \
|| ((FLAG) == DMA_FLAG_TE2) || ((FLAG) == DMA_FLAG_GL3) || ((FLAG) == DMA_FLAG_TC3) \
|| ((FLAG) == DMA_FLAG_HT3) || ((FLAG) == DMA_FLAG_TE3) || ((FLAG) == DMA_FLAG_GL4) \
|| ((FLAG) == DMA_FLAG_TC4) || ((FLAG) == DMA_FLAG_HT4) || ((FLAG) == DMA_FLAG_TE4) \
|| ((FLAG) == DMA_FLAG_GL5) || ((FLAG) == DMA_FLAG_TC5) || ((FLAG) == DMA_FLAG_HT5) \
|| ((FLAG) == DMA_FLAG_TE5) || ((FLAG) == DMA_FLAG_GL6) || ((FLAG) == DMA_FLAG_TC6) \
|| ((FLAG) == DMA_FLAG_HT6) || ((FLAG) == DMA_FLAG_TE6) || ((FLAG) == DMA_FLAG_GL7) \
|| ((FLAG) == DMA_FLAG_TC7) || ((FLAG) == DMA_FLAG_HT7) || ((FLAG) == DMA_FLAG_TE7) \
|| ((FLAG) == DMA_FLAG_GL8) || ((FLAG) == DMA_FLAG_TC8) || ((FLAG) == DMA_FLAG_HT8) \
|| ((FLAG) == DMA_FLAG_TE8))
/**
* @}
*/
/** @addtogroup DMA_Buffer_Size
* @{
*/
#define IS_DMA_BUF_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
/**
* @}
*/
/** @addtogroup DMA_remap_request_definition
* @{
*/
#define DMA_REMAP_ADC1 ((uint32_t)0x00000000)
#define DMA_REMAP_USART1_TX ((uint32_t)0x00000001)
#define DMA_REMAP_USART1_RX ((uint32_t)0x00000002)
#define DMA_REMAP_USART2_TX ((uint32_t)0x00000003)
#define DMA_REMAP_USART2_RX ((uint32_t)0x00000004)
#define DMA_REMAP_USART3_TX ((uint32_t)0x00000005)
#define DMA_REMAP_USART3_RX ((uint32_t)0x00000006)
#define DMA_REMAP_UART4_TX ((uint32_t)0x00000007)
#define DMA_REMAP_UART4_RX ((uint32_t)0x00000008)
#define DMA_REMAP_UART5_TX ((uint32_t)0x00000009)
#define DMA_REMAP_UART5_RX ((uint32_t)0x0000000A)
#define DMA_REMAP_LPUART_TX ((uint32_t)0x0000000B)
#define DMA_REMAP_LPUART_RX ((uint32_t)0x0000000C)
#define DMA_REMAP_SPI1_TX ((uint32_t)0x0000000D)
#define DMA_REMAP_SPI1_RX ((uint32_t)0x0000000E)
#define DMA_REMAP_SPI2_TX ((uint32_t)0x0000000F)
#define DMA_REMAP_SPI2_RX ((uint32_t)0x00000010)
#define DMA_REMAP_I2C1_TX ((uint32_t)0x00000011)
#define DMA_REMAP_I2C1_RX ((uint32_t)0x00000012)
#define DMA_REMAP_I2C2_TX ((uint32_t)0x00000013)
#define DMA_REMAP_I2C2_RX ((uint32_t)0x00000014)
#define DMA_REMAP_DAC1 ((uint32_t)0x00000015)
#define DMA_REMAP_TIM1_CH1 ((uint32_t)0x00000016)
#define DMA_REMAP_TIM1_CH2 ((uint32_t)0x00000017)
#define DMA_REMAP_TIM1_CH3 ((uint32_t)0x00000018)
#define DMA_REMAP_TIM1_CH4 ((uint32_t)0x00000019)
#define DMA_REMAP_TIM1_COM ((uint32_t)0x0000001A)
#define DMA_REMAP_TIM1_UP ((uint32_t)0x0000001B)
#define DMA_REMAP_TIM1_TRIG ((uint32_t)0x0000001C)
#define DMA_REMAP_TIM2_CH1 ((uint32_t)0x0000001D)
#define DMA_REMAP_TIM2_CH2 ((uint32_t)0x0000001E)
#define DMA_REMAP_TIM2_CH3 ((uint32_t)0x0000001F)
#define DMA_REMAP_TIM2_CH4 ((uint32_t)0x00000020)
#define DMA_REMAP_TIM2_UP ((uint32_t)0x00000021)
#define DMA_REMAP_TIM3_CH1 ((uint32_t)0x00000022)
#define DMA_REMAP_TIM3_CH3 ((uint32_t)0x00000023)
#define DMA_REMAP_TIM3_CH4 ((uint32_t)0x00000024)
#define DMA_REMAP_TIM3_UP ((uint32_t)0x00000025)
#define DMA_REMAP_TIM3_TRIG ((uint32_t)0x00000026)
#define DMA_REMAP_TIM4_CH1 ((uint32_t)0x00000027)
#define DMA_REMAP_TIM4_CH2 ((uint32_t)0x00000028)
#define DMA_REMAP_TIM4_CH3 ((uint32_t)0x00000029)
#define DMA_REMAP_TIM4_UP ((uint32_t)0x0000002A)
#define DMA_REMAP_TIM5_CH1 ((uint32_t)0x0000002B)
#define DMA_REMAP_TIM5_CH2 ((uint32_t)0x0000002C)
#define DMA_REMAP_TIM5_CH3 ((uint32_t)0x0000002D)
#define DMA_REMAP_TIM5_CH4 ((uint32_t)0x0000002E)
#define DMA_REMAP_TIM5_UP ((uint32_t)0x0000002F)
#define DMA_REMAP_TIM5_TRIG ((uint32_t)0x00000030)
#define DMA_REMAP_TIM6_UP ((uint32_t)0x00000031)
#define DMA_REMAP_TIM7_UP ((uint32_t)0x00000032)
#define DMA_REMAP_TIM8_CH1 ((uint32_t)0x00000033)
#define DMA_REMAP_TIM8_CH2 ((uint32_t)0x00000034)
#define DMA_REMAP_TIM8_CH3 ((uint32_t)0x00000035)
#define DMA_REMAP_TIM8_CH4 ((uint32_t)0x00000036)
#define DMA_REMAP_TIM8_COM ((uint32_t)0x00000037)
#define DMA_REMAP_TIM8_UP ((uint32_t)0x00000038)
#define DMA_REMAP_TIM8_TRIG ((uint32_t)0x00000039)
#define DMA_REMAP_TIM9_CH1 ((uint32_t)0x0000003A)
#define DMA_REMAP_TIM9_TRIG ((uint32_t)0x0000003B)
#define DMA_REMAP_TIM9_CH3 ((uint32_t)0x0000003C)
#define DMA_REMAP_TIM9_CH4 ((uint32_t)0x0000003D)
#define DMA_REMAP_TIM9_UP ((uint32_t)0x0000003E)
#define IS_DMA_REMAP(FLAG) \
(((FLAG) == DMA_REMAP_ADC1) || ((FLAG) == DMA_REMAP_USART1_TX) || ((FLAG) == DMA_REMAP_USART1_RX) \
|| ((FLAG) == DMA_REMAP_USART2_TX) || ((FLAG) == DMA_REMAP_USART2_RX) || ((FLAG) == DMA_REMAP_USART3_TX) \
|| ((FLAG) == DMA_REMAP_USART3_RX) || ((FLAG) == DMA_REMAP_UART4_TX) || ((FLAG) == DMA_REMAP_UART4_RX) \
|| ((FLAG) == DMA_REMAP_UART5_TX) || ((FLAG) == DMA_REMAP_UART5_RX) || ((FLAG) == DMA_REMAP_LPUART_TX) \
|| ((FLAG) == DMA_REMAP_LPUART_RX) || ((FLAG) == DMA_REMAP_SPI1_TX) || ((FLAG) == DMA_REMAP_SPI1_RX) \
|| ((FLAG) == DMA_REMAP_SPI2_TX) || ((FLAG) == DMA_REMAP_SPI2_RX) || ((FLAG) == DMA_REMAP_I2C1_TX) \
|| ((FLAG) == DMA_REMAP_I2C1_RX) || ((FLAG) == DMA_REMAP_I2C2_TX) || ((FLAG) == DMA_REMAP_I2C2_RX) \
|| ((FLAG) == DMA_REMAP_DAC1) || ((FLAG) == DMA_REMAP_TIM1_CH1) || ((FLAG) == DMA_REMAP_TIM1_CH2) \
|| ((FLAG) == DMA_REMAP_TIM1_CH3) || ((FLAG) == DMA_REMAP_TIM1_CH4) || ((FLAG) == DMA_REMAP_TIM1_COM) \
|| ((FLAG) == DMA_REMAP_TIM1_UP) || ((FLAG) == DMA_REMAP_TIM1_TRIG)|| ((FLAG) == DMA_REMAP_TIM2_CH1) \
|| ((FLAG) == DMA_REMAP_TIM2_CH2) || ((FLAG) == DMA_REMAP_TIM2_CH3) || ((FLAG) == DMA_REMAP_TIM2_CH4) \
|| ((FLAG) == DMA_REMAP_TIM2_UP) || ((FLAG) == DMA_REMAP_TIM3_CH1) || ((FLAG) == DMA_REMAP_TIM3_CH3) \
|| ((FLAG) == DMA_REMAP_TIM3_CH4) || ((FLAG) == DMA_REMAP_TIM3_UP) || ((FLAG) == DMA_REMAP_TIM3_TRIG) \
|| ((FLAG) == DMA_REMAP_TIM4_CH1) || ((FLAG) == DMA_REMAP_TIM4_CH2) || ((FLAG) == DMA_REMAP_TIM4_CH3) \
|| ((FLAG) == DMA_REMAP_TIM4_UP) || ((FLAG) == DMA_REMAP_TIM5_CH1) || ((FLAG) == DMA_REMAP_TIM5_CH2) \
|| ((FLAG) == DMA_REMAP_TIM5_CH3) || ((FLAG) == DMA_REMAP_TIM5_CH4) || ((FLAG) == DMA_REMAP_TIM5_UP) \
|| ((FLAG) == DMA_REMAP_TIM5_TRIG)|| ((FLAG) == DMA_REMAP_TIM6_UP) || ((FLAG) == DMA_REMAP_TIM7_UP) \
|| ((FLAG) == DMA_REMAP_TIM8_CH1) || ((FLAG) == DMA_REMAP_TIM8_CH2) || ((FLAG) == DMA_REMAP_TIM8_CH3) \
|| ((FLAG) == DMA_REMAP_TIM8_CH4) || ((FLAG) == DMA_REMAP_TIM8_COM) || ((FLAG) == DMA_REMAP_TIM8_UP) \
|| ((FLAG) == DMA_REMAP_TIM8_TRIG)|| ((FLAG) == DMA_REMAP_TIM9_CH1) || ((FLAG) == DMA_REMAP_TIM9_TRIG) \
|| ((FLAG) == DMA_REMAP_TIM9_CH3) || ((FLAG) == DMA_REMAP_TIM9_CH4) || ((FLAG) == DMA_REMAP_TIM9_UP))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMA_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
void DMA_DeInit(DMA_ChannelType* DMAChx);
void DMA_Init(DMA_ChannelType* DMAChx, DMA_InitType* DMA_InitParam);
void DMA_StructInit(DMA_InitType* DMA_InitParam);
void DMA_EnableChannel(DMA_ChannelType* DMAChx, FunctionalState Cmd);
void DMA_ConfigInt(DMA_ChannelType* DMAChx, uint32_t DMAInt, FunctionalState Cmd);
void DMA_SetCurrDataCounter(DMA_ChannelType* DMAChx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_ChannelType* DMAChx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAFlag, DMA_Module* DMAy);
void DMA_ClearFlag(uint32_t DMAFlag, DMA_Module* DMAy);
INTStatus DMA_GetIntStatus(uint32_t DMA_IT, DMA_Module* DMAy);
void DMA_ClrIntPendingBit(uint32_t DMA_IT, DMA_Module* DMAy);
void DMA_RequestRemap(uint32_t DMA_REMAP, DMA_Module* DMAy, DMA_ChannelType* DMAChx, FunctionalState Cmd);
#ifdef __cplusplus
}
#endif
#endif /*__N32G43X_DMA_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_exti.h
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@@ -0,0 +1,232 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_exti.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_EXTI_H__
#define __N32G43X_EXTI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** @addtogroup EXTI_Exported_Types
* @{
*/
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTI_ModeType;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTI_TriggerType;
#define IS_EXTI_TRIGGER(TRIGGER) \
(((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) \
|| ((TRIGGER) == EXTI_Trigger_Rising_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTI_ModeType EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_ModeType */
EXTI_TriggerType EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_ModeType */
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitType;
/**
* @}
*/
/** @addtogroup EXTI_Exported_Constants
* @{
*/
/** @addtogroup EXTI_Lines
* @{
*/
#define EXTI_LINE0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
#define EXTI_LINE1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
#define EXTI_LINE2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
#define EXTI_LINE3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
#define EXTI_LINE4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
#define EXTI_LINE5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
#define EXTI_LINE6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
#define EXTI_LINE7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
#define EXTI_LINE8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
#define EXTI_LINE9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
#define EXTI_LINE10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
#define EXTI_LINE11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
#define EXTI_LINE12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
#define EXTI_LINE13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
#define EXTI_LINE14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
#define EXTI_LINE15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
#define EXTI_LINE16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the USB Device/USB OTG FS Wakeup from suspend event */
#define EXTI_LINE18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the RTC Alarm event */
#define EXTI_LINE19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the RTC Time stamp event */
#define EXTI_LINE20 ((uint32_t)0x100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */
#define EXTI_LINE21 ((uint32_t)0x200000) /*!< External interrupt line 21 Connected to the COMP1 Global interrupt */
#define EXTI_LINE22 ((uint32_t)0x400000) /*!< External interrupt line 22 Connected to the COMP2 Global interrupt */
#define EXTI_LINE23 ((uint32_t)0x800000) /*!< External interrupt line 23 Connected to the LPUART Global interrupt */
#define EXTI_LINE24 ((uint32_t)0x1000000) /*!< External interrupt line 24 Connected to the LPTIM Global interrupt */
#define EXTI_LINE25 ((uint32_t)0x2000000) /*!< External interrupt line 25 Connected to the TSC Global interrupt */
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xF0000000) == 0x00) && ((LINE) != (uint16_t)0x00))
#define IS_GET_EXTI_LINE(LINE) \
(((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) \
|| ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) \
|| ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) \
|| ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) \
|| ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) \
|| ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) \
|| ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25))
/**
* @}
*/
/** @addtogroup EXTI_TSSEL_Line
* @{
*/
#define EXTI_TSSEL_LINE_MASK ((uint32_t)0x00000)
#define EXTI_TSSEL_LINE0 ((uint32_t)0x00000) /*!< External interrupt line 0 */
#define EXTI_TSSEL_LINE1 ((uint32_t)0x00001) /*!< External interrupt line 1 */
#define EXTI_TSSEL_LINE2 ((uint32_t)0x00002) /*!< External interrupt line 2 */
#define EXTI_TSSEL_LINE3 ((uint32_t)0x00003) /*!< External interrupt line 3 */
#define EXTI_TSSEL_LINE4 ((uint32_t)0x00004) /*!< External interrupt line 4 */
#define EXTI_TSSEL_LINE5 ((uint32_t)0x00005) /*!< External interrupt line 5 */
#define EXTI_TSSEL_LINE6 ((uint32_t)0x00006) /*!< External interrupt line 6 */
#define EXTI_TSSEL_LINE7 ((uint32_t)0x00007) /*!< External interrupt line 7 */
#define EXTI_TSSEL_LINE8 ((uint32_t)0x00008) /*!< External interrupt line 8 */
#define EXTI_TSSEL_LINE9 ((uint32_t)0x00009) /*!< External interrupt line 9 */
#define EXTI_TSSEL_LINE10 ((uint32_t)0x0000A) /*!< External interrupt line 10 */
#define EXTI_TSSEL_LINE11 ((uint32_t)0x0000B) /*!< External interrupt line 11 */
#define EXTI_TSSEL_LINE12 ((uint32_t)0x0000C) /*!< External interrupt line 12 */
#define EXTI_TSSEL_LINE13 ((uint32_t)0x0000D) /*!< External interrupt line 13 */
#define EXTI_TSSEL_LINE14 ((uint32_t)0x0000E) /*!< External interrupt line 14 */
#define EXTI_TSSEL_LINE15 ((uint32_t)0x0000F) /*!< External interrupt line 15 */
#define IS_EXTI_TSSEL_LINE(LINE) \
(((LINE) == EXTI_TSSEL_LINE0) || ((LINE) == EXTI_TSSEL_LINE1) || ((LINE) == EXTI_TSSEL_LINE2) \
|| ((LINE) == EXTI_TSSEL_LINE3) || ((LINE) == EXTI_TSSEL_LINE4) || ((LINE) == EXTI_TSSEL_LINE5) \
|| ((LINE) == EXTI_TSSEL_LINE6) || ((LINE) == EXTI_TSSEL_LINE7) || ((LINE) == EXTI_TSSEL_LINE8) \
|| ((LINE) == EXTI_TSSEL_LINE9) || ((LINE) == EXTI_TSSEL_LINE10) || ((LINE) == EXTI_TSSEL_LINE11) \
|| ((LINE) == EXTI_TSSEL_LINE12) || ((LINE) == EXTI_TSSEL_LINE13) || ((LINE) == EXTI_TSSEL_LINE14) \
|| ((LINE) == EXTI_TSSEL_LINE15))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup EXTI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
void EXTI_DeInit(void);
void EXTI_InitPeripheral(EXTI_InitType* EXTI_InitStruct);
void EXTI_InitStruct(EXTI_InitType* EXTI_InitStruct);
void EXTI_TriggerSWInt(uint32_t EXTI_Line);
FlagStatus EXTI_GetStatusFlag(uint32_t EXTI_Line);
void EXTI_ClrStatusFlag(uint32_t EXTI_Line);
INTStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClrITPendBit(uint32_t EXTI_Line);
void EXTI_RTCTimeStampSel(uint32_t EXTI_TSSEL_Line);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43X_EXTI_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_flash.h
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bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_gpio.h
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bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_i2c.h
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bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_iwdg.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_iwdg.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_IWDG_H__
#define __N32G43X_IWDG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup IWDG
* @{
*/
/** @addtogroup IWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Constants
* @{
*/
/** @addtogroup IWDG_WriteAccess
* @{
*/
#define IWDG_WRITE_ENABLE ((uint16_t)0x5555)
#define IWDG_WRITE_DISABLE ((uint16_t)0x0000)
#define IS_IWDG_WRITE(ACCESS) (((ACCESS) == IWDG_WRITE_ENABLE) || ((ACCESS) == IWDG_WRITE_DISABLE))
/**
* @}
*/
/** @addtogroup IWDG_prescaler
* @{
*/
#define IWDG_PRESCALER_DIV4 ((uint8_t)0x00)
#define IWDG_PRESCALER_DIV8 ((uint8_t)0x01)
#define IWDG_PRESCALER_DIV16 ((uint8_t)0x02)
#define IWDG_PRESCALER_DIV32 ((uint8_t)0x03)
#define IWDG_PRESCALER_DIV64 ((uint8_t)0x04)
#define IWDG_PRESCALER_DIV128 ((uint8_t)0x05)
#define IWDG_PRESCALER_DIV256 ((uint8_t)0x06)
#define IS_IWDG_PRESCALER_DIV(PRESCALER) \
(((PRESCALER) == IWDG_PRESCALER_DIV4) || ((PRESCALER) == IWDG_PRESCALER_DIV8) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV16) || ((PRESCALER) == IWDG_PRESCALER_DIV32) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV64) || ((PRESCALER) == IWDG_PRESCALER_DIV128) \
|| ((PRESCALER) == IWDG_PRESCALER_DIV256))
/**
* @}
*/
/** @addtogroup IWDG_Flag
* @{
*/
#define IWDG_PVU_FLAG ((uint16_t)0x0001)
#define IWDG_CRVU_FLAG ((uint16_t)0x0002)
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_PVU_FLAG) || ((FLAG) == IWDG_CRVU_FLAG))
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
void IWDG_WriteConfig(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescalerDiv(uint8_t IWDG_Prescaler);
void IWDG_CntReload(uint16_t Reload);
void IWDG_ReloadKey(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43X_IWDG_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lptim.h
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/** ----------------------------------------------------------------------------
* Nationz Technology Software Support - NATIONZ -
* -----------------------------------------------------------------------------
* Copyright (c) 2022, Nationz Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaiimer below.
*
* - Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the disclaimer below in the documentation and/or
* other materials provided with the distribution.
*
* Nationz's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONZ "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* -----------------------------------------------------------------------------
*/
/** ****************************************************************************
* @copyright Nationz Co.,Ltd
* Copyright (c) 2019 All Rights Reserved
*******************************************************************************
* @file n32g43x_lptim.h
* @author
* @date
* @version v1.2.0
* @brief
******************************************************************************/
#ifndef __n32g43x_LPTIM_H
#define __n32g43x_LPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "n32g43x.h"
/** @addtogroup n32g43x_StdPeriph_Driver
* @{
*/
/** @addtogroup LPTIM
* @{
*/
//#if defined (LPTIM)
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LPTIM_ES_INIT LPTIM Exported Init structure
* @{
*/
/**
* @brief LPTIM Init structure definition
*/
typedef struct
{
uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
This parameter can be a value of @ref LPTIM_EC_CLK_SOURCE.
This feature can be modified afterwards using unitary function @ref LPTIM_SetClockSource().*/
uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
This parameter can be a value of @ref LPTIM_EC_PRESCALER.
This feature can be modified afterwards using using unitary function @ref LPTIM_SetPrescaler().*/
uint32_t Waveform; /*!< Specifies the waveform shape.
This parameter can be a value of @ref LPTIM_EC_OUTPUT_WAVEFORM.
This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
uint32_t Polarity; /*!< Specifies waveform polarity.
This parameter can be a value of @ref LPTIM_EC_OUTPUT_POLARITY.
This feature can be modified afterwards using unitary function @ref LPTIM_ConfigOutput().*/
} LPTIM_InitType;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
* @{
*/
/** @defgroup LPTIM_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LPTIM_ReadReg function
* @{
*/
#define LPTIM_INTSTS_CMPM_FLAG LPTIM_INTSTS_CMPM /*!< Compare match */
#define LPTIM_INTSTS_ARRM_FLAG LPTIM_INTSTS_ARRM /*!< Autoreload match */
#define LPTIM_INTSTS_EXTRIG_FLAG LPTIM_INTSTS_EXTRIG /*!< External trigger edge event */
#define LPTIM_INTSTS_CMPUPD_FLAG LPTIM_INTSTS_CMPUPD /*!< Compare register update OK */
#define LPTIM_INTSTS_ARRUPD_FLAG LPTIM_INTSTS_ARRUPD /*!< Autoreload register update OK */
#define LPTIM_INTSTS_UP_FLAG LPTIM_INTSTS_UP /*!< Counter direction change down to up */
#define LPTIM_INTSTS_DOWN_FLAG LPTIM_INTSTS_DOWN /*!< Counter direction change up to down */
/**
* @}
*/
/** @defgroup LPTIM_EC_IT IT Defines
* @brief IT defines which can be used with LPTIM_ReadReg and LPTIM_WriteReg functions
* @{
*/
#define LPTIM_INTEN_CMPMIE_ENABLE LPTIM_INTEN_CMPMIE /*!< Compare match Interrupt Enable */
#define LPTIM_INTEN_ARRMIE_ENABLE LPTIM_INTEN_ARRMIE /*!< Autoreload match Interrupt Enable */
#define LPTIM_INTEN_EXTRIGIE_ENABLE LPTIM_INTEN_EXTRIGIE /*!< External trigger valid edge Interrupt Enable */
#define LPTIM_INTEN_CMPUPDIE_ENABLE LPTIM_INTEN_CMPUPDIE /*!< Compare register update OK Interrupt Enable */
#define LPTIM_INTEN_ARRUPDIE_ENABLE LPTIM_INTEN_ARRUPDIE /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_INTEN_UPIE_ENABLE LPTIM_INTEN_UPIE /*!< Direction change to UP Interrupt Enable */
#define LPTIM_INTEN_DOWNIE_ENABLE LPTIM_INTEN_DOWNIE /*!< Direction change to down Interrupt Enable */
/**
* @}
*/
/** @defgroup LPTIM_EC_OPERATING_MODE Operating Mode
* @{
*/
#define LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CTRL_TSTCM /*!<LP Timer starts in continuous mode*/
#define LPTIM_OPERATING_MODE_ONESHOT LPTIM_CTRL_SNGMST /*!<LP Tilmer starts in single mode*/
/**
* @}
*/
/** @defgroup LPTIM_EC_UPDATE_MODE Update Mode
* @{
*/
#define LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
#define LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFG_RELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
/**
* @}
*/
/** @defgroup LPTIM_EC_COUNTER_MODE Counter Mode
* @{
*/
#define LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
#define LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFG_CNTMEN /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
#define LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
#define LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFG_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
*/
/** @defgroup LPTIM_EC_OUTPUT_POLARITY Output Polarity
* @{
*/
#define LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
#define LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFG_WAVEPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
/**
* @}
*/
/** @defgroup LPTIM_EC_PRESCALER Prescaler Value
* @{
*/
#define LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
#define LPTIM_PRESCALER_DIV2 LPTIM_CFG_CLKPRE_0 /*!<Prescaler division factor is set to 2*/
#define LPTIM_PRESCALER_DIV4 LPTIM_CFG_CLKPRE_1 /*!<Prescaler division factor is set to 4*/
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFG_CLKPRE_1 | LPTIM_CFG_CLKPRE_0) /*!<Prescaler division factor is set to 8*/
#define LPTIM_PRESCALER_DIV16 LPTIM_CFG_CLKPRE_2 /*!<Prescaler division factor is set to 16*/
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFG_CLKPRE_2 | LPTIM_CFG_CLKPRE_0) /*!<Prescaler division factor is set to 32*/
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFG_CLKPRE_2 | LPTIM_CFG_CLKPRE_1) /*!<Prescaler division factor is set to 64*/
#define LPTIM_PRESCALER_DIV128 LPTIM_CFG_CLKPRE /*!<Prescaler division factor is set to 128*/
/**
* @}
*/
/** @defgroup LPTIM_EC_TRIG_SOURCE Trigger Source
* @{
*/
#define LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
#define LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFG_TRGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
#define LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFG_TRGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
#define LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFG_TRGSEL_1 | LPTIM_CFG_TRGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
#define LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFG_TRGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
#define LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFG_TRGSEL_2 | LPTIM_CFG_TRGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
#define LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFG_TRGSEL_2 | LPTIM_CFG_TRGSEL_1) /*!<External input trigger is connected to COMP1 output*/
#define LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFG_TRGSEL /*!<External input trigger is connected to COMP2 output*/
/**
* @}
*/
/** @defgroup LPTIM_EC_TRIG_FILTER Trigger Filter
* @{
*/
#define LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
#define LPTIM_TRIG_FILTER_2 LPTIM_CFG_TRIGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
#define LPTIM_TRIG_FILTER_4 LPTIM_CFG_TRIGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
#define LPTIM_TRIG_FILTER_8 LPTIM_CFG_TRIGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
/**
* @}
*/
/** @defgroup LPTIM_EC_TRIG_POLARITY Trigger Polarity
* @{
*/
#define LPTIM_TRIG_POLARITY_RISING LPTIM_CFG_TRGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
#define LPTIM_TRIG_POLARITY_FALLING LPTIM_CFG_TRGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
#define LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFG_TRGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
/**
* @}
*/
/** @defgroup LPTIM_EC_CLK_SOURCE Clock Source
* @{
*/
#define LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
#define LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFG_CLKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_EC_CLK_FILTER Clock Filter
* @{
*/
#define LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
#define LPTIM_CLK_FILTER_2 LPTIM_CFG_CLKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
#define LPTIM_CLK_FILTER_4 LPTIM_CFG_CLKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
#define LPTIM_CLK_FILTER_8 LPTIM_CFG_CLKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
/**
* @}
*/
/** @defgroup LPTIM_EC_CLK_POLARITY Clock Polarity
* @{
*/
#define LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LPTIM_CLK_POLARITY_FALLING LPTIM_CFG_CLKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFG_CLKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/** @defgroup LPTIM_EC_ENCODER_MODE Encoder Mode
* @{
*/
#define LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LPTIM_ENCODER_MODE_FALLING LPTIM_CFG_CLKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFG_CLKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @defgroup LPTIM_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->(__REG__), (__VALUE__))
/**
* @brief Read a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->(__REG__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
/** @defgroup LPTIM_EF_Init Initialisation and deinitialisation functions
* @{
*/
void LPTIM_DeInit(LPTIM_Module *LPTIMx);
void LPTIM_StructInit(LPTIM_InitType *LPTIM_InitStruct);
ErrorStatus LPTIM_Init(LPTIM_Module *LPTIMx, LPTIM_InitType *LPTIM_InitStruct);
void LPTIM_Disable(LPTIM_Module *LPTIMx);
void LPTIM_Enable(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabled(LPTIM_Module *LPTIMx);
void LPTIM_StartCounter(LPTIM_Module *LPTIMx, uint32_t OperatingMode);
void LPTIM_SetUpdateMode(LPTIM_Module *LPTIMx, uint32_t UpdateMode);
uint32_t LPTIM_GetUpdateMode(LPTIM_Module *LPTIMx);
void LPTIM_SetAutoReload(LPTIM_Module *LPTIMx, uint32_t AutoReload);
uint32_t LPTIM_GetAutoReload(LPTIM_Module *LPTIMx);
void LPTIM_SetCompare(LPTIM_Module *LPTIMx, uint32_t CompareValue);
uint32_t LPTIM_GetCompare(LPTIM_Module *LPTIMx);
uint32_t LPTIM_GetCounter(LPTIM_Module *LPTIMx);
void LPTIM_SetCounterMode(LPTIM_Module *LPTIMx, uint32_t CounterMode);
uint32_t LPTIM_GetCounterMode(LPTIM_Module *LPTIMx);
void LPTIM_ConfigOutput(LPTIM_Module *LPTIMx, uint32_t Waveform, uint32_t Polarity);
void LPTIM_SetWaveform(LPTIM_Module *LPTIMx, uint32_t Waveform);
uint32_t LPTIM_GetWaveform(LPTIM_Module *LPTIMx);
void LPTIM_SetPolarity(LPTIM_Module *LPTIMx, uint32_t Polarity);
uint32_t LPTIM_GetPolarity(LPTIM_Module *LPTIMx);
void LPTIM_SetPrescaler(LPTIM_Module *LPTIMx, uint32_t Prescaler);
uint32_t LPTIM_GetPrescaler(LPTIM_Module *LPTIMx);
void LPTIM_EnableTimeout(LPTIM_Module *LPTIMx);
void LPTIM_DisableTimeout(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledTimeout(LPTIM_Module *LPTIMx);
void LPTIM_TrigSw(LPTIM_Module *LPTIMx);
void LPTIM_ConfigTrigger(LPTIM_Module *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity);
uint32_t LPTIM_GetTriggerSource(LPTIM_Module *LPTIMx);
uint32_t LPTIM_GetTriggerFilter(LPTIM_Module *LPTIMx);
uint32_t LPTIM_GetTriggerPolarity(LPTIM_Module *LPTIMx);
void LPTIM_SetClockSource(LPTIM_Module *LPTIMx, uint32_t ClockSource);
uint32_t LPTIM_GetClockSource(LPTIM_Module *LPTIMx);
void LPTIM_ConfigClock(LPTIM_Module *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity);
uint32_t LPTIM_GetClockPolarity(LPTIM_Module *LPTIMx);
uint32_t LPTIM_GetClockFilter(LPTIM_Module *LPTIMx);
void LPTIM_SetEncoderMode(LPTIM_Module *LPTIMx, uint32_t EncoderMode);
uint32_t LPTIM_GetEncoderMode(LPTIM_Module *LPTIMx);
void LPTIM_EnableEncoderMode(LPTIM_Module *LPTIMx);
void LPTIM_DisableEncoderMode(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledEncoderMode(LPTIM_Module *LPTIMx);
void LPTIM_ClearFLAG_CMPM(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_CMPM(LPTIM_Module *LPTIMx);
void LPTIM_ClearFLAG_ARRM(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_ARRM(LPTIM_Module *LPTIMx);
void LPTIM_ClearFlag_EXTTRIG(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_EXTTRIG(LPTIM_Module *LPTIMx);
void LPTIM_ClearFlag_CMPOK(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_CMPOK(LPTIM_Module *LPTIMx);
void LPTIM_ClearFlag_ARROK(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_ARROK(LPTIM_Module *LPTIMx);
void LPTIM_ClearFlag_UP(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_UP(LPTIM_Module *LPTIMx);
void LPTIM_ClearFlag_DOWN(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsActiveFlag_DOWN(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_CMPM(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_CMPM(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_CMPM(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_ARRM(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_ARRM(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_ARRM(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_EXTTRIG(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_EXTTRIG(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_EXTTRIG(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_CMPOK(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_CMPOK(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_CMPOK(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_ARROK(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_ARROK(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_ARROK(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_UP(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_UP(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_UP(LPTIM_Module *LPTIMx);
void LPTIM_EnableIT_DOWN(LPTIM_Module *LPTIMx);
void LPTIM_DisableIT_DOWN(LPTIM_Module *LPTIMx);
uint32_t LPTIM_IsEnabledIT_DOWN(LPTIM_Module *LPTIMx);
void LPTIM_EnableNoEncoderMode(LPTIM_Module *LPTIMx);
/**
* @}
*/
/**
* @}
*/
//#endif /* LPTIM */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __n32g43x_LPTIM_H */
/******************* (C) COPYRIGHT 2019 NATIONZ *****END OF FILE****/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_lpuart.h
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_lpuart.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43x_LPUART_H__
#define __N32G43x_LPUART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup LPUART
* @{
*/
/** @addtogroup LPUART_Exported_Types
* @{
*/
/**
* @brief LPUART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the LPUART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((CLK) / (LPUART_InitStruct->BaudRate)))
- FractionalDivider */
uint16_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (only support
8 data bits). */
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref Mode */
uint16_t RtsThreshold; /* Specifies RTS Threshold.
This parameter can be a value of @ref RtsThreshold */
uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref LPUART_Hardware_Flow_Control */
} LPUART_InitType;
/**
* @}
*/
/** @addtogroup LPUART_Exported_Constants
* @{
*/
/** @addtogroup Parity
* @{
*/
#define LPUART_PE_NO ((uint16_t)0x0008)
#define LPUART_PE_EVEN ((uint16_t)0x0000)
#define LPUART_PE_ODD ((uint16_t)0x0001)
#define IS_LPUART_PARITY(PARITY) (((PARITY) == LPUART_PE_NO) || ((PARITY) == LPUART_PE_EVEN) || ((PARITY) == LPUART_PE_ODD))
/**
* @}
*/
/** @addtogroup Mode
* @{
*/
#define LPUART_MODE_RX ((uint16_t)0x0000)
#define LPUART_MODE_TX ((uint16_t)0x0002)
#define IS_LPUART_MODE(MODE) (((MODE) == LPUART_MODE_RX) || ((MODE) == LPUART_MODE_TX))
/**
* @}
*/
/** @addtogroup RtsThreshold
* @{
*/
#define LPUART_RTSTH_FIFOHF ((uint16_t)0x0000)
#define LPUART_RTSTH_FIFO3QF ((uint16_t)0x0100)
#define LPUART_RTSTH_FIFOFU ((uint16_t)0x0200)
#define IS_LPUART_RTSTHRESHOLD(RTSTHRESHOLD) \
(((RTSTHRESHOLD) == LPUART_RTSTH_FIFOHF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFO3QF) || ((RTSTHRESHOLD) == LPUART_RTSTH_FIFOFU))
/**
* @}
*/
/** @addtogroup Hardware_Flow_Control
* @{
*/
#define LPUART_HFCTRL_NONE ((uint16_t)0x0000)
#define LPUART_HFCTRL_CTS ((uint16_t)0x0400)
#define LPUART_HFCTRL_RTS ((uint16_t)0x0800)
#define LPUART_HFCTRL_RTS_CTS ((uint16_t)0x0C00)
#define IS_LPUART_HARDWARE_FLOW_CONTROL(CONTROL) \
(((CONTROL) == LPUART_HFCTRL_NONE) || ((CONTROL) == LPUART_HFCTRL_RTS) || ((CONTROL) == LPUART_HFCTRL_CTS) \
|| ((CONTROL) == LPUART_HFCTRL_RTS_CTS))
/**
* @}
*/
/** @addtogroup LPUART_Interrupt_definition
* @{
*/
#define LPUART_INT_PE ((uint16_t)0x0001)
#define LPUART_INT_TXC ((uint16_t)0x0102)
#define LPUART_INT_FIFO_OV ((uint16_t)0x0204)
#define LPUART_INT_FIFO_FU ((uint16_t)0x0308)
#define LPUART_INT_FIFO_HF ((uint16_t)0x0410)
#define LPUART_INT_FIFO_NE ((uint16_t)0x0520)
#define LPUART_INT_WUF ((uint16_t)0x0640)
#define IS_LPUART_CFG_INT(IT) \
(((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
|| ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
#define IS_LPUART_GET_INT(IT) \
(((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
|| ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
#define IS_LPUART_CLR_INT(IT) \
(((IT) == LPUART_INT_PE) || ((IT) == LPUART_INT_TXC) || ((IT) == LPUART_INT_FIFO_OV) || ((IT) == LPUART_INT_FIFO_FU) \
|| ((IT) == LPUART_INT_FIFO_HF) || ((IT) == LPUART_INT_FIFO_NE) || ((IT) == LPUART_INT_WUF))
/**
* @}
*/
/** @addtogroup LPUART_DMA_Requests
* @{
*/
#define LPUART_DMAREQ_TX ((uint16_t)0x0020)
#define LPUART_DMAREQ_RX ((uint16_t)0x0040)
#define IS_LPUART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF9F) == (uint16_t)0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @addtogroup LPUART_WakeUp_methods
* @{
*/
#define LPUART_WUSTP_STARTBIT ((uint16_t)0x0000)
#define LPUART_WUSTP_RXNE ((uint16_t)0x1000)
#define LPUART_WUSTP_BYTE ((uint16_t)0x2000)
#define LPUART_WUSTP_FRAME ((uint16_t)0x3000)
#define IS_LPUART_WAKEUP(WAKEUP) \
(((WAKEUP) == LPUART_WUSTP_STARTBIT) || ((WAKEUP) == LPUART_WUSTP_RXNE) || ((WAKEUP) == LPUART_WUSTP_BYTE) || ((WAKEUP) == LPUART_WUSTP_FRAME))
/**
* @}
*/
/** @addtogroup LPUART_Sampling_methods
* @{
*/
#define LPUART_SMPCNT_3B ((uint16_t)0x0000)
#define LPUART_SMPCNT_1B ((uint16_t)0x4000)
#define IS_LPUART_SAMPLING(SAMPLING) (((SAMPLING) == LPUART_SMPCNT_1B) || ((SAMPLING) == LPUART_SMPCNT_3B))
/**
* @}
*/
/** @addtogroup LPUART_Flags
* @{
*/
#define LPUART_FLAG_PEF ((uint16_t)0x0001)
#define LPUART_FLAG_TXC ((uint16_t)0x0002)
#define LPUART_FLAG_FIFO_OV ((uint16_t)0x0004)
#define LPUART_FLAG_FIFO_FU ((uint16_t)0x0008)
#define LPUART_FLAG_FIFO_HF ((uint16_t)0x0010)
#define LPUART_FLAG_FIFO_NE ((uint16_t)0x0020)
#define LPUART_FLAG_CTS ((uint16_t)0x0040)
#define LPUART_FLAG_WUF ((uint16_t)0x0080)
#define LPUART_FLAG_NF ((uint16_t)0x0100)
#define IS_LPUART_FLAG(FLAG) \
(((FLAG) == LPUART_FLAG_PEF) || ((FLAG) == LPUART_FLAG_TXC) || ((FLAG) == LPUART_FLAG_FIFO_OV) \
|| ((FLAG) == LPUART_FLAG_FIFO_FU) || ((FLAG) == LPUART_FLAG_FIFO_HF) || ((FLAG) == LPUART_FLAG_FIFO_NE) \
|| ((FLAG) == LPUART_FLAG_CTS) || ((FLAG) == LPUART_FLAG_WUF) || ((FLAG) == LPUART_FLAG_NF))
#define IS_LPUART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFE40) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_LPUART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x010000))
#define IS_LPUART_DATA(DATA) ((DATA) <= 0xFF)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup LPUART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup LPUART_Exported_Functions
* @{
*/
void LPUART_DeInit(void);
void LPUART_Init(LPUART_InitType* LPUART_InitStruct);
void LPUART_StructInit(LPUART_InitType* LPUART_InitStruct);
void LPUART_FlushRxFifo(void);
void LPUART_ConfigInt(uint16_t LPUART_INT, FunctionalState Cmd);
void LPUART_EnableDMA(uint16_t LPUART_DMAReq, FunctionalState Cmd);
void LPUART_ConfigWakeUpMethod(uint16_t LPUART_WakeUpMethod);
void LPUART_EnableWakeUpStop(FunctionalState Cmd);
void LPUART_ConfigSamplingMethod(uint16_t LPUART_SamplingMethod);
void LPUART_EnableLoopBack(FunctionalState Cmd);
void LPUART_SendData(uint8_t Data);
uint8_t LPUART_ReceiveData(void);
void LPUART_ConfigWakeUpData(uint32_t LPUART_WakeUpData);
FlagStatus LPUART_GetFlagStatus(uint16_t LPUART_FLAG);
void LPUART_ClrFlag(uint16_t LPUART_FLAG);
INTStatus LPUART_GetIntStatus(uint16_t LPUART_INT);
void LPUART_ClrIntPendingBit(uint16_t LPART_INT);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43x_LPUART_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_opamp.h
+209
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@@ -0,0 +1,209 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_opamp.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_OPAMPMP_H__
#define __N32G43X_OPAMPMP_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
#include <stdbool.h>
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/** @addtogroup OPAMP_Exported_Constants
* @{
*/
typedef enum
{
OPAMP1 = 0,
OPAMP2 = 4,
} OPAMPX;
// OPAMP_CS
typedef enum
{
OPAMP2_CS_TIMSRCSEL_TIM1CC6 = (0x0L << 24),
OPAMP2_CS_TIMSRCSEL_TIM8CC6 = (0x1L << 24),
}OPAMP2_CS_TIMSRCSEL;
typedef enum
{
OPAMP1_CS_VPSSEL_PA1 = (0x00L << 19),
OPAMP1_CS_VPSSEL_PA5 = (0x01L << 19),
OPAMP1_CS_VPSSEL_PA4 = (0x02L << 19),
OPAMP1_CS_VPSSEL_PA7 = (0x03L << 19),
OPAMP1_CS_VPSSEL_NC = (0x04L << 19),
OPAMP2_CS_VPSSEL_PA7 = (0x00L << 19),
OPAMP2_CS_VPSSEL_PA4 = (0x01L << 19),
OPAMP2_CS_VPSSEL_PB14 = (0x02L << 19),
OPAMP2_CS_VPSSEL_PD13 = (0x03L << 19),
OPAMP2_CS_VPSSEL_NC = (0x04L << 19),
} OPAMP_CS_VPSSEL;
typedef enum
{
OPAMP1_CS_VMSSEL_PA3 = (0x00L << 17),
OPAMP1_CS_VMSSEL_PC5 = (0x01L << 17),
OPAMP1_CS_VMSSEL_NC = (0x02L << 17),
OPAMP1_CS_VMSSEL_FLOAT = (0x03L << 17),
OPAMP2_CS_VMSSEL_PC5 = (0x00L << 17),
OPAMP2_CS_VMSSEL_PB0 = (0x01L << 17),
OPAMP2_CS_VMSSEL_PA5 = (0x02L << 17),
OPAMP2_CS_VMSSEL_FLOAT = (0x03L << 17),
} OPAMP_CS_VMSSEL;
typedef enum
{
OPAMP1_CS_VPSEL_PA1 = (0x00L << 8),
OPAMP1_CS_VPSEL_PA5 = (0x01L << 8),
OPAMP1_CS_VPSEL_PA4 = (0x02L << 8),
OPAMP1_CS_VPSEL_PA7 = (0x03L << 8),
OPAMP1_CS_VPSEL_NC = (0x04L << 8),
OPAMP2_CS_VPSEL_PA7 = (0x00L << 8),
OPAMP2_CS_VPSEL_PA4 = (0x01L << 8),
OPAMP2_CS_VPSEL_PB14 = (0x02L << 8),
OPAMP2_CS_VPSEL_PD13 = (0x03L << 8),
OPAMP2_CS_VPSEL_NC = (0x04L << 8),
} OPAMP_CS_VPSEL;
typedef enum
{
OPAMP1_CS_VMSEL_PA3 = (0x00L << 6),
OPAMP1_CS_VMSEL_PC5 = (0x01L << 6),
OPAMPx_CS_VMSEL_NC = (0x02L << 6),
OPAMPx_CS_VMSEL_FLOAT = (0x03L << 6),
OPAMP2_CS_VMSEL_PC5 = (0x00L << 6),
OPAMP2_CS_VMSEL_PB0 = (0x01L << 6),
OPAMP2_CS_VMSEL_PA5 = (0x02L << 6),
OPAMP2_CS_VMSEL_FLOAT = (0x03L << 6),
} OPAMP_CS_VMSEL;
typedef enum
{
OPAMP_CS_PGA_GAIN_2 = (0x00 << 3),
OPAMP_CS_PGA_GAIN_4 = (0x01 << 3),
OPAMP_CS_PGA_GAIN_8 = (0x02 << 3),
OPAMP_CS_PGA_GAIN_16 = (0x03 << 3),
OPAMP_CS_PGA_GAIN_32 = (0x04 << 3),
} OPAMP_CS_PGA_GAIN;
typedef enum
{
OPAMP_CS_EXT_OPAMP = (0x00 << 1),
OPAMP_CS_PGA_EN = (0x02 << 1),
OPAMP_CS_FOLLOW = (0x03 << 1),
} OPAMP_CS_MOD;
// bit mask
#define OPAMP_CS_EN_MASK (0x01L << 0)
#define OPAMP_CS_MOD_MASK (0x03L << 1)
#define OPAMP_CS_PGA_GAIN_MASK (0x07L << 3)
#define OPAMP_CS_VMSEL_MASK (0x03L << 6)
#define OPAMP_CS_VPSEL_MASK (0x07L << 8)
#define OPAMP_CS_CALON_MASK (0x01L << 11)
#define OPAMP_CS_TSTREF_MASK (0x01L << 13)
#define OPAMP_CS_CALOUT_MASK (0x01L << 14)
#define OPAMP_CS_RANGE_MASK (0x01L << 15)
#define OPAMP_CS_TCMEN_MASK (0x01L << 16)
#define OPAMP_CS_VMSEL_SECOND_MASK (0x03L << 17)
#define OPAMP_CS_VPSEL_SECOND_MASK (0x07L << 19)
#define OPAMP_CS_OPAMP2_TIMSRCSEL (0x01L << 24)
/** @addtogroup OPAMP_LOCK
* @{
*/
#define OPAMP_LOCK_1 0x01L
#define OPAMP_LOCK_2 0x02L
/**
* @}
*/
/**
* @}
*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
OPAMP2_CS_TIMSRCSEL Opa2SrcSel; /*only for opa2 can sel,opa1 always TIM1_CC6*/
FunctionalState TimeAutoMuxEn; /*call ENABLE or DISABLE */
FunctionalState HighVolRangeEn; /*call ENABLE or DISABLE ,low range VDDA < 2.4V,high range VDDA >= 2.4V*/
OPAMP_CS_PGA_GAIN Gain; /*see @EM_PGA_GAIN */
OPAMP_CS_MOD Mod; /*see @EM_OPAMP_MOD*/
} OPAMP_InitType;
/** @addtogroup OPAMP_Exported_Functions
* @{
*/
void OPAMP_DeInit(void);
void OPAMP_StructInit(OPAMP_InitType* OPAMP_InitStruct);
void OPAMP_Init(OPAMPX OPAMPx, OPAMP_InitType* OPAMP_InitStruct);
void OPAMP_Enable(OPAMPX OPAMPx, FunctionalState en);
void OPAMP_SetPgaGain(OPAMPX OPAMPx, OPAMP_CS_PGA_GAIN Gain);
void OPAMP_SetVpSecondSel(OPAMPX OPAMPx, OPAMP_CS_VPSSEL VpSSel);
void OPAMP_SetVmSecondSel(OPAMPX OPAMPx, OPAMP_CS_VMSSEL VmSSel);
void OPAMP_SetVpSel(OPAMPX OPAMPx, OPAMP_CS_VPSEL VpSel);
void OPAMP_SetVmSel(OPAMPX OPAMPx, OPAMP_CS_VMSEL VmSel);
bool OPAMP_IsCalOutHigh(OPAMPX OPAMPx);
void OPAMP_CalibrationEnable(OPAMPX OPAMPx, FunctionalState en);
void OPAMP_SetLock(uint32_t Lock); // see @OPAMP_LOCK
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__N32G43X_ADC_H */
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_pwr.h
+222
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@@ -0,0 +1,222 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_pwr.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43x_PWR_H__
#define __N32G43x_PWR_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/** @addtogroup PWR_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup PWR_Exported_Constants
* @{
*/
/** @addtogroup PVD_detection_level
* @{
*/
#define PWR_PVDLEVEL_2V1 ((uint32_t)0x00000000)
#define PWR_PVDLEVEL_2V25 ((uint32_t)0x0000002)
#define PWR_PVDLEVEL_2V4 ((uint32_t)0x0000004)
#define PWR_PVDLEVEL_2V55 ((uint32_t)0x0000006)
#define PWR_PVDLEVEL_2V7 ((uint32_t)0x0000008)
#define PWR_PVDLEVEL_2V85 ((uint32_t)0x000000A)
#define PWR_PVDLEVEL_2V95 ((uint32_t)0x000000C)
#define PWR_PVDLEVEL_IN ((uint32_t)0x000000E)
#define IS_PWR_PVD_LEVEL(LEVEL) \
(((LEVEL) == PWR_PVDLEVEL_2V1) || ((LEVEL) == PWR_PVDLEVEL_2V25) || ((LEVEL) == PWR_PVDLEVEL_2V4) \
|| ((LEVEL) == PWR_PVDLEVEL_2V55) || ((LEVEL) == PWR_PVDLEVEL_2V7) || ((LEVEL) == PWR_PVDLEVEL_2V85) \
|| ((LEVEL) == PWR_PVDLEVEL_2V95) || ((LEVEL) == PWR_PVDLEVEL_IN) )
/**
* @}
*/
/** @addtogroup Regulator_state_is_STOP_mode
* @{
*/
#define PWR_REGULATOR_ON ((uint32_t)0x00000000)
#define PWR_REGULATOR_LOWPOWER ((uint32_t)0x00000001)
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_REGULATOR_ON) || ((REGULATOR) == PWR_REGULATOR_LOWPOWER))
/**
* @}
*/
/** @defgroup SLEEP_mode_entry
* @{
*/
#define SLEEP_ON_EXIT (1)
#define SLEEP_OFF_EXIT (0)
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/**
* @}
*/
/** @defgroup STOP_mode_entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
/** @addtogroup PWR_Flag
* @{
*/
//STS1
#define PWR_WKUP0_FLAG ((uint32_t)0x00000001)
#define PWR_WKUP1_FLAG ((uint32_t)0x00000002)
#define PWR_WKUP2_FLAG ((uint32_t)0x00000004)
#define PWR_STBY_FLAG ((uint32_t)0x00000100)
//STS2
#define PWR_LPRUN_FLAG ((uint32_t)0x00000001)
#define PWR_MR_FLAG ((uint32_t)0x00000002)
#define PWR_PVDO_FLAG ((uint32_t)0x00000004)
#define IS_PWR_GET_FLAG(FLAG) \
(((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
|| ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
#define IS_PWR_CLEAR_FLAG(FLAG) \
(((FLAG) == PWR_WKUP0_FLAG) || ((FLAG) == PWR_WKUP1_FLAG) || ((FLAG) == PWR_WKUP2_FLAG) || ((FLAG) == PWR_STBY_FLAG)\
|| ((FLAG) == PWR_LPRUN_FLAG) || ((FLAG) == PWR_MR_FLAG) || ((FLAG) == PWR_PVDO_FLAG))
/** @addtogroup SRAM1 SRAM2 retention set
* @{
*/
//#define SRAM1DIS_SRAM2DIS 0
//#define SRAM1EN_SRAM2DIS 1
//#define SRAM1DIS_SRAM2EN 2
//#define SRAM1EN_SRAM2EN 3
/** @addtogroup MR VOLTAGE
* @{
*/
#define MR_1V0 2
#define MR_1V1 3
/**
* @}
*/
typedef enum
{
WAKEUP_PIN0 = 0x0001,
WAKEUP_PIN1 = 0x0002,
WAKEUP_PIN2 = 0x0004,
} WAKEUP_PINX;
/** @addtogroup PWR_Exported_Macros
* @{
*/
/**
* @}
*/
#define LPRUN_SRAM_ADDR (__IO unsigned*)(0x40001800 + 0x20)
#define CLERR_BIT25 0xfdffffff //bit25
#define _SetLprunSramVoltage(vale) do{(*LPRUN_SRAM_ADDR) &= CLERR_BIT25;(*LPRUN_SRAM_ADDR) |= (uint32_t)(vale <<25);}while (0) //0:0.9V 1:1.1V
#define _SetBandGapMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_BGDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<8);}while (0) //0:always on 1:duty on
#define _SetPvdBorMode(vale) do{PWR->CTRL3 &= (~PWR_CTRL3_PBDTLPR);PWR->CTRL3 |= (uint32_t)(vale <<16);}while (0) //0:normal mode 1:standby mode
/** @addtogroup PWR_Exported_Functions
* @{
*/
void PWR_DeInit(void);
void PWR_BackupAccessEnable(FunctionalState Cmd);
void PWR_PvdEnable(FunctionalState Cmd);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinEnable(WAKEUP_PINX WKUP_Pin,FunctionalState Cmd);
void PWR_EnterStopState(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSLEEPMode(uint8_t SLEEPONEXIT, uint8_t PWR_STOPEntry);
void PWR_EnterSTOP2Mode(uint8_t PWR_STOPEntry,uint32_t RetentionMode);
void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry,uint32_t Sam2Ret);
void PWR_EnterLowPowerRunMode(void);
void PWR_ExitLowPowerRunMode(void);
void PWR_EnterLowPowerSleepMode(uint8_t SLEEPONEXIT, uint8_t PWR_SLEEPEntry);
FlagStatus PWR_GetFlagStatus(uint8_t STS, uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
void PWR_WakeUpPinConfig(void);
void SetSysClock_MSI(void);
uint8_t GetMrVoltage(void);
void PWR_MRconfig(uint8_t voltage);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43x_PWR_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_spi.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43x_SPI_H__
#define __N32G43x_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/** @addtogroup SPI_Exported_Types
* @{
*/
/**
* @brief SPI Init structure definition
*/
typedef struct
{
uint16_t DataDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SpiMode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t DataLen; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t CLKPOL; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t CLKPHA; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t BaudRatePres; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. */
} SPI_InitType;
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint16_t I2sMode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2sMode */
uint16_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref Standard */
uint16_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t MCLKEnable; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFrequency; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t CLKPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitType;
/**
* @}
*/
/** @addtogroup SPI_Exported_Constants
* @{
*/
#define IS_SPI_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2))
/** @addtogroup SPI_data_direction
* @{
*/
#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
#define SPI_DIR_DOUBLELINE_RONLY ((uint16_t)0x0400)
#define SPI_DIR_SINGLELINE_RX ((uint16_t)0x8000)
#define SPI_DIR_SINGLELINE_TX ((uint16_t)0xC000)
#define IS_SPI_DIR_MODE(MODE) \
(((MODE) == SPI_DIR_DOUBLELINE_FULLDUPLEX) || ((MODE) == SPI_DIR_DOUBLELINE_RONLY) \
|| ((MODE) == SPI_DIR_SINGLELINE_RX) || ((MODE) == SPI_DIR_SINGLELINE_TX))
/**
* @}
*/
/** @addtogroup SPI_mode
* @{
*/
#define SPI_MODE_MASTER ((uint16_t)0x0104)
#define SPI_MODE_SLAVE ((uint16_t)0x0000)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_MASTER) || ((MODE) == SPI_MODE_SLAVE))
/**
* @}
*/
/** @addtogroup SPI_data_size
* @{
*/
#define SPI_DATA_SIZE_16BITS ((uint16_t)0x0800)
#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATA_SIZE_16BITS) || ((DATASIZE) == SPI_DATA_SIZE_8BITS))
/**
* @}
*/
/** @addtogroup SPI_Clock_Polarity
* @{
*/
#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
#define SPI_CLKPOL_HIGH ((uint16_t)0x0002)
#define IS_SPI_CLKPOL(CPOL) (((CPOL) == SPI_CLKPOL_LOW) || ((CPOL) == SPI_CLKPOL_HIGH))
/**
* @}
*/
/** @addtogroup SPI_Clock_Phase
* @{
*/
#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
#define SPI_CLKPHA_SECOND_EDGE ((uint16_t)0x0001)
#define IS_SPI_CLKPHA(CPHA) (((CPHA) == SPI_CLKPHA_FIRST_EDGE) || ((CPHA) == SPI_CLKPHA_SECOND_EDGE))
/**
* @}
*/
/** @addtogroup SPI_Slave_Select_management
* @{
*/
#define SPI_NSS_SOFT ((uint16_t)0x0200)
#define SPI_NSS_HARD ((uint16_t)0x0000)
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || ((NSS) == SPI_NSS_HARD))
/**
* @}
*/
/** @addtogroup SPI_BaudRate_Prescaler
* @{
*/
#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
#define SPI_BR_PRESCALER_4 ((uint16_t)0x0008)
#define SPI_BR_PRESCALER_8 ((uint16_t)0x0010)
#define SPI_BR_PRESCALER_16 ((uint16_t)0x0018)
#define SPI_BR_PRESCALER_32 ((uint16_t)0x0020)
#define SPI_BR_PRESCALER_64 ((uint16_t)0x0028)
#define SPI_BR_PRESCALER_128 ((uint16_t)0x0030)
#define SPI_BR_PRESCALER_256 ((uint16_t)0x0038)
#define IS_SPI_BR_PRESCALER(PRESCALER) \
(((PRESCALER) == SPI_BR_PRESCALER_2) || ((PRESCALER) == SPI_BR_PRESCALER_4) || ((PRESCALER) == SPI_BR_PRESCALER_8) \
|| ((PRESCALER) == SPI_BR_PRESCALER_16) || ((PRESCALER) == SPI_BR_PRESCALER_32) \
|| ((PRESCALER) == SPI_BR_PRESCALER_64) || ((PRESCALER) == SPI_BR_PRESCALER_128) \
|| ((PRESCALER) == SPI_BR_PRESCALER_256))
/**
* @}
*/
/** @addtogroup SPI_MSB_LSB_transmission
* @{
*/
#define SPI_FB_MSB ((uint16_t)0x0000)
#define SPI_FB_LSB ((uint16_t)0x0080)
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FB_MSB) || ((BIT) == SPI_FB_LSB))
/**
* @}
*/
/** @addtogroup I2sMode
* @{
*/
#define I2S_MODE_SlAVE_TX ((uint16_t)0x0000)
#define I2S_MODE_SlAVE_RX ((uint16_t)0x0100)
#define I2S_MODE_MASTER_TX ((uint16_t)0x0200)
#define I2S_MODE_MASTER_RX ((uint16_t)0x0300)
#define IS_I2S_MODE(MODE) \
(((MODE) == I2S_MODE_SlAVE_TX) || ((MODE) == I2S_MODE_SlAVE_RX) || ((MODE) == I2S_MODE_MASTER_TX) \
|| ((MODE) == I2S_MODE_MASTER_RX))
/**
* @}
*/
/** @addtogroup Standard
* @{
*/
#define I2S_STD_PHILLIPS ((uint16_t)0x0000)
#define I2S_STD_MSB_ALIGN ((uint16_t)0x0010)
#define I2S_STD_LSB_ALIGN ((uint16_t)0x0020)
#define I2S_STD_PCM_SHORTFRAME ((uint16_t)0x0030)
#define I2S_STD_PCM_LONGFRAME ((uint16_t)0x00B0)
#define IS_I2S_STANDARD(STANDARD) \
(((STANDARD) == I2S_STD_PHILLIPS) || ((STANDARD) == I2S_STD_MSB_ALIGN) || ((STANDARD) == I2S_STD_LSB_ALIGN) \
|| ((STANDARD) == I2S_STD_PCM_SHORTFRAME) || ((STANDARD) == I2S_STD_PCM_LONGFRAME))
/**
* @}
*/
/** @addtogroup I2S_Data_Format
* @{
*/
#define I2S_DATA_FMT_16BITS ((uint16_t)0x0000)
#define I2S_DATA_FMT_16BITS_EXTENDED ((uint16_t)0x0001)
#define I2S_DATA_FMT_24BITS ((uint16_t)0x0003)
#define I2S_DATA_FMT_32BITS ((uint16_t)0x0005)
#define IS_I2S_DATA_FMT(FORMAT) \
(((FORMAT) == I2S_DATA_FMT_16BITS) || ((FORMAT) == I2S_DATA_FMT_16BITS_EXTENDED) \
|| ((FORMAT) == I2S_DATA_FMT_24BITS) || ((FORMAT) == I2S_DATA_FMT_32BITS))
/**
* @}
*/
/** @addtogroup I2S_MCLK_Output
* @{
*/
#define I2S_MCLK_ENABLE ((uint16_t)0x0200)
#define I2S_MCLK_DISABLE ((uint16_t)0x0000)
#define IS_I2S_MCLK_ENABLE(OUTPUT) (((OUTPUT) == I2S_MCLK_ENABLE) || ((OUTPUT) == I2S_MCLK_DISABLE))
/**
* @}
*/
/** @addtogroup I2S_Audio_Frequency
* @{
*/
#define I2S_AUDIO_FREQ_192K ((uint32_t)192000)
#define I2S_AUDIO_FREQ_96K ((uint32_t)96000)
#define I2S_AUDIO_FREQ_48K ((uint32_t)48000)
#define I2S_AUDIO_FREQ_44K ((uint32_t)44100)
#define I2S_AUDIO_FREQ_32K ((uint32_t)32000)
#define I2S_AUDIO_FREQ_22K ((uint32_t)22050)
#define I2S_AUDIO_FREQ_16K ((uint32_t)16000)
#define I2S_AUDIO_FREQ_11K ((uint32_t)11025)
#define I2S_AUDIO_FREQ_8K ((uint32_t)8000)
#define I2S_AUDIO_FREQ_DEFAULT ((uint32_t)2)
#define IS_I2S_AUDIO_FREQ(FREQ) \
((((FREQ) >= I2S_AUDIO_FREQ_8K) && ((FREQ) <= I2S_AUDIO_FREQ_192K)) || ((FREQ) == I2S_AUDIO_FREQ_DEFAULT))
/**
* @}
*/
/** @addtogroup I2S_Clock_Polarity
* @{
*/
#define I2S_CLKPOL_LOW ((uint16_t)0x0000)
#define I2S_CLKPOL_HIGH ((uint16_t)0x0008)
#define IS_I2S_CLKPOL(CPOL) (((CPOL) == I2S_CLKPOL_LOW) || ((CPOL) == I2S_CLKPOL_HIGH))
/**
* @}
*/
/** @addtogroup SPI_I2S_DMA_transfer_requests
* @{
*/
#define SPI_I2S_DMA_TX ((uint16_t)0x0002)
#define SPI_I2S_DMA_RX ((uint16_t)0x0001)
#define IS_SPI_I2S_DMA(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
/**
* @}
*/
/** @addtogroup SPI_NSS_internal_software_management
* @{
*/
#define SPI_NSS_HIGH ((uint16_t)0x0100)
#define SPI_NSS_LOW ((uint16_t)0xFEFF)
#define IS_SPI_NSS_LEVEL(INTERNAL) (((INTERNAL) == SPI_NSS_HIGH) || ((INTERNAL) == SPI_NSS_LOW))
/**
* @}
*/
/** @addtogroup SPI_CRC_Transmit_Receive
* @{
*/
#define SPI_CRC_TX ((uint8_t)0x00)
#define SPI_CRC_RX ((uint8_t)0x01)
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_TX) || ((CRC) == SPI_CRC_RX))
/**
* @}
*/
/** @addtogroup SPI_direction_transmit_receive
* @{
*/
#define SPI_BIDIRECTION_RX ((uint16_t)0xBFFF)
#define SPI_BIDIRECTION_TX ((uint16_t)0x4000)
#define IS_SPI_BIDIRECTION(DIRECTION) (((DIRECTION) == SPI_BIDIRECTION_RX) || ((DIRECTION) == SPI_BIDIRECTION_TX))
/**
* @}
*/
/** @addtogroup SPI_I2S_interrupts_definition
* @{
*/
#define SPI_I2S_INT_TE ((uint8_t)0x71)
#define SPI_I2S_INT_RNE ((uint8_t)0x60)
#define SPI_I2S_INT_ERR ((uint8_t)0x50)
#define IS_SPI_I2S_CONFIG_INT(IT) (((IT) == SPI_I2S_INT_TE) || ((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_ERR))
#define SPI_I2S_INT_OVER ((uint8_t)0x56)
#define SPI_INT_MODERR ((uint8_t)0x55)
#define SPI_INT_CRCERR ((uint8_t)0x54)
#define I2S_INT_UNDER ((uint8_t)0x53)
#define IS_SPI_I2S_CLR_INT(IT) (((IT) == SPI_INT_CRCERR))
#define IS_SPI_I2S_GET_INT(IT) \
(((IT) == SPI_I2S_INT_RNE) || ((IT) == SPI_I2S_INT_TE) || ((IT) == I2S_INT_UNDER) || ((IT) == SPI_INT_CRCERR) \
|| ((IT) == SPI_INT_MODERR) || ((IT) == SPI_I2S_INT_OVER))
/**
* @}
*/
/** @addtogroup SPI_I2S_flags_definition
* @{
*/
#define SPI_I2S_RNE_FLAG ((uint16_t)0x0001)
#define SPI_I2S_TE_FLAG ((uint16_t)0x0002)
#define I2S_CHSIDE_FLAG ((uint16_t)0x0004)
#define I2S_UNDER_FLAG ((uint16_t)0x0008)
#define SPI_CRCERR_FLAG ((uint16_t)0x0010)
#define SPI_MODERR_FLAG ((uint16_t)0x0020)
#define SPI_I2S_OVER_FLAG ((uint16_t)0x0040)
#define SPI_I2S_BUSY_FLAG ((uint16_t)0x0080)
#define IS_SPI_I2S_CLR_FLAG(FLAG) (((FLAG) == SPI_CRCERR_FLAG))
#define IS_SPI_I2S_GET_FLAG(FLAG) \
(((FLAG) == SPI_I2S_BUSY_FLAG) || ((FLAG) == SPI_I2S_OVER_FLAG) || ((FLAG) == SPI_MODERR_FLAG) \
|| ((FLAG) == SPI_CRCERR_FLAG) || ((FLAG) == I2S_UNDER_FLAG) || ((FLAG) == I2S_CHSIDE_FLAG) \
|| ((FLAG) == SPI_I2S_TE_FLAG) || ((FLAG) == SPI_I2S_RNE_FLAG))
/**
* @}
*/
/** @addtogroup SPI_CRC_polynomial
* @{
*/
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SPI_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
void SPI_I2S_DeInit(SPI_Module* SPIx);
void SPI_Init(SPI_Module* SPIx, SPI_InitType* SPI_InitStruct);
void I2S_Init(SPI_Module* SPIx, I2S_InitType* I2S_InitStruct);
void SPI_InitStruct(SPI_InitType* SPI_InitStruct);
void I2S_InitStruct(I2S_InitType* I2S_InitStruct);
void SPI_Enable(SPI_Module* SPIx, FunctionalState Cmd);
void I2S_Enable(SPI_Module* SPIx, FunctionalState Cmd);
void SPI_I2S_EnableInt(SPI_Module* SPIx, uint8_t SPI_I2S_IT, FunctionalState Cmd);
void SPI_I2S_EnableDma(SPI_Module* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState Cmd);
void SPI_I2S_TransmitData(SPI_Module* SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_Module* SPIx);
void SPI_SetNssLevel(SPI_Module* SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputEnable(SPI_Module* SPIx, FunctionalState Cmd);
void SPI_ConfigDataLen(SPI_Module* SPIx, uint16_t DataLen);
void SPI_TransmitCrcNext(SPI_Module* SPIx);
void SPI_EnableCalculateCrc(SPI_Module* SPIx, FunctionalState Cmd);
uint16_t SPI_GetCRCDat(SPI_Module* SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPoly(SPI_Module* SPIx);
void SPI_ConfigBidirectionalMode(SPI_Module* SPIx, uint16_t DataDirection);
FlagStatus SPI_I2S_GetStatus(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClrCRCErrFlag(SPI_Module* SPIx, uint16_t SPI_I2S_FLAG);
INTStatus SPI_I2S_GetIntStatus(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClrITPendingBit(SPI_Module* SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif /*__N32G43x_SPI_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
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/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_tsc.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_TSC_H__
#define __N32G43X_TSC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43X_StdPeriph_Driver
* @{
*/
/** @addtogroup TSC
* @{
*/
/**
* @brief TSC error code
*/
typedef enum {
TSC_ERROR_OK = 0x00U, /*!< No error */
TSC_ERROR_CLOCK = 0x01U, /*!< clock config error */
TSC_ERROR_PARAMETER = 0x02U, /*!< parameter error */
TSC_ERROR_HW_MODE = 0x03U, /*!< Exit hw mode timeout */
}TSC_ErrorTypeDef;
/**
* @
*/
/**
* @brief TSC clock source
*/
#define TSC_CLK_SRC_LSI (RCC_LSXCLK_SRC_LSI) /*!< LSI*/
#define TSC_CLK_SRC_LSE (RCC_LSE_ENABLE|RCC_LSXCLK_SRC_LSE) /*!< LSE */
#define TSC_CLK_SRC_LSE_BYPASS (RCC_LSE_BYPASS|RCC_LSXCLK_SRC_LSE) /*!< LSE bypass */
/**
* @
*/
/**
* @defgroup Detect_Period
*/
#define TSC_DET_PERIOD_8 (0x00000000U) /*!< DET_PERIOD[3:0] = 8/TSC_CLOCK */
#define TSC_DET_PERIOD_16 (0x01UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000001U DET_PERIOD[3:0] = 16/TSC_CLOCK */
#define TSC_DET_PERIOD_24 (0x02UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000002U DET_PERIOD[3:0] = 24/TSC_CLOCK */
#define TSC_DET_PERIOD_32 (0x03UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000003U DET_PERIOD[3:0] = 32/TSC_CLOCK(default) */
#define TSC_DET_PERIOD_40 (0x04UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000004U DET_PERIOD[3:0] = 40/TSC_CLOCK */
#define TSC_DET_PERIOD_48 (0x05UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000005U DET_PERIOD[3:0] = 48/TSC_CLOCK */
#define TSC_DET_PERIOD_56 (0x06UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000006U DET_PERIOD[3:0] = 56/TSC_CLOCK */
#define TSC_DET_PERIOD_64 (0x07UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000007U DET_PERIOD[3:0] = 64/TSC_CLOCK */
#define TSC_DET_PERIOD_72 (0x08UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000008U DET_PERIOD[3:0] = 72/TSC_CLOCK */
#define TSC_DET_PERIOD_80 (0x09UL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x00000009U DET_PERIOD[3:0] = 80/TSC_CLOCK */
#define TSC_DET_PERIOD_88 (0x0AUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000AU DET_PERIOD[3:0] = 88/TSC_CLOCK */
#define TSC_DET_PERIOD_96 (0x0BUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000BU DET_PERIOD[3:0] = 96/TSC_CLOCK */
#define TSC_DET_PERIOD_104 (0x0CUL << TSC_CTRL_DET_PERIOD_Pos) /*!< 0x0000000CU DET_PERIOD[3:0] = 104/TSC_CLOCK */
/**
* @
*/
/**
* @defgroup Detect_Filter
*/
#define TSC_DET_FILTER_1 (0x00000000U) /*!< DET_FILTER[3:0] = 1 sample */
#define TSC_DET_FILTER_2 (0x01UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000010U DET_FILTER[3:0] = 2 samples */
#define TSC_DET_FILTER_3 (0x02UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000020U DET_FILTER[3:0] = 3 samples */
#define TSC_DET_FILTER_4 (0x03UL << TSC_CTRL_DET_FILTER_Pos) /*!< 0x00000030U DET_FILTER[3:0] = 4 samples */
/**
* @
*/
/**
* @defgroup HW_Detect_Mode
*/
#define TSC_HW_DET_MODE_DISABLE (0x00000000U) /*!< Hardware detect mode disable */
#define TSC_HW_DET_MODE_ENABLE (0x01UL << TSC_CTRL_HW_DET_MODE_Pos) /*!< 0x00000040U Hardware detect mode enable */
/**
* @
*/
/**
* @defgroup Detect_Type
*/
#define TSC_DET_TYPE_Msk (TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk)
#define TSC_DET_TYPE_Pos (TSC_CTRL_LESS_DET_SEL_Pos)
#define TSC_DET_TYPE_NONE (0UL) /*!< 0x00000000U Disable detect */
#define TSC_DET_TYPE_LESS (0x01UL << TSC_DET_TYPE_Pos) /*!< 0x00000100U Less detect enable */
#define TSC_DET_TYPE_GREAT (0x02UL << TSC_DET_TYPE_Pos) /*!< 0x00000200U Great detect enable */
#define TSC_DET_TYPE_PERIOD (0x03UL << TSC_DET_TYPE_Pos) /*!< 0x00000300U Both great and less detct enable */
/**
* @
*/
/**
* @defgroup TSC_Interrupt
*/
#define TSC_IT_DET_ENABLE (TSC_CTRL_DET_INTEN) /*!< Enable TSC detect interrupt */
#define TSC_IT_DET_DISABLE (0UL) /*!< Disable TSC detect interrupt */
/**
* @
*/
/**
* @defgroup TSC_Out
*/
#define TSC_OUT_PIN (0x00000000U) /*!< TSC output to TSC_OUT pin */
#define TSC_OUT_TIM4_ETR (0x1UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM4 ETR */
#define TSC_OUT_TIM2_ETR (0x2UL << TSC_CTRL_TM4_ETR_Pos) /*!< TSC output to TIM2 ETR and TIM2 CH1*/
/**
* @
*/
/**
* @defgroup TSC_Flag
*/
#define TSC_FLAG_HW (0x1UL << TSC_CTRL_HW_DET_ST_Pos) /*!< Flag of hardware detect mode */
#define TSC_FLAG_GREAT_DET (0x1UL << TSC_STS_GREAT_DET_Pos) /*!< Flag of great detect type */
#define TSC_FLAG_LESS_DET (0x1UL << TSC_STS_LESS_DET_Pos) /*!< Flag of less detect type */
#define TSC_FLAG_PERIOD_DET (TSC_FLAG_GREAT_DET|TSC_FLAG_LESS_DET) /*!< Flag of period detect type */
/**
* @
*/
/**
* @defgroup TSC_SW_Detect
*/
#define TSC_SW_MODE_DISABLE (0x00000000U) /*!< Disable software detect mode */
#define TSC_SW_MODE_ENABLE (0x1UL << TSC_ANA_CTRL_SW_TSC_EN_Pos) /*!< Enable software detect mode */
/**
* @
*/
/**
* @defgroup TSC_PadOption
*/
#define TSC_PAD_INTERNAL_RES (0x00000000U) /*!< Use internal resistor */
#define TSC_PAD_EXTERNAL_RES (0x1UL << TSC_ANA_SEL_PAD_OPT_Pos) /*!< Use external resistor */
/**
* @
*/
/**
* @defgroup TSC_PadSpeed
*/
#define TSC_PAD_SPEED_0 (0x00000000U) /*!< Low speed,about 100K */
#define TSC_PAD_SPEED_1 (0x1UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
#define TSC_PAD_SPEED_2 (0x2UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
#define TSC_PAD_SPEED_3 (0x3UL << TSC_ANA_SEL_SP_OPT_Pos) /*!< Middle spped */
/**
* @
*/
/**
* @defgroup TSC_Constant
*/
#define TSC_CHN_SEL_ALL (TSC_CHNEN_CHN_SELx_Msk)
#define MAX_TSC_HW_CHN (24) /*Maximum number of tsc pin*/
#define MAX_TSC_THRESHOLD_BASE (2047) /*Maximum detect base value of threshold*/
#define MAX_TSC_THRESHOLD_DELTA (255) /*Maximum detect delta value of threshold*/
#define TSC_TIMEOUT (0x01000000) /*TSC normal timeout */
/**
* @
*/
/**
* @defgroup TSC_DetectMode
*/
#define TSC_HW_DETECT_MODE (0x00000001U) /*TSC hardware detect mode*/
#define TSC_SW_DETECT_MODE (0x00000000U) /*TSC software detect mode*/
/**
* @
*/
/* TSC Exported macros -----------------------------------------------------------*/
/** @defgroup TSC_Exported_Macros
* @{
*/
/** @brief Enable the TSC HW detect mode
* @param None
* @retval None
*/
#define __TSC_HW_ENABLE() SET_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
/** @brief Disable the TSC HW detect mode
* @param None
* @retval None
*/
#define __TSC_HW_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_HW_DET_MODE_ENABLE)
/** @brief Config TSC detect period for HW detect mode
* @param __PERIOD__ specifies the TSC detect period during HW detect mode
* @arg TSC_DET_PERIOD_8: Detect period = 8/TSC_CLK
* @arg TSC_DET_PERIOD_16: Detect Period = 1/TSC_CLK
* @arg TSC_DET_PERIOD_24: Detect Period = 2/TSC_CLK
* @arg TSC_DET_PERIOD_32: Detect Period = 3/TSC_CLK
* @arg TSC_DET_PERIOD_40: Detect Period = 4/TSC_CLK
* @arg TSC_DET_PERIOD_48: Detect Period = 5/TSC_CLK
* @arg TSC_DET_PERIOD_56: Detect Period = 6/TSC_CLK
* @arg TSC_DET_PERIOD_64: Detect Period = 7/TSC_CLK
* @arg TSC_DET_PERIOD_72: Detect Period = 7/TSC_CLK
* @arg TSC_DET_PERIOD_80: Detect Period = 7/TSC_CLK
* @arg TSC_DET_PERIOD_88: Detect Period = 7/TSC_CLK
* @arg TSC_DET_PERIOD_96: Detect Period = 7/TSC_CLK
* @arg TSC_DET_PERIOD_104:Detect Period = 7/TSC_CLK
* @retval None
*/
#define __TSC_PERIOD_CONFIG(__PERIOD__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_PERIOD_Msk,__PERIOD__)
/** @brief Config TSC detect filter for HW detect mode
* @param __FILTER__ specifies the least usefull continuous samples during HW detect mode
* @arg TSC_DET_FILTER_1: Detect filter = 1 pulse
* @arg TSC_DET_FILTER_2: Detect filter = 2 pulse
* @arg TSC_DET_FILTER_3: Detect filter = 3 pulse
* @arg TSC_DET_FILTER_4: Detect filter = 4 pulse
* @retval None
*/
#define __TSC_FILTER_CONFIG(__FILTER__) MODIFY_REG(TSC->CTRL, TSC_CTRL_DET_FILTER_Msk,__FILTER__)
/** @brief Config TSC detect type for HW detect mode,less great or both
* @param __TYPE__ specifies the detect type of a sample during HW detect mode
* @arg TSC_DET_TYPE_NONE: Detect disable
* @arg TSC_DET_TYPE_LESS: Pulse number must be greater than the threshold(basee-delta) during a sample time
* @arg TSC_DET_TYPE_GREAT: Pulse number must be less than the threshold(basee+delta) during a sample time
* @arg TSC_DET_TYPE_PERIOD:Pulse number must be greater than (basee-delta)
and also be less than (basee+delta) during a sample time
* @retval None
*/
#define __TSC_LESS_GREAT_CONFIG(__TYPE__) MODIFY_REG(TSC->CTRL, \
(TSC_CTRL_LESS_DET_SEL_Msk|TSC_CTRL_GREAT_DET_SEL_Msk), \
__TYPE__)
/** @brief Enable TSC interrupt
* @param None
* @retval None
*/
#define __TSC_INT_ENABLE() SET_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
/** @brief Disable TSC interrupt
* @param None
* @retval None
*/
#define __TSC_INT_DISABLE() CLEAR_BIT(TSC->CTRL, TSC_IT_DET_ENABLE)
/** @brief Config the TSC output
* @param __OUT__ specifies where the TSC output should go
* @arg TSC_OUT_PIN: TSC output to the TSC_OUT pin
* @arg TSC_OUT_TIM4_ETR: TSC output to TIM4 as ETR
* @arg TSC_OUT_TIM2_ETR: TSC output to TIM2 as ETR
* @retval None
*/
#define __TSC_OUT_CONFIG(__OUT__) MODIFY_REG( TSC->CTRL, \
(TSC_CTRL_TM4_ETR_Msk|TSC_CTRL_TM2_ETR_CH1_Msk),\
__OUT__)
/** @brief Config the TSC channel
* @param __CHN__ specifies the pin of channels used for detect
* This parameter:bit[0:23] used,bit[24:31] must be 0
* bitx: TSC channel x
* @retval None
*/
#define __TSC_CHN_CONFIG(__CHN__) WRITE_REG(TSC->CHNEN, __CHN__)
/** @brief Enable the TSC SW detect mode
* @param None
* @retval None
*/
#define __TSC_SW_ENABLE() SET_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
/** @brief Disable the TSC SW detect mode
* @param None
* @retval None
*/
#define __TSC_SW_DISABLE() CLEAR_BIT(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_TSC_EN)
/** @brief Config the detect channel number during SW detect mode
* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
* @retval None
*/
#define __TSC_SW_CHN_NUM_CONFIG(__NUM__) MODIFY_REG(TSC->ANA_CTRL, TSC_ANA_CTRL_SW_PAD_MUX_Msk,__NUM__)
/** @brief Config the pad charge type
* @param __OPT__ specifies which resistor is used for charge
* @arg TSC_PAD_INTERNAL_RES: Internal resistor is used
* @arg TSC_PAD_EXTERNAL_RES: External resistor is used
* @retval None
*/
#define __TSC_PAD_OPT_CONFIG(__OPT__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_PAD_OPT_Msk,__OPT__)
/** @brief Config TSC speed
* @param __SPEED__ specifies the TSC speed range
* @arg TSC_PAD_SPEED_0: Low speed
* @arg TSC_PAD_SPEED_1: Middle speed
* @arg TSC_PAD_SPEED_2: Middle speed
* @arg TSC_PAD_SPEED_3: High speed
* @retval None
*/
#define __TSC_PAD_SPEED_CONFIG(__SPEED__) MODIFY_REG(TSC->ANA_SEL, TSC_ANA_SEL_SP_OPT_Msk,__SPEED__)
/** @brief Check if the HW detect mode is enable
* @param None
* @retval Current state of HW detect mode
*/
#define __TSC_GET_HW_MODE() (((TSC->CTRL) & TSC_FLAG_HW) == (TSC_FLAG_HW))
/** @brief Check the detect type during HW detect mode
* @param __FLAG__ specifies the flag of detect type
* @arg TSC_FLAG_LESS_DET: Flag of less detect type
* @arg TSC_FLAG_GREAT_DET: Flag of great detect type
* @arg TSC_FLAG_PERIOD_DET: Flag of priod detect type
* @retval Current state of flag
*/
#define __TSC_GET_HW_DET_TYPE(__FLAG__) (((TSC->STS) & (__FLAG__))==(__FLAG__))
/** @brief Get the number of channel which is detected now
* @param None
* @retval Current channel number
*/
#define __TSC_GET_CHN_NUMBER() (((TSC->STS) & TSC_STS_CHN_NUM_Msk) >> TSC_STS_CHN_NUM_Pos )
/** @brief Get the count value of pulse
* @param None
* @retval Pulse count of current channel
*/
#define __TSC_GET_CHN_CNT() (((TSC->STS) & TSC_STS_CNT_VAL_Msk ) >> TSC_STS_CNT_VAL_Pos )
/** @brief Get the base value of one channel
* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
* @retval base value of the channel
*/
#define __TSC_GET_CHN_BASE(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_BASE_Msk ) >> TSC_THRHDx_BASE_Pos)
/** @brief Get the delta value of one channel
* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
* @retval delta value of the channel
*/
#define __TSC_GET_CHN_DELTA(__NUM__) ((TSC->THRHD[(__NUM__)] & TSC_THRHDx_DELTA_Msk ) >> TSC_THRHDx_DELTA_Pos )
/** @brief Get the internal resist value of one channel
* @param __NUM__ specifies channel number,must be less than MAX_TSC_HW_CHN
* @retval resist value of the channel
*/
#define __TSC_GET_CHN_RESIST(__NUM__) ((TSC->RESR[(__NUM__)>>3] >>(((__NUM__) & 0x7UL)*4)) & TSC_RESRx_CHN_RESIST_Msk)
/* Private macros ------------------------------------------------------------*/
/** @defgroup TSC_Private_Macros
* @{
*/
#define IS_TSC_DET_PERIOD(_PERIOD_) \
(((_PERIOD_)==TSC_DET_PERIOD_8) ||((_PERIOD_)==TSC_DET_PERIOD_16)||((_PERIOD_)==TSC_DET_PERIOD_24) \
||((_PERIOD_)==TSC_DET_PERIOD_32)||((_PERIOD_)==TSC_DET_PERIOD_40)||((_PERIOD_)==TSC_DET_PERIOD_48) \
||((_PERIOD_)==TSC_DET_PERIOD_56)||((_PERIOD_)==TSC_DET_PERIOD_64)||((_PERIOD_)==TSC_DET_PERIOD_72) \
||((_PERIOD_)==TSC_DET_PERIOD_80)||((_PERIOD_)==TSC_DET_PERIOD_88)||((_PERIOD_)==TSC_DET_PERIOD_96) \
||((_PERIOD_)==TSC_DET_PERIOD_104) )
#define IS_TSC_FILTER(_FILTER_) \
( ((_FILTER_)==TSC_DET_FILTER_1) ||((_FILTER_)==TSC_DET_FILTER_2)\
||((_FILTER_)==TSC_DET_FILTER_3) ||((_FILTER_)==TSC_DET_FILTER_4) )
#define IS_TSC_DET_MODE(_MODE_) \
( ((_MODE_)==TSC_HW_DETECT_MODE) ||((_MODE_)==TSC_SW_DETECT_MODE) )
#define IS_TSC_DET_TYPE(_TYPE_) \
( ((_TYPE_)==TSC_DET_TYPE_GREAT) ||((_TYPE_)==TSC_DET_TYPE_LESS) \
||((_TYPE_)==TSC_DET_TYPE_PERIOD)|| ((_TYPE_)==TSC_DET_TYPE_NONE) )
#define IS_TSC_INT(_INT_) (((_INT_)==TSC_IT_DET_ENABLE)||((_INT_)==TSC_IT_DET_DISABLE))
#define IS_TSC_OUT(_ETR_) (((_ETR_)==TSC_OUT_PIN)||((_ETR_)==TSC_OUT_TIM2_ETR)||((_ETR_)==TSC_OUT_TIM4_ETR))
#define IS_TSC_CHN(_CHN_) (0==((_CHN_)&(~TSC_CHNEN_CHN_SELx_Msk)))
#define IS_TSC_CHN_NUMBER(_NUM_) ( ((_NUM_)==1) \
||(((_NUM_)>=4) && ((_NUM_)<=17)) \
||(((_NUM_)>=19) && ((_NUM_)<=23)) )
#define IS_TSC_PAD_OPTION(_OPT_) (((_OPT_)==TSC_PAD_INTERNAL_RES)||((_OPT_)==TSC_PAD_EXTERNAL_RES))
#define IS_TSC_PAD_SPEED(_SPEED_) \
( ((_SPEED_)==TSC_PAD_SPEED_0)||((_SPEED_)==TSC_PAD_SPEED_1) \
||((_SPEED_)==TSC_PAD_SPEED_2)||((_SPEED_)==TSC_PAD_SPEED_3) )
#define IS_TSC_RESISTOR_VALUE(_RES_) \
( ((_RES_)==TSC_RESRx_CHN_RESIST_0)||((_RES_)==TSC_RESRx_CHN_RESIST_1) \
||((_RES_)==TSC_RESRx_CHN_RESIST_2)||((_RES_)==TSC_RESRx_CHN_RESIST_3) \
||((_RES_)==TSC_RESRx_CHN_RESIST_4)||((_RES_)==TSC_RESRx_CHN_RESIST_5) \
||((_RES_)==TSC_RESRx_CHN_RESIST_6)||((_RES_)==TSC_RESRx_CHN_RESIST_7) )
#define IS_TSC_THRESHOLD_BASE(_BASE_) ( (_BASE_)<=MAX_TSC_THRESHOLD_BASE)
#define IS_TSC_THRESHOLD_DELTA(_DELTA_) ( (_DELTA_)<=MAX_TSC_THRESHOLD_DELTA)
/**
* @brief TSC Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the TSC work mode.
This parameter can be one value of @ref TSC_DetectMode */
uint32_t Period; /*!< Configures the TSC check period for a sample.
This parameter can be one value of @ref Detect_Period */
uint32_t Filter; /*!< Configures the TSC filter.
This parameter can be one value of @ref Detect_Filter */
uint32_t Type; /*!< Configures the TSC check type
This parameter can be one value of @ref Detect_Type */
uint32_t Chn; /*!< Selects the TSC chnnel used
This parameter can be one value of @ref TSC_CHNEN_CHN_SELx_Msk */
uint32_t Out; /*!< Configures the TSC_OUT etr
This parameter can be one value of @ref TSC_Out */
uint32_t Int; /*!< Configures the TSC interrupt
This parameter can be one value of @ref TSC_Interrupt */
uint32_t PadOpt; /*!< Configures the TSC charge resistor
This parameter can be one value of @ref TSC_PadOption */
uint32_t Speed; /*!< Configures the TSC detect speed
This parameter can be one value of @ref TSC_PadSpeed */
}TSC_InitType;
typedef struct
{
uint16_t TSC_Base; /*!< base value */
uint8_t TSC_Delta; /*!< offset value */
uint8_t TSC_Resistor; /*!< resistance value configuration*/
} TSC_ChnCfg;
TSC_ErrorTypeDef TSC_Init(TSC_InitType* InitParam);
TSC_ErrorTypeDef TSC_ClockConfig(uint32_t TSC_ClkSource);
TSC_ErrorTypeDef TSC_ConfigInternalResistor(uint32_t Channels, uint32_t res );
TSC_ErrorTypeDef TSC_ConfigThreshold( uint32_t Channels, uint32_t base, uint32_t delta);
TSC_ErrorTypeDef TSC_GetChannelCfg( TSC_ChnCfg* ChnCfg, uint32_t ChannelNum);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43X_TSC_H__ */
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_usart.h
+397
View File
@@ -0,0 +1,397 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_usart.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43x_USART_H__
#define __N32G43x_USART_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/** @addtogroup USART_Exported_Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref Mode */
uint16_t HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitType;
/**
* @brief USART Clock Init Structure definition
*/
typedef struct
{
uint16_t Clock; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref Clock */
uint16_t Polarity; /*!< Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t Phase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitType;
/**
* @}
*/
/** @addtogroup USART_Exported_Constants
* @{
*/
#define IS_USART_ALL_PERIPH(PERIPH) \
(((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5))
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3))
#define IS_USART_1234_PERIPH(PERIPH) \
(((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4))
/** @addtogroup USART_Word_Length
* @{
*/
#define USART_WL_8B ((uint16_t)0x0000)
#define USART_WL_9B ((uint16_t)0x1000)
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WL_8B) || ((LENGTH) == USART_WL_9B))
/**
* @}
*/
/** @addtogroup USART_Stop_Bits
* @{
*/
#define USART_STPB_1 ((uint16_t)0x0000)
#define USART_STPB_0_5 ((uint16_t)0x1000)
#define USART_STPB_2 ((uint16_t)0x2000)
#define USART_STPB_1_5 ((uint16_t)0x3000)
#define IS_USART_STOPBITS(STOPBITS) \
(((STOPBITS) == USART_STPB_1) || ((STOPBITS) == USART_STPB_0_5) || ((STOPBITS) == USART_STPB_2) \
|| ((STOPBITS) == USART_STPB_1_5))
/**
* @}
*/
/** @addtogroup Parity
* @{
*/
#define USART_PE_NO ((uint16_t)0x0000)
#define USART_PE_EVEN ((uint16_t)0x0400)
#define USART_PE_ODD ((uint16_t)0x0600)
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_PE_NO) || ((PARITY) == USART_PE_EVEN) || ((PARITY) == USART_PE_ODD))
/**
* @}
*/
/** @addtogroup Mode
* @{
*/
#define USART_MODE_RX ((uint16_t)0x0004)
#define USART_MODE_TX ((uint16_t)0x0008)
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
/**
* @}
*/
/** @addtogroup USART_Hardware_Flow_Control
* @{
*/
#define USART_HFCTRL_NONE ((uint16_t)0x0000)
#define USART_HFCTRL_RTS ((uint16_t)0x0100)
#define USART_HFCTRL_CTS ((uint16_t)0x0200)
#define USART_HFCTRL_RTS_CTS ((uint16_t)0x0300)
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \
(((CONTROL) == USART_HFCTRL_NONE) || ((CONTROL) == USART_HFCTRL_RTS) || ((CONTROL) == USART_HFCTRL_CTS) \
|| ((CONTROL) == USART_HFCTRL_RTS_CTS))
/**
* @}
*/
/** @addtogroup Clock
* @{
*/
#define USART_CLK_DISABLE ((uint16_t)0x0000)
#define USART_CLK_ENABLE ((uint16_t)0x0800)
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLK_DISABLE) || ((CLOCK) == USART_CLK_ENABLE))
/**
* @}
*/
/** @addtogroup USART_Clock_Polarity
* @{
*/
#define USART_CLKPOL_LOW ((uint16_t)0x0000)
#define USART_CLKPOL_HIGH ((uint16_t)0x0400)
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CLKPOL_LOW) || ((CPOL) == USART_CLKPOL_HIGH))
/**
* @}
*/
/** @addtogroup USART_Clock_Phase
* @{
*/
#define USART_CLKPHA_1EDGE ((uint16_t)0x0000)
#define USART_CLKPHA_2EDGE ((uint16_t)0x0200)
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CLKPHA_1EDGE) || ((CPHA) == USART_CLKPHA_2EDGE))
/**
* @}
*/
/** @addtogroup USART_Last_Bit
* @{
*/
#define USART_CLKLB_DISABLE ((uint16_t)0x0000)
#define USART_CLKLB_ENABLE ((uint16_t)0x0100)
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_CLKLB_DISABLE) || ((LASTBIT) == USART_CLKLB_ENABLE))
/**
* @}
*/
/** @addtogroup USART_Interrupt_definition
* @{
*/
#define USART_INT_PEF ((uint16_t)0x0028)
#define USART_INT_TXDE ((uint16_t)0x0727)
#define USART_INT_TXC ((uint16_t)0x0626)
#define USART_INT_RXDNE ((uint16_t)0x0525)
#define USART_INT_IDLEF ((uint16_t)0x0424)
#define USART_INT_LINBD ((uint16_t)0x0846)
#define USART_INT_CTSF ((uint16_t)0x096A)
#define USART_INT_ERRF ((uint16_t)0x0060)
#define USART_INT_OREF ((uint16_t)0x0360)
#define USART_INT_NEF ((uint16_t)0x0260)
#define USART_INT_FEF ((uint16_t)0x0160)
#define IS_USART_CFG_INT(IT) \
(((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
|| ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) \
|| ((IT) == USART_INT_ERRF))
#define IS_USART_GET_INT(IT) \
(((IT) == USART_INT_PEF) || ((IT) == USART_INT_TXDE) || ((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) \
|| ((IT) == USART_INT_IDLEF) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF) || ((IT) == USART_INT_OREF) \
|| ((IT) == USART_INT_NEF) || ((IT) == USART_INT_FEF))
#define IS_USART_CLR_INT(IT) \
(((IT) == USART_INT_TXC) || ((IT) == USART_INT_RXDNE) || ((IT) == USART_INT_LINBD) || ((IT) == USART_INT_CTSF))
/**
* @}
*/
/** @addtogroup USART_DMA_Requests
* @{
*/
#define USART_DMAREQ_TX ((uint16_t)0x0080)
#define USART_DMAREQ_RX ((uint16_t)0x0040)
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
/**
* @}
*/
/** @addtogroup USART_WakeUp_methods
* @{
*/
#define USART_WUM_IDLELINE ((uint16_t)0x0000)
#define USART_WUM_ADDRMASK ((uint16_t)0x0800)
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WUM_IDLELINE) || ((WAKEUP) == USART_WUM_ADDRMASK))
/**
* @}
*/
/** @addtogroup USART_LIN_Break_Detection_Length
* @{
*/
#define USART_LINBDL_10B ((uint16_t)0x0000)
#define USART_LINBDL_11B ((uint16_t)0x0020)
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == USART_LINBDL_10B) || ((LENGTH) == USART_LINBDL_11B))
/**
* @}
*/
/** @addtogroup USART_IrDA_Low_Power
* @{
*/
#define USART_IRDAMODE_LOWPPWER ((uint16_t)0x0004)
#define USART_IRDAMODE_NORMAL ((uint16_t)0x0000)
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IRDAMODE_LOWPPWER) || ((MODE) == USART_IRDAMODE_NORMAL))
/**
* @}
*/
/** @addtogroup USART_Flags
* @{
*/
#define USART_FLAG_CTSF ((uint16_t)0x0200)
#define USART_FLAG_LINBD ((uint16_t)0x0100)
#define USART_FLAG_TXDE ((uint16_t)0x0080)
#define USART_FLAG_TXC ((uint16_t)0x0040)
#define USART_FLAG_RXDNE ((uint16_t)0x0020)
#define USART_FLAG_IDLEF ((uint16_t)0x0010)
#define USART_FLAG_OREF ((uint16_t)0x0008)
#define USART_FLAG_NEF ((uint16_t)0x0004)
#define USART_FLAG_FEF ((uint16_t)0x0002)
#define USART_FLAG_PEF ((uint16_t)0x0001)
#define IS_USART_FLAG(FLAG) \
(((FLAG) == USART_FLAG_PEF) || ((FLAG) == USART_FLAG_TXDE) || ((FLAG) == USART_FLAG_TXC) \
|| ((FLAG) == USART_FLAG_RXDNE) || ((FLAG) == USART_FLAG_IDLEF) || ((FLAG) == USART_FLAG_LINBD) \
|| ((FLAG) == USART_FLAG_CTSF) || ((FLAG) == USART_FLAG_OREF) || ((FLAG) == USART_FLAG_NEF) \
|| ((FLAG) == USART_FLAG_FEF))
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) \
((((*(uint32_t*)&(PERIPH)) != UART4_BASE) && ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \
|| ((USART_FLAG) != USART_FLAG_CTSF))
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x00337F99))
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
/**
* @}
*/
/**
* @}
*/
/** @addtogroup USART_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup USART_Exported_Functions
* @{
*/
void USART_DeInit(USART_Module* USARTx);
void USART_Init(USART_Module* USARTx, USART_InitType* USART_InitStruct);
void USART_StructInit(USART_InitType* USART_InitStruct);
void USART_ClockInit(USART_Module* USARTx, USART_ClockInitType* USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitType* USART_ClockInitStruct);
void USART_Enable(USART_Module* USARTx, FunctionalState Cmd);
void USART_ConfigInt(USART_Module* USARTx, uint16_t USART_INT, FunctionalState Cmd);
void USART_EnableDMA(USART_Module* USARTx, uint16_t USART_DMAReq, FunctionalState Cmd);
void USART_SetAddr(USART_Module* USARTx, uint8_t USART_Addr);
void USART_ConfigWakeUpMode(USART_Module* USARTx, uint16_t USART_WakeUpMode);
void USART_EnableRcvWakeUp(USART_Module* USARTx, FunctionalState Cmd);
void USART_ConfigLINBreakDetectLength(USART_Module* USARTx, uint16_t USART_LINBreakDetectLength);
void USART_EnableLIN(USART_Module* USARTx, FunctionalState Cmd);
void USART_SendData(USART_Module* USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_Module* USARTx);
void USART_SendBreak(USART_Module* USARTx);
void USART_SetGuardTime(USART_Module* USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_Module* USARTx, uint8_t USART_Prescaler);
void USART_EnableSmartCard(USART_Module* USARTx, FunctionalState Cmd);
void USART_SetSmartCardNACK(USART_Module* USARTx, FunctionalState Cmd);
void USART_EnableHalfDuplex(USART_Module* USARTx, FunctionalState Cmd);
void USART_ConfigIrDAMode(USART_Module* USARTx, uint16_t USART_IrDAMode);
void USART_EnableIrDA(USART_Module* USARTx, FunctionalState Cmd);
FlagStatus USART_GetFlagStatus(USART_Module* USARTx, uint16_t USART_FLAG);
void USART_ClrFlag(USART_Module* USARTx, uint16_t USART_FLAG);
INTStatus USART_GetIntStatus(USART_Module* USARTx, uint16_t USART_INT);
void USART_ClrIntPendingBit(USART_Module* USARTx, uint16_t USART_INT);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43x_USART_H__ */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/inc/n32g43x_wwdg.h
+122
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@@ -0,0 +1,122 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file n32g43x_wwdg.h
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G43X_WWDG_H__
#define __N32G43X_WWDG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g43x.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/** @addtogroup WWDG_Exported_Types
* @{
*/
/**
* @}
*/
/** @addtogroup WWDG_Exported_Constants
* @{
*/
/** @addtogroup WWDG_Prescaler
* @{
*/
#define WWDG_PRESCALER_DIV1 ((uint32_t)0x00000000)
#define WWDG_PRESCALER_DIV2 ((uint32_t)0x00000080)
#define WWDG_PRESCALER_DIV4 ((uint32_t)0x00000100)
#define WWDG_PRESCALER_DIV8 ((uint32_t)0x00000180)
#define IS_WWDG_PRESCALER_DIV(PRESCALER) \
(((PRESCALER) == WWDG_PRESCALER_DIV1) || ((PRESCALER) == WWDG_PRESCALER_DIV2) \
|| ((PRESCALER) == WWDG_PRESCALER_DIV4) || ((PRESCALER) == WWDG_PRESCALER_DIV8))
#define IS_WWDG_WVALUE(VALUE) ((VALUE) <= 0x7F)
#define IS_WWDG_CNT(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
/**
* @}
*/
/**
* @}
*/
/** @addtogroup WWDG_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
void WWDG_DeInit(void);
void WWDG_SetPrescalerDiv(uint32_t WWDG_Prescaler);
void WWDG_SetWValue(uint8_t WindowValue);
void WWDG_EnableInt(void);
void WWDG_SetCnt(uint8_t Counter);
void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetEWINTF(void);
void WWDG_ClrEWINTF(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G43X__WWDG_H */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
bsp/n32/libraries/N32G43x_Firmware_Library/n32g43x_std_periph_driver/src/misc.c
+229
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@@ -0,0 +1,229 @@
/*****************************************************************************
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
* ****************************************************************************
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Nations' name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY NATIONS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL NATIONS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ****************************************************************************/
/**
* @file misc.c
* @author Nations
* @version v1.2.0
*
* @copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#include "misc.h"
/** @addtogroup N32G43x_StdPeriph_Driver
* @{
*/
/** @addtogroup MISC
* @brief MISC driver modules
* @{
*/
/** @addtogroup MISC_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Private_Defines
* @{
*/
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
/**
* @}
*/
/** @addtogroup MISC_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Private_Variables
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup MISC_Private_Functions
* @{
*/
/**
* @brief Configures the priority grouping: pre-emption priority and subpriority.
* @param NVIC_PriorityGroup specifies the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PriorityGroup_0 0 bits for pre-emption priority
* 4 bits for subpriority
* @arg NVIC_PriorityGroup_1 1 bits for pre-emption priority
* 3 bits for subpriority
* @arg NVIC_PriorityGroup_2 2 bits for pre-emption priority
* 2 bits for subpriority
* @arg NVIC_PriorityGroup_3 3 bits for pre-emption priority
* 1 bits for subpriority
* @arg NVIC_PriorityGroup_4 4 bits for pre-emption priority
* 0 bits for subpriority
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
}
/**
* @brief Initializes the NVIC peripheral according to the specified
* parameters in the NVIC_InitStruct.
* @param NVIC_InitStruct pointer to a NVIC_InitType structure that contains
* the configuration information for the specified NVIC peripheral.
*/
void NVIC_Init(NVIC_InitType* NVIC_InitStruct)
{
uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority --------------------------------*/
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08;
tmppre = (0x4 - tmppriority);
tmpsub = tmpsub >> tmppriority;
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
tmppriority = tmppriority << 0x04;
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
/* Enable the Selected IRQ Channels --------------------------------------*/
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
<< (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels -------------------------------------*/
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = (uint32_t)0x01
<< (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
}
}
/**
* @brief Sets the vector table location and Offset.
* @param NVIC_VectTab specifies if the vector table is in RAM or FLASH memory.
* This parameter can be one of the following values:
* @arg NVIC_VectTab_RAM
* @arg NVIC_VectTab_FLASH
* @param Offset Vector Table base offset field. This value must be a multiple
* of 0x200.
*/
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
{
/* Check the parameters */
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
assert_param(IS_NVIC_OFFSET(Offset));
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
}
/**
* @brief Selects the condition for the system to enter low power mode.
* @param LowPowerMode Specifies the new mode for the system to enter low power mode.
* This parameter can be one of the following values:
* @arg NVIC_LP_SEVONPEND
* @arg NVIC_LP_SLEEPDEEP
* @arg NVIC_LP_SLEEPONEXIT
* @param Cmd new state of LP condition. This parameter can be: ENABLE or DISABLE.
*/
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState Cmd)
{
/* Check the parameters */
assert_param(IS_NVIC_LP(LowPowerMode));
assert_param(IS_FUNCTIONAL_STATE(Cmd));
if (Cmd != DISABLE)
{
SCB->SCR |= LowPowerMode;
}
else
{
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
}
/**
* @brief Configures the SysTick clock source.
* @param SysTick_CLKSource specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SysTick_CLKSource_HCLK_Div8 AHB clock divided by 8 selected as SysTick clock source.
* @arg SysTick_CLKSource_HCLK AHB clock selected as SysTick clock source.
*/
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
{
SysTick->CTRL |= SysTick_CLKSource_HCLK;
}
else
{
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
}
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/

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