[bsp][hpmicro] Update libraries, add new BSPs

- Updated hpm_sdk in libraries - Updated rt-thread driver adapter - Updated bsp for hpm6750evkmini - Updated bsp for hpm6750evk - Added bsp for hpm6750evk2 - Added bsp for hpm6300evk - Added bsp for hpm6200evk Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
2026-10-02 14:23:19 +08:00 · 2023-08-16 13:46:43 +08:00
parent 83a2863ab6
commit 0bd93292b3
685 changed files with 135406 additions and 258066 deletions
@@ -0,0 +1,11 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+  - hpm6200evk/startup
+  - hpm6300evk/startup
+  - hpm6750evk/startup
+  - hpm6750evk2/startup
+  - hpm6750evkmini/startup
+  - libraries/hpm_sdk
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
@@ -0,0 +1,114 @@
+# HPMicro HPM6200EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides brief introduction of the BSP (board support package) for the HPM6200EVK development board.
+
+The document consists of the following parts:
+
+- HPM6200EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6200EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6200EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6200evk)
@@ -0,0 +1,115 @@
+# 先楫 HPM6200EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6200EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6200EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+ HPM6200EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 由RT-Thread Industry IO扩展板提供支持    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6280-single-core.cfg -f boards\debug_scripts\boards\hpm6200evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6200EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6200evk)
@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -9,6 +9,6 @@ src = Glob('*.c')
 CPPDEFINES=[]
 CPPPATH = [cwd]

-group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)

 Return('group')
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include <drv_gpio.h>
+
+void thread_entry(void *arg);
+
+
+int main(void)
+{
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1){
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
+        rt_thread_mdelay(500);
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}
@@ -0,0 +1,18 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    fal_flash_port.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6280']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
@@ -0,0 +1,33 @@
+# Copyright 2023 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x1
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4002000
+    $::_TARGET0 riscv dmi_write 0x3C 0x2
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000800
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000810
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000820
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+
+    $::_TARGET0 riscv dmi_write 0x39 0xF4000830
+    $::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
+    echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+    init_clock
+}
+
+$_TARGET0 configure -event gdb-attach {
+    reset halt
+}
@@ -0,0 +1,11 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 8000
+adapter srst delay 500
+
+source [find interface/cmsis-dap.cfg]
+
+transport select jtag
+reset_config srst_only
@@ -0,0 +1,15 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
+
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+reset_config trst_and_srst
+adapter srst delay 50
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6014
+
+ftdi_layout_init 0x0018 0x001b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
@@ -0,0 +1,11 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+
+source [find interface/jlink.cfg]
+
+transport select jtag
+reset_config srst_only
@@ -0,0 +1,14 @@
+# Copyright (c) 2021 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+bindto 0.0.0.0
+adapter speed 10000
+adapter srst delay 500
+reset_config srst_only
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x010b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
@@ -0,0 +1,61 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+set _CHIP hpm6280
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0
+
+proc dmi_write {reg value} {
+    $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+    set v [$::_TARGET0 riscv dmi_read ${reg}]
+    return ${v}
+}
+proc dmi_write_memory {addr value} {
+    dmi_write 0x39 ${addr}
+    dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+    set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
+    dmi_write 0x38 ${sbcs}
+    dmi_write 0x39 ${addr}
+    set value [dmi_read 0x3C]
+    return ${value}
+}
+
+proc release_core1 {} {
+    # set start point for core1
+    dmi_write_memory 0xF4002C08 0x20012588
+
+    # set boot flag for core1
+    dmi_write_memory 0xF4002C0C 0xC1BEF1A9
+
+    # release core1
+    dmi_write_memory 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+$_TARGET1 configure -event examine-start {
+    release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+    $::_TARGET0 arp_poll
+    release_core1
+}
+
@@ -0,0 +1,13 @@
+# Copyright 2021 hpmicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+set _CHIP hpm6280
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+targets $_TARGET0
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2022 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern const struct fal_flash_dev stm32f2_onchip_flash;
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2022 hpmicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -7,16 +7,12 @@

 #ifndef HPM_PINMUX_H
 #define HPM_PINMUX_H
-#include "hpm_soc.h"

 #ifdef __cplusplus
 extern "C" {
 #endif
 void init_uart_pins(UART_Type *ptr);
-void init_lcd_pins(LCDC_Type *ptr);
 void init_i2c_pins(I2C_Type *ptr);
-void init_cap_pins(void);
-void init_sdram_pins(void);
 void init_gpio_pins(void);
 void init_spi_pins(SPI_Type *ptr);
 void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
@@ -24,30 +20,23 @@ void init_pins(void);
 void init_gptmr_pins(GPTMR_Type *ptr);
 void init_hall_trgm_pins(void);
 void init_qei_trgm_pins(void);
-void init_i2s_pins(I2S_Type *ptr);
-void init_dao_pins(void);
-void init_pdm_pins(void);
-void init_vad_pins(void);
-void init_cam_pins(CAM_Type *ptr);
-void init_fpga_power_pins(void);
 void init_butn_pins(void);
 void init_acmp_pins(void);
-void init_enet_pins(ENET_Type *ptr);
 void init_pwm_pins(PWM_Type *ptr);
+void init_hrpwm_pins(PWM_Type *ptr);
 void init_adc_pins(void);
-void init_usb_pins(USB_Type *ptr);
-void init_can_pins(CAN_Type *ptr);
-void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8);
-void init_adc12_pins(void);
-void init_adc16_pins(void);
+void init_dac_pins(DAC_Type *ptr);
+void init_usb_pins(void);
+void init_can_pins(MCAN_Type *ptr);
 void init_adc_bldc_pins(void);
-
+void init_rgb_pwm_pins(void);
 void init_i2c_pins_as_gpio(I2C_Type *ptr);
-
-void init_beep_pwm_pins(void);
-void init_led_pins_as_pwm(void);
 void init_led_pins_as_gpio(void);
+void init_led_pins_as_pwm(void);
 void init_trgmux_pins(uint32_t pin);
+void init_pla_pins(void);
+void init_lin_pins(LIN_Type *ptr);
+void init_sdm_pins(void);
 #ifdef __cplusplus
 }
 #endif
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+   gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+
+void BOARD_LED_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    clock_cpu_delay_us(us);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <drv_gpio.h>
+
+/* gpio section */
+#define APP_LED0_PIN_NUM GET_PIN(B, 19)
+#define APP_LED_ON (1)
+#define APP_LED_OFF (0)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can0"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */
@@ -0,0 +1,108 @@
+# Copyright 2021-2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+CHIP_NAME='HPM6280'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+# Fallback toolchain info
+FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
+FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
+FALLBACK_TOOLCHAIN_VER='2022-04-12'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+if RTT_EXEC_PATH != None:
+    folders = RTT_EXEC_PATH.split(os.sep)
+    # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
+    if 'arm_gcc' in folders and 'platform' in folders:
+        RTT_EXEC_PATH = ''
+        for path in folders:
+            if path != 'platform':
+                RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
+            else:
+                break
+        RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
+    # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
+    if 'platform' in folders:
+        os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    ARCH_ABI = ' -mcmodel=medlow '
+    CFLAGS = ARCH_ABI  + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = CFLAGS +  ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    CFLAGS = CFLAGS + ' -std=gnu11'
@@ -12,6 +12,7 @@ src = Split('''

 if rtconfig.PLATFORM == 'gcc':
    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+    src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]

 CPPPATH = [cwd]
 CPPDEFINES=['D45', rtconfig.CHIP_NAME]
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 *
 */
@@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void)

    extern uint8_t __etext[];
    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __tbss_start__[], __tbss_end__[];
+    extern uint8_t __tdata_start__[], __tdata_end__[];
    extern uint8_t __data_start__[], __data_end__[];
    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];

+    /* tbss section */
+    size = __tbss_end__ - __tbss_start__;
+    for (i = 0; i < size; i++) {
+        *(__tbss_start__ + i) = 0;
+    }
+
    /* bss section */
    size = __bss_end__ - __bss_start__;
    for (i = 0; i < size; i++) {
@@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void)
        *(__noncacheable_bss_start__ + i) = 0;
    }

+    /* tdata section LMA: etext */
+    size = __tdata_end__ - __tdata_start__;
+    for (i = 0; i < size; i++) {
+        *(__tdata_start__ + i) = *(__etext + i);
+    }
+
    /* data section LMA: etext */
    size = __data_end__ - __data_start__;
    for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + i);
+        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
    }

    /* ramfunc section LMA: etext + data length */
    size = __ramfunc_end__ - __ramfunc_start__;
    for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
    }

    /* noncacheable init section LMA: etext + data length + ramfunc length */
    size = __noncacheable_init_end__ - __noncacheable_init_start__;
    for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
    }
 }

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "cpuport.h"
+
+    .globl rt_hw_do_after_save_above
+    .type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, trap_entry
+    jalr    t2
+
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -16,14 +16,9 @@ _start:
    .option push
    .option norelax
    la gp, __global_pointer$
+    la tp, __thread_pointer
    .option pop

-#ifdef INIT_EXT_RAM_FOR_DATA
-    la t0, _stack_in_dlm
-    mv sp, t0
-    call _init_ext_ram
-#endif
-
    /* Initialize stack pointer */
    la t0, _stack
    mv sp, t0
@@ -44,7 +39,6 @@ _start:
 #endif
    /* Disable Vector mode */
    csrci CSR_MMISC_CTL, 2
-
    /* Initialize trap_entry base */
    la t0, SW_handler
    csrw mtvec, t0
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .vector_table, "a"
+.global __vector_table
+.align 9
+
+__vector_table:
+    .weak default_isr_trap
+    .set default_isr_trap, SW_handler
+    .long default_isr_trap
+    IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
+    IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
+    IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
+    IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
+    IRQ_HANDLER 5 /* GPIO0_X IRQ handler */
+    IRQ_HANDLER 6 /* GPIO0_Y IRQ handler */
+    IRQ_HANDLER 7 /* GPIO0_Z IRQ handler */
+    IRQ_HANDLER 8 /* GPIO1_A IRQ handler */
+    IRQ_HANDLER 9 /* GPIO1_B IRQ handler */
+    IRQ_HANDLER 10 /* GPIO1_C IRQ handler */
+    IRQ_HANDLER 11 /* GPIO1_D IRQ handler */
+    IRQ_HANDLER 12 /* GPIO1_X IRQ handler */
+    IRQ_HANDLER 13 /* GPIO1_Y IRQ handler */
+    IRQ_HANDLER 14 /* GPIO1_Z IRQ handler */
+    IRQ_HANDLER 15 /* ADC0 IRQ handler */
+    IRQ_HANDLER 16 /* ADC1 IRQ handler */
+    IRQ_HANDLER 17 /* ADC2 IRQ handler */
+    IRQ_HANDLER 18 /* SDFM IRQ handler */
+    IRQ_HANDLER 19 /* DAC0 IRQ handler */
+    IRQ_HANDLER 20 /* DAC1 IRQ handler */
+    IRQ_HANDLER 21 /* ACMP[0] IRQ handler */
+    IRQ_HANDLER 22 /* ACMP[1] IRQ handler */
+    IRQ_HANDLER 23 /* ACMP[2] IRQ handler */
+    IRQ_HANDLER 24 /* ACMP[3] IRQ handler */
+    IRQ_HANDLER 25 /* SPI0 IRQ handler */
+    IRQ_HANDLER 26 /* SPI1 IRQ handler */
+    IRQ_HANDLER 27 /* SPI2 IRQ handler */
+    IRQ_HANDLER 28 /* SPI3 IRQ handler */
+    IRQ_HANDLER 29 /* UART0 IRQ handler */
+    IRQ_HANDLER 30 /* UART1 IRQ handler */
+    IRQ_HANDLER 31 /* UART2 IRQ handler */
+    IRQ_HANDLER 32 /* UART3 IRQ handler */
+    IRQ_HANDLER 33 /* UART4 IRQ handler */
+    IRQ_HANDLER 34 /* UART5 IRQ handler */
+    IRQ_HANDLER 35 /* UART6 IRQ handler */
+    IRQ_HANDLER 36 /* UART7 IRQ handler */
+    IRQ_HANDLER 37 /* CAN0 IRQ handler */
+    IRQ_HANDLER 38 /* CAN1 IRQ handler */
+    IRQ_HANDLER 39 /* CAN2 IRQ handler */
+    IRQ_HANDLER 40 /* CAN3 IRQ handler */
+    IRQ_HANDLER 41 /* PTPC IRQ handler */
+    IRQ_HANDLER 42 /* WDG0 IRQ handler */
+    IRQ_HANDLER 43 /* WDG1 IRQ handler */
+    IRQ_HANDLER 44 /* TSNS IRQ handler */
+    IRQ_HANDLER 45 /* MBX0A IRQ handler */
+    IRQ_HANDLER 46 /* MBX0B IRQ handler */
+    IRQ_HANDLER 47 /* MBX1A IRQ handler */
+    IRQ_HANDLER 48 /* MBX1B IRQ handler */
+    IRQ_HANDLER 49 /* GPTMR0 IRQ handler */
+    IRQ_HANDLER 50 /* GPTMR1 IRQ handler */
+    IRQ_HANDLER 51 /* GPTMR2 IRQ handler */
+    IRQ_HANDLER 52 /* GPTMR3 IRQ handler */
+    IRQ_HANDLER 53 /* I2C0 IRQ handler */
+    IRQ_HANDLER 54 /* I2C1 IRQ handler */
+    IRQ_HANDLER 55 /* I2C2 IRQ handler */
+    IRQ_HANDLER 56 /* I2C3 IRQ handler */
+    IRQ_HANDLER 57 /* PWM0 IRQ handler */
+    IRQ_HANDLER 58 /* HALL0 IRQ handler */
+    IRQ_HANDLER 59 /* QEI0 IRQ handler */
+    IRQ_HANDLER 60 /* PWM1 IRQ handler */
+    IRQ_HANDLER 61 /* HALL1 IRQ handler */
+    IRQ_HANDLER 62 /* QEI1 IRQ handler */
+    IRQ_HANDLER 63 /* PWM2 IRQ handler */
+    IRQ_HANDLER 64 /* HALL2 IRQ handler */
+    IRQ_HANDLER 65 /* QEI2 IRQ handler */
+    IRQ_HANDLER 66 /* PWM3 IRQ handler */
+    IRQ_HANDLER 67 /* HALL3 IRQ handler */
+    IRQ_HANDLER 68 /* QEI3 IRQ handler */
+    IRQ_HANDLER 69 /* SDP IRQ handler */
+    IRQ_HANDLER 70 /* XPI0 IRQ handler */
+    IRQ_HANDLER 71 /* XDMA IRQ handler */
+    IRQ_HANDLER 72 /* HDMA IRQ handler */
+    IRQ_HANDLER 73 /* RNG IRQ handler */
+    IRQ_HANDLER 74 /* USB0 IRQ handler */
+    IRQ_HANDLER 75 /* PSEC IRQ handler */
+    IRQ_HANDLER 76 /* PGPIO IRQ handler */
+    IRQ_HANDLER 77 /* PWDG IRQ handler */
+    IRQ_HANDLER 78 /* PTMR IRQ handler */
+    IRQ_HANDLER 79 /* PUART IRQ handler */
+    IRQ_HANDLER 80 /* FUSE IRQ handler */
+    IRQ_HANDLER 81 /* SECMON IRQ handler */
+    IRQ_HANDLER 82 /* RTC IRQ handler */
+    IRQ_HANDLER 83 /* BUTN IRQ handler */
+    IRQ_HANDLER 84 /* BGPIO IRQ handler */
+    IRQ_HANDLER 85 /* BVIO IRQ handler */
+    IRQ_HANDLER 86 /* BROWNOUT IRQ handler */
+    IRQ_HANDLER 87 /* SYSCTL IRQ handler */
+    IRQ_HANDLER 88 /* DEBUG[0] IRQ handler */
+    IRQ_HANDLER 89 /* DEBUG[1] IRQ handler */
+    IRQ_HANDLER 90 /* LIN0 IRQ handler */
+    IRQ_HANDLER 91 /* LIN1 IRQ handler */
+    IRQ_HANDLER 92 /* LIN2 IRQ handler */
+    IRQ_HANDLER 93 /* LIN3 IRQ handler */
@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')
@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"
@@ -0,0 +1,116 @@
+# HPMicro HPM6300EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provides brief introduction of the BSP (board support package) for the HPM6300EVK development board.
+
+The document consists of the following parts:
+
+- HPM6300EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6300EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| Ethernet                 | √           | Supported by RT-Thread Industry IO    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6300EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6300evk)
@@ -0,0 +1,115 @@
+# 先楫 HPM6300EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6300EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6300EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+ HPM6300EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 由RT-Thread Industry IO扩展板提供支持    |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6360.cfg -f boards\debug_scripts\boards\hpm6300evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6300EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6300evk)
@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
@@ -0,0 +1,75 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
+    CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
+
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
+    libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
+else:
+    libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hpm_library = 'hpm_sdk'
+rtconfig.BSP_LIBRARY_TYPE = hpm_library
+
+# include soc
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
+
+# include components
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
+
+
+# includes rtt drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers',  'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)
@@ -9,6 +9,6 @@ src = Glob('*.c')
 CPPDEFINES=[]
 CPPPATH = [cwd]

-group = DefineGroup('board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)

 Return('group')
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * Change Logs:
+ * Date         Author          Notes
+ * 2021-08-13   Fan YANG        first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "rtt_board.h"
+#include <drv_gpio.h>
+
+void thread_entry(void *arg);
+
+
+int main(void)
+{
+    static uint32_t led_thread_arg = 0;
+    rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
+    rt_thread_startup(led_thread);
+
+    return 0;
+}
+
+
+void thread_entry(void *arg)
+{
+    rt_pin_mode(APP_LED0_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while(1){
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_ON);
+        rt_thread_mdelay(500);
+        rt_pin_write(APP_LED0_PIN_NUM, APP_LED_OFF);
+        rt_thread_mdelay(500);
+    }
+}
@@ -0,0 +1,19 @@
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers
+src = Split("""
+    board.c
+    rtt_board.c
+    pinmux.c
+    fal_flash_port.c
+    eth_phy_port.c
+""")
+
+CPPPATH = [cwd]
+CPPDEFINES=['D45', 'HPM6360']
+
+group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -41,10 +41,10 @@
 #define BOARD_APP_UART_CLK_NAME clock_uart0

 #ifndef BOARD_CONSOLE_TYPE
-#define BOARD_CONSOLE_TYPE console_type_uart
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
 #endif

-#if console_type_uart == BOARD_CONSOLE_TYPE
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_BASE
 #if BOARD_RUNNING_CORE == HPM_CORE0
 #define BOARD_CONSOLE_BASE HPM_UART0
@@ -80,8 +80,8 @@
 /* sdram section */
 #define BOARD_SDRAM_ADDRESS  (0x40000000UL)
 #define BOARD_SDRAM_SIZE     (32*SIZE_1MB)
-#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
-#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_16_BITS
+#define BOARD_SDRAM_CS       FEMC_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_16_BITS
 #define BOARD_SDRAM_REFRESH_COUNT (8192UL)
 #define BOARD_SDRAM_REFRESH_IN_MS (64UL)
 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL)
@@ -149,22 +149,18 @@
 #define BOARD_APP_SPI_RX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX0
 #define BOARD_APP_SPI_TX_DMA HPM_DMA_SRC_SPI3_TX
 #define BOARD_APP_SPI_TX_DMAMUX_CH DMAMUX_MUXCFG_HDMA_MUX1
-#define BOARD_SPI_CS_GPIO_CTRL           HPM_GPIO0
-#define BOARD_SPI_CS_PIN                 IOC_PAD_PC18
-#define BOARD_SPI_CS_ACTIVE_LEVEL        (0U)
+

 /* Flash section */
 #define BOARD_APP_XPI_NOR_XPI_BASE            (HPM_XPI0)
 #define BOARD_APP_XPI_NOR_CFG_OPT_HDR         (0xfcf90001U)
-#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000005U)
+#define BOARD_APP_XPI_NOR_CFG_OPT_OPT0        (0x00000007U)
 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)

 /* i2s section */
 #define BOARD_APP_I2S_BASE HPM_I2S0
 #define BOARD_APP_I2S_DATA_LINE      (2U)
 #define BOARD_APP_I2S_CLK_NAME clock_i2s0
-#define BOARD_APP_AUDIO_CLK_SRC clock_source_pll2_clk0
-#define BOARD_APP_AUDIO_CLK_SRC_NAME clk_pll2clk0

 /* enet section */
 #define BOARD_ENET_RMII                 HPM_ENET0
@@ -174,12 +170,30 @@
 #define BOARD_ENET_RMII                 HPM_ENET0
 #define BOARD_ENET_RMII_INT_REF_CLK     (1U)
 #define BOARD_ENET_RMII_PTP_CLOCK       (clock_ptp0)
+#define BOARD_ENET0_INF             (0U)  /* 0: RMII, 1: RGMII */
+#define BOARD_ENET0_INT_REF_CLK     (0U)
+#define BOARD_ENET0_PHY_RST_TIME    (30)
+
+
+#if BOARD_ENET0_INF
+#define BOARD_ENET0_TX_DLY          (0U)
+#define BOARD_ENET0_RX_DLY          (0U)
+#endif
+
+#if __USE_ENET_PTP
+#define BOARD_ENET0_PTP_CLOCK       (clock_ptp0)
+#endif
+

 /* ADC section */
 #define BOARD_APP_ADC16_NAME "ADC0"
 #define BOARD_APP_ADC16_BASE HPM_ADC0
 #define BOARD_APP_ADC16_IRQn IRQn_ADC0
-#define BOARD_APP_ADC16_CH_1                     (13U)
+#define BOARD_APP_ADC16_CH                       (13U)
+#define BOARD_APP_ADC_SEQ_DMA_SIZE_IN_4BYTES     (1024U)
+#define BOARD_APP_ADC_PMT_DMA_SIZE_IN_4BYTES     (192U)
+#define BOARD_APP_ADC_PREEMPT_TRIG_LEN           (1U)
+#define BOARD_APP_ADC_SINGLE_CONV_CNT            (6)
 #define BOARD_APP_ADC_TRIG_PWMT0                 HPM_PWM0
 #define BOARD_APP_ADC_TRIG_PWMT1                 HPM_PWM1
 #define BOARD_APP_ADC_TRIG_TRGM0                 HPM_TRGM0
@@ -208,15 +222,10 @@
 #define BOARD_CALLBACK_TIMER_CLK_NAME (clock_gptmr3)

 /* SDXC section */
-#define BOARD_APP_SDCARD_SDXC_BASE                  (HPM_SDXC0)
-#define BOARD_APP_SDCARD_SUPPORT_1V8                (0)
-#define BOARD_APP_SDCARD_SUPPORT_CARD_DETECTION     (1)
-#define BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO  (0)
-#if BOARD_APP_SDCARD_CARD_DETECTION_USING_GPIO
-#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO        NULL
-#define BOARD_APP_SDCARD_CARD_DETECTION_GPIO_INDEX  0
-#define BOARD_APP_SDCARD_CARD_DETECTION_PIN_INDEX   0
-#endif
+#define BOARD_APP_SDCARD_SDXC_BASE            (HPM_SDXC0)
+#define BOARD_APP_SDCARD_CDN_GPIO_CTRL        (HPM_GPIO0)
+#define BOARD_APP_SDCARD_CDN_GPIO_PIN         (15UL)
+#define BOARD_APP_SDCARD_SUPPORT_1V8          (0)

 /* USB section */
 #define BOARD_USB0_ID_PORT       (HPM_GPIO0)
@@ -328,13 +337,11 @@ void board_init_i2c(I2C_Type *ptr);

 void board_init_can(CAN_Type *ptr);

-uint32_t board_init_dram_clock(void);
+uint32_t board_init_femc_clock(void);

 void board_init_sdram_pins(void);
 void board_init_gpio_pins(void);
 void board_init_spi_pins(SPI_Type *ptr);
-void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
-void board_write_spi_cs(uint32_t pin, uint8_t state);
 void board_init_led_pins(void);

 void board_led_write(uint8_t state);
@@ -354,7 +361,7 @@ void board_init_adc16_pins(void);
 void board_init_dac_pins(DAC_Type *ptr);

 uint32_t board_init_can_clock(CAN_Type *ptr);
-
+uint32_t board_init_gptmr_clock(GPTMR_Type *ptr);
 uint32_t board_init_i2s_clock(I2S_Type *ptr);
 uint32_t board_init_pdm_clock(void);
 uint32_t board_init_dao_clock(void);
@@ -363,15 +370,19 @@ void board_init_sd_pins(SDXC_Type *ptr);
 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
 bool board_sd_detect_card(SDXC_Type *ptr);
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off);

 void board_init_usb_pins(void);
 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);
 uint8_t board_get_usb_id_status(void);

+uint8_t    board_enet_get_dma_pbl(ENET_Type *ptr);
+hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
 hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);
 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
-
+hpm_stat_t board_enet_enable_irq(ENET_Type *ptr);
+hpm_stat_t board_enet_disable_irq(ENET_Type *ptr);
 /*
 * @brief Initialize PMP and PMA for but not limited to the following purposes:
 *      -- non-cacheable memory initialization
@@ -0,0 +1,50 @@
+riscv expose_csrs 262
+riscv expose_csrs 800
+riscv expose_csrs 1984
+riscv expose_csrs 1985
+riscv expose_csrs 1986
+riscv expose_csrs 1987
+riscv expose_csrs 1988
+riscv expose_csrs 1989
+riscv expose_csrs 1990
+riscv expose_csrs 1991
+riscv expose_csrs 1992
+riscv expose_csrs 1993
+riscv expose_csrs 1994
+riscv expose_csrs 1995
+riscv expose_csrs 1996
+riscv expose_csrs 1997
+riscv expose_csrs 1998
+riscv expose_csrs 1999
+riscv expose_csrs 2000
+riscv expose_csrs 2001
+riscv expose_csrs 2002
+riscv expose_csrs 2003
+riscv expose_csrs 2004
+riscv expose_csrs 2005
+riscv expose_csrs 2015
+riscv expose_csrs 2016
+riscv expose_csrs 2017
+riscv expose_csrs 2048
+riscv expose_csrs 2049
+riscv expose_csrs 2057
+riscv expose_csrs 2059
+riscv expose_csrs 2060
+riscv expose_csrs 2500
+riscv expose_csrs 2501
+riscv expose_csrs 2505
+riscv expose_csrs 2509
+riscv expose_csrs 2511
+riscv expose_csrs 2513
+riscv expose_csrs 2514
+riscv expose_csrs 2515
+riscv expose_csrs 2516
+riscv expose_csrs 2528
+riscv expose_csrs 2531
+riscv expose_csrs 2532
+riscv expose_csrs 2533
+riscv expose_csrs 2534
+riscv expose_csrs 4032
+riscv expose_csrs 4033
+riscv expose_csrs 4034
+riscv expose_csrs 4035
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef ETH_PHY_PORT_H
+#define ETH_PHY_PORT_H
+
+#include "hpm_ioc_regs.h"
+#include <rtdevice.h>
+
+#ifndef PHY_AUTO_NEGO
+#define PHY_AUTO_NEGO  (1U)
+#endif
+
+#ifndef PHY_MDIO_CSR_CLK_FREQ
+#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
+#endif
+
+enum phy_link_status
+{
+   PHY_LINK_DOWN = 0U,
+   PHY_LINK_UP
+};
+
+typedef struct {
+    rt_uint32_t phy_speed;
+    rt_uint32_t phy_duplex;
+} phy_info_t;
+
+typedef struct {
+    rt_uint32_t phy_link;
+    rt_phy_t phy;
+    phy_info_t phy_info;
+} phy_device_t;
+
+/** @note PHY: RTL8201 */
+
+#define PHY_NAME    ("RTL8201")
+#define PHY_ID1     (0x1CU)
+
+/* The PHY basic control register */
+#define PHY_BASIC_CONTROL_REG       (0x00U)
+#define PHY_RESET_MASK              (1U << 15)
+#define PHY_AUTO_NEGOTIATION_MASK   (1U << 12)
+
+/* The PHY basic status register */
+#define PHY_BASIC_STATUS_REG        (0x01U)
+#define PHY_LINKED_STATUS_MASK      (1U << 2)
+#define PHY_AUTONEGO_COMPLETE_MASK  (1U << 5)
+
+/* The PHY ID one register */
+#define PHY_ID1_REG                 (0x02U)
+
+/* The PHY ID two register */
+#define PHY_ID2_REG                 (0x03U)
+
+/* The PHY auto-negotiate advertise register */
+#define PHY_AUTONEG_ADVERTISE_REG   (0x04U)
+
+/*  The PHY status register. */
+#define PHY_STATUS_REG              (0x00U)
+#define PHY_10M_MASK                (1 << 13)
+#define PHY_100M_MASK               (1 << 13)
+#define PHY_FULL_DUPLEX_MASK        (1 << 8)
+#define PHY_STATUS_SPEED_10M(SR)    ((SR) & PHY_100M_MASK) ? 0: 1
+#define PHY_STATUS_SPEED_100M(SR)   ((SR) & PHY_100M_MASK)
+#define PHY_STATUS_FULL_DUPLEX(SR)  ((SR) & PHY_FULL_DUPLEX_MASK)
+
+/* PHY0 register list */
+#define PHY0_REG_LIST  PHY_BASIC_CONTROL_REG,\
+                       PHY_BASIC_STATUS_REG,\
+                       PHY_ID1_REG,\
+                       PHY_ID2_REG,\
+                       PHY_AUTONEG_ADVERTISE_REG,\
+                       PHY_STATUS_REG
+
+/* PHY0 register index */
+#define PHY_BASIC_STATUS_REG_IDX (1U)
+#define PHY_ID1_REG_IDX          (2U)
+#define PHY_STATUS_REG_IDX       (5U)
+
+#endif
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#ifdef RT_USING_FAL
+#define NOR_FLASH_DEV_NAME             "norflash0"
+#define NOR_FLASH_MEM_BASE             0x80000000UL
+#define NOR_FLASH_SIZE_IN_BYTES        0x1000000UL
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                               \
+{                                                                                    \
+    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* RT_USING_FAL */
+
+#endif /* _FAL_CFG_H_ */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -28,6 +28,9 @@ void init_uart_pins(UART_Type *ptr)
    } else if (ptr == HPM_UART2) {
        HPM_IOC->PAD[IOC_PAD_PC26].FUNC_CTL = IOC_PC26_FUNC_CTL_UART2_TXD;
        HPM_IOC->PAD[IOC_PAD_PC27].FUNC_CTL = IOC_PC27_FUNC_CTL_UART2_RXD;
+    } else if (ptr == HPM_PUART) {
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_PUART_RXD;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_PUART_TXD;
    }
 }

@@ -135,16 +138,6 @@ void init_spi_pins(SPI_Type *ptr)
    }
 }

-void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
-{
-    if (ptr == HPM_SPI3) {
-        HPM_IOC->PAD[IOC_PAD_PC18].FUNC_CTL = IOC_PC18_FUNC_CTL_GPIO_C_18;
-        HPM_IOC->PAD[IOC_PAD_PC21].FUNC_CTL = IOC_PC21_FUNC_CTL_SPI3_MOSI;
-        HPM_IOC->PAD[IOC_PAD_PC19].FUNC_CTL = IOC_PC19_FUNC_CTL_SPI3_MISO;
-        HPM_IOC->PAD[IOC_PAD_PC20].FUNC_CTL = IOC_PC20_FUNC_CTL_SPI3_SCLK | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
-    }
-}
-
 void init_pins(void)
 {
    init_uart_pins(BOARD_CONSOLE_BASE);
@@ -174,8 +167,8 @@ void init_qei_trgm_pins(void)

 void init_butn_pins(void)
 {
-    /* HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN; */
-    /* HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN; */
+    // HPM_BIOC->PAD[IOC_PAD_PZ02].FUNC_CTL = IOC_PZ02_FUNC_CTL_PBUTN;
+    // HPM_BIOC->PAD[IOC_PAD_PZ03].FUNC_CTL = IOC_PZ03_FUNC_CTL_WBUTN;
 }

 void init_acmp_pins(void)
@@ -248,6 +241,23 @@ void init_can_pins(CAN_Type *ptr)
    }
 }

+void init_sdxc_power_pin(SDXC_Type *ptr)
+{
+
+}
+
+void init_sdxc_vsel_pin(SDXC_Type *ptr)
+{
+
+}
+
+void init_sdxc_card_detection_pin(SDXC_Type *ptr)
+{
+     /* SDXC0.CD */
+    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
+    HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) | IOC_PAD_PAD_CTL_PS_SET(1);
+}
+
 void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
 {
    uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
@@ -262,10 +272,6 @@ void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
    HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = func_ctl;
    HPM_IOC->PAD[IOC_PAD_PA10].PAD_CTL = pad_ctl;

-    /* SDXC0.CD */
-    HPM_IOC->PAD[IOC_PAD_PA14].FUNC_CTL = func_ctl;
-    HPM_IOC->PAD[IOC_PAD_PA14].PAD_CTL = pad_ctl;
-
    /* SDXC0.DATA0 */
    HPM_IOC->PAD[IOC_PAD_PA12].FUNC_CTL = func_ctl;
    HPM_IOC->PAD[IOC_PAD_PA12].PAD_CTL = pad_ctl;
@@ -1,5 +1,5 @@
 /*
- *Copyright (c) 2022 hpmicro
+ *Copyright (c) 2022-2023 HPMicro
 *
 *SPDX-License-Identifier: BSD-3-Clause
 *
@@ -16,7 +16,6 @@ void init_i2c_pins(I2C_Type *ptr);
 void init_sdram_pins(void);
 void init_gpio_pins(void);
 void init_spi_pins(SPI_Type *ptr);
-void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
 void init_pins(void);
 void init_gptmr_pins(GPTMR_Type *ptr);
 void init_hall_trgm_pins(void);
@@ -29,6 +28,9 @@ void init_adc_pins(void);
 void init_dac_pins(DAC_Type *ptr);
 void init_usb_pins(void);
 void init_can_pins(CAN_Type *ptr);
+void init_sdxc_power_pin(SDXC_Type *ptr);
+void init_sdxc_vsel_pin(SDXC_Type *ptr);
+void init_sdxc_card_detection_pin(SDXC_Type *ptr);
 void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8);
 void init_adc_bldc_pins(void);
 void init_rgb_pwm_pins(void);
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021-2022 HPMicro
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "board.h"
+#include "rtt_board.h"
+#include "hpm_uart_drv.h"
+#include "hpm_gpio_drv.h"
+#include "hpm_mchtmr_drv.h"
+#include "hpm_pmp_drv.h"
+#include "assert.h"
+#include "hpm_clock_drv.h"
+#include "hpm_sysctl_drv.h"
+#include <rthw.h>
+#include <rtthread.h>
+#include "hpm_dma_manager.h"
+
+void os_tick_config(void);
+
+extern int rt_hw_uart_init(void);
+
+void rtt_board_init(void)
+{
+    board_init_clock();
+    board_init_console();
+    board_init_pmp();
+
+    dma_manager_init();
+
+    /* initialize memory system */
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+
+    /* Configure the OS Tick */
+    os_tick_config();
+
+    /* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
+    rt_hw_uart_init();
+
+    /* Set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+void app_init_led_pins(void)
+{
+    gpio_set_pin_output(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
+    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, BOARD_LED_OFF_LEVEL);
+}
+
+void app_led_write(uint32_t index, bool state)
+{
+   gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+}
+
+
+void BOARD_LED_write(uint32_t index, bool state)
+{
+    switch (index)
+    {
+    case 0:
+        gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
+        break;
+    default:
+        /* Suppress the toolchain warnings */
+        break;
+    }
+}
+
+void os_tick_config(void)
+{
+    sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
+    sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
+
+    mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
+
+    enable_mchtmr_irq();
+}
+
+void rt_hw_board_init(void)
+{
+    rtt_board_init();
+
+    /* Call the RT-Thread Component Board Initialization */
+    rt_components_board_init();
+}
+
+void rt_hw_console_output(const char *str)
+{
+    while (*str != '\0')
+    {
+        uart_send_byte(BOARD_APP_UART_BASE, *str++);
+    }
+}
+
+ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
+{
+    HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
+
+    rt_interrupt_enter();
+    rt_tick_increase();
+    rt_interrupt_leave();
+}
+
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    clock_cpu_delay_us(us);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    HPM_PPOR->RESET_ENABLE = (1UL << 31);
+    HPM_PPOR->RESET_HOT &= ~(1UL << 31);
+    HPM_PPOR->RESET_COLD |= (1UL << 31);
+
+    HPM_PPOR->SOFTWARE_RESET = 1000U;
+    while(1) {
+
+    }
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021 hpmicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RTT_BOARD_H
+#define _RTT_BOARD_H
+#include "hpm_common.h"
+#include "hpm_soc.h"
+#include <drv_gpio.h>
+
+/* gpio section */
+#define APP_LED0_PIN_NUM GET_PIN(A, 7)
+#define APP_LED_ON (0)
+#define APP_LED_OFF (1)
+
+
+
+/* mchtimer section */
+#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
+
+/* CAN section */
+#define BOARD_CAN_NAME                        "can0"
+
+/***************************************************************
+ *
+ * RT-Thread related definitions
+ *
+ **************************************************************/
+extern unsigned int __heap_start__;
+extern unsigned int __heap_end__;
+
+#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
+#define RT_HW_HEAP_END ((void*)&__heap_end__)
+
+
+typedef struct {
+    uint16_t vdd;
+    uint8_t bus_width;
+    uint8_t drive_strength;
+}sdxc_io_cfg_t;
+
+void app_init_led_pins(void);
+void app_led_write(uint32_t index, bool state);
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+
+
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+#endif /* _RTT_BOARD_H */
@@ -0,0 +1,108 @@
+# Copyright 2021-2023 HPMicro
+# SPDX-License-Identifier: BSD-3-Clause
+
+import os
+import sys
+
+# toolchains options
+ARCH='risc-v'
+CPU='hpmicro'
+CHIP_NAME='HPM6360'
+
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+# Fallback toolchain info
+FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
+FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
+FALLBACK_TOOLCHAIN_VER='2022-04-12'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+if RTT_EXEC_PATH != None:
+    folders = RTT_EXEC_PATH.split(os.sep)
+    # If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
+    if 'arm_gcc' in folders and 'platform' in folders:
+        RTT_EXEC_PATH = ''
+        for path in folders:
+            if path != 'platform':
+                RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
+            else:
+                break
+        RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
+    # Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
+    if 'platform' in folders:
+        os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_RISCV_TOOLCHAIN'):
+        EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
+    else:
+        EXEC_PATH   = r'/opt/riscv-gnu-gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+BUILD = 'flash_debug'
+
+if PLATFORM == 'gcc':
+    PREFIX = 'riscv32-unknown-elf-'
+    CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    GDB = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
+
+    ARCH_ABI = ' -mcmodel=medlow '
+    CFLAGS = ARCH_ABI  + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS = CFLAGS
+    LFLAGS  = ARCH_ABI + '  --specs=nano.specs --specs=nosys.specs  -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'ram_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'ram_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
+    elif BUILD == 'flash_debug':
+        CFLAGS += ' -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+        CFLAGS += ' -O0'
+        LFLAGS += ' -O0'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    elif BUILD == 'flash_release':
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        CFLAGS += ' -DFLASH_XIP=1'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    else:
+        CFLAGS += ' -O2 -Os'
+        LFLAGS += ' -O2 -Os'
+        LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
+    LFLAGS += ' -T ' + LINKER_FILE
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+    # module setting
+    CXXFLAGS = CFLAGS +  ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    CFLAGS = CFLAGS + ' -std=gnu11'
@@ -12,6 +12,7 @@ src = Split('''

 if rtconfig.PLATFORM == 'gcc':
    src += [os.path.join('toolchains', 'gcc', 'start.S')]
+    src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]

 CPPPATH = [cwd]
 CPPDEFINES=['D45', rtconfig.CHIP_NAME]
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 - 2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 *
 */
@@ -43,11 +43,19 @@ __attribute__((weak)) void c_startup(void)

    extern uint8_t __etext[];
    extern uint8_t __bss_start__[], __bss_end__[];
+    extern uint8_t __tbss_start__[], __tbss_end__[];
+    extern uint8_t __tdata_start__[], __tdata_end__[];
    extern uint8_t __data_start__[], __data_end__[];
    extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
    extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
    extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];

+    /* tbss section */
+    size = __tbss_end__ - __tbss_start__;
+    for (i = 0; i < size; i++) {
+        *(__tbss_start__ + i) = 0;
+    }
+
    /* bss section */
    size = __bss_end__ - __bss_start__;
    for (i = 0; i < size; i++) {
@@ -60,22 +68,28 @@ __attribute__((weak)) void c_startup(void)
        *(__noncacheable_bss_start__ + i) = 0;
    }

+    /* tdata section LMA: etext */
+    size = __tdata_end__ - __tdata_start__;
+    for (i = 0; i < size; i++) {
+        *(__tdata_start__ + i) = *(__etext + i);
+    }
+
    /* data section LMA: etext */
    size = __data_end__ - __data_start__;
    for (i = 0; i < size; i++) {
-        *(__data_start__ + i) = *(__etext + i);
+        *(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
    }

    /* ramfunc section LMA: etext + data length */
    size = __ramfunc_end__ - __ramfunc_start__;
    for (i = 0; i < size; i++) {
-        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __data_start__) + i);
+        *(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
    }

    /* noncacheable init section LMA: etext + data length + ramfunc length */
    size = __noncacheable_init_end__ - __noncacheable_init_start__;
    for (i = 0; i < size; i++) {
-        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __data_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
+        *(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
    }
 }

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#include "cpuport.h"
+
+    .globl rt_hw_do_after_save_above
+    .type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+    csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, trap_entry
+    jalr    t2
+
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -16,6 +16,7 @@ _start:
    .option push
    .option norelax
    la gp, __global_pointer$
+    la tp, __thread_pointer
    .option pop

 #ifdef INIT_EXT_RAM_FOR_DATA
@@ -44,7 +45,6 @@ _start:
 #endif
    /* Disable Vector mode */
    csrci CSR_MMISC_CTL, 2
-
    /* Initialize trap_entry base */
    la t0, SW_handler
    csrw mtvec, t0
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -0,0 +1,13 @@
+# for module compiling
+import os
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+
+objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
+ASFLAGS = ' -I' + cwd
+
+Return('objs')
@@ -0,0 +1,116 @@
+# HPMicro HPM6750EVK BSP(Board Support Package) Introduction
+
+[中文页](README_zh.md) |
+
+## Introduction
+
+This document provide brief introduction of the BSP (board support package) for the HPM6750EVK development board.
+
+The document consists of the following parts:
+
+- HPM6750EVK Board Resources Introduction
+- Quickly Getting Started
+- Refreences
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## Board Resources Introduction
+
+HPM6750EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Display, Audio, motor control, etc.
+![board](figures/board.png)
+
+
+## Peripheral Condition
+
+Each peripheral supporting condition for this BSP is as follows:
+
+
+| **On-board Peripherals** | **Support** | **Note**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| Ethernet                 | √           |  Dual Ethernet Ports                  |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| On-Board Debugger        | √           | ft2232                                |
+
+
+## Execution Instruction
+
+### Quickly Getting Started
+
+The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
+
+#### Parpare Environment
+- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
+- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
+    - For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
+  - Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
+    - For example: `C:\DevTools\openocd-hpmicro\bin`
+
+#### Configure and Build project
+
+Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
+
+- Configure the project via `menuconfig` in `RT-Thread ENV`
+- Build the project using `scons -jN`, `N` equals to the number of CPU cores
+- Clean the project using `scons -c`
+
+#### Hardware Connection
+
+- Switch BOOT pin to 2'b00
+- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
+
+
+#### Dowload / Debug
+
+- Users can download the project via the below command:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- Users can debug the project via the below command:
+
+  - Connect debugger via `OpenOCD`:
+
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg
+```
+  - Start Debugger via `GDB`:
+
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+  - In the `gdb shell`, type the following commands:
+
+```console
+load
+c
+```
+
+### **Running Results**
+
+Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
+
+Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **References**
+
+- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6750EVKMINI RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6750evk)
@@ -0,0 +1,115 @@
+# 先楫 HPM6750EVK BSP(板级支持包)说明
+
+[English](README.md) |
+
+## 简介
+
+本文档为 HPM6750EVK 的 BSP (板级支持包) 说明。
+
+本文包含如下部分:
+
+- HPM6750EVK 板级资源介绍
+- 快速上手指南
+- 参考链接
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 板级资源介绍
+
+HPM6750EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于显示、音频和电机控制等应用。
+
+开发板外观如下图所示：
+
+![board](figures/board.png)
+
+
+## 板载外设
+
+本 BSP 目前对外设的支持情况如下:
+
+
+| **板载外设** | **支持情况** | **备注**                              |
+| ------------------------ | ----------- | ------------------------------------- |
+| USB                      | √           |                                       |
+| QSPI Flash               | √           |                                       |
+| 以太网                    | √           | 双以太网端口                           |
+| GPIO                     | √           |                                       |
+| SPI                      | √           |                                       |
+| I2C                      | √           |                                       |
+| SDIO                     | √           |                                       |
+| RTC                      | √           |                                       |
+| PWM                      | √           |                                       |
+| 板载调试器                | √           | ft2232                                |
+
+
+## 使用说明
+
+### 快速开始
+
+本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
+
+#### 准备环境
+- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
+- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
+    - 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
+- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
+- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.3.0.zip)
+  - 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
+  - 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
+
+#### 配置和构建工程
+
+通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
+
+- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
+- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
+- 通过 `scons -c` 命令清除构建
+
+#### 硬件连接
+
+- 将BOOT 引脚拨到2'b00
+- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
+
+#### 下载 和 调试
+
+- 通过如下命令完成下载:
+  ```console
+  %OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
+  ```
+
+- 通过如下命令实现调试:
+
+  - 通过 `OpenOCD` 来连接开发板:
+```console
+%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6750-single-core.cfg -f boards\debug_scripts\boards\hpm6750evk.cfg
+```
+  - 通过 `GDB` 实现调试:
+```console
+%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
+```
+
+  - 在`GDB Shell`中使用如下命令来加载和运行:
+
+```console
+load
+c
+```
+
+### **运行结果**
+
+一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
+
+配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Aug 16 2023 18:18:18
+ 2006 - 2023 Copyright by RT-Thread team
+```
+
+## **参考链接**
+
+- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
+- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
+- [HPM6750EVKMINI RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6750evk)
@@ -5,7 +5,6 @@ config SOC_HPM6000
    select SOC_SERIES_HPM6000
    select RT_USING_COMPONENTS_INIT
    select RT_USING_USER_MAIN
-    select RT_USING_HW_ATOMIC
    default y

 menu "On-chip Peripheral Drivers"
@@ -247,6 +246,11 @@ menu "On-chip Peripheral Drivers"
        bool "Enable LVGL"
        default n
        select PKG_USING_LVGL if BSP_USING_LVGL
+        select BSP_USING_PDMA if BSP_USING_LVGL
+
+    menuconfig BSP_USING_PDMA
+        bool "Enable PDMA Driver"
+        default n

    menuconfig BSP_USING_GPTMR
        bool "Enable GPTMR"
@@ -286,7 +290,7 @@ menu "On-chip Peripheral Drivers"
                    default y
        endif

-    menuconfig BSP_USING_DRAM
+    menuconfig BSP_USING_FEMC
       bool "Enable DRAM"
       default y
    menuconfig INIT_EXT_RAM_FOR_DATA
@@ -373,6 +377,36 @@ menu "On-chip Peripheral Drivers"
                bool "Enable CAN3"
                default n
     endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC if BSP_USING_ADC
+        if BSP_USING_ADC
+            menuconfig BSP_USING_ADC12
+            bool "Enable ADC12"
+            default n
+                if BSP_USING_ADC12
+                    config BSP_USING_ADC0
+                        bool "Enable ADC0"
+                        default n
+                    config BSP_USING_ADC1
+                        bool "Enable ADC1"
+                        default n
+                    config BSP_USING_ADC2
+                        bool "Enable ADC2"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC16
+            bool "Enable ADC16"
+            default n
+                if BSP_USING_ADC16
+                    config BSP_USING_ADC3
+                        bool "Enable ADC3"
+                        default n
+                endif
+        endif
+
 endmenu


@@ -10,7 +10,6 @@ src = Split("""
    eth_phy_port.c
    fal_flash_port.c
    hpm_sgtl5000.c
-    trap_gcc.S
 """)

 CPPPATH = [cwd]
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -13,6 +13,7 @@
 #include "hpm_soc.h"
 #include "hpm_soc_feature.h"
 #include "pinmux.h"
+#include "hpm_lcdc_drv.h"

 #define BOARD_NAME "hpm6750evk"
 #define BOARD_UF2_SIGNATURE (0x0A4D5048UL)
@@ -50,10 +51,10 @@
 #define BOARD_APP_UART_CLK_NAME clock_uart0

 #ifndef BOARD_CONSOLE_TYPE
-#define BOARD_CONSOLE_TYPE console_type_uart
+#define BOARD_CONSOLE_TYPE CONSOLE_TYPE_UART
 #endif

-#if BOARD_CONSOLE_TYPE == console_type_uart
+#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
 #ifndef BOARD_CONSOLE_BASE
 #if BOARD_RUNNING_CORE == HPM_CORE0
 #define BOARD_CONSOLE_BASE HPM_UART0
@@ -74,8 +75,8 @@
 /* sdram section */
 #define BOARD_SDRAM_ADDRESS  (0x40000000UL)
 #define BOARD_SDRAM_SIZE     (32*SIZE_1MB)
-#define BOARD_SDRAM_CS       DRAM_SDRAM_CS0
-#define BOARD_SDRAM_PORT_SIZE DRAM_SDRAM_PORT_SIZE_32_BITS
+#define BOARD_SDRAM_CS       FEMC_SDRAM_CS0
+#define BOARD_SDRAM_PORT_SIZE FEMC_SDRAM_PORT_SIZE_32_BITS
 #define BOARD_SDRAM_REFRESH_COUNT (8192UL)
 #define BOARD_SDRAM_REFRESH_IN_MS (64UL)
 #define BOARD_SDRAM_DATA_WIDTH_IN_BYTE (4UL)
@@ -201,11 +202,58 @@
 #define BOARD_APP_XPI_NOR_CFG_OPT_OPT1        (0x00001000U)

 /* lcd section */
+
+/*
+ * BOARD_PANEL_TIMING_PARA {HSPW, HBP, HFP, VSPW, VBP, VFP, HSSP, VSSP, DESP, PDSP, PCSP}
+ *
+ * HSPW: Horizontal Synchronization Pulse width
+ * HBP: Horizontal Back Porch
+ * HFP: Horizontal Front Porch
+ * VSPW: Vertical Synchronization Pulse width
+ * VBP: Vertical Back Porch
+ * VFP: Vertical Front Porch
+ * HSSP: Horizontal Synchronization Signal Polarity, 0: High Active, 1: Low Active
+ * VSSP: Vertical Synchronization Signal Polarity, 0: High Active, 1: Low Active
+ * DESP: Data Enable Signal Polarity, 0: High Active, 1: Low Active
+ * PDSP: Pixel Data Signal Polarity, 0: High Active, 1: Low Active
+ * PCSP: Pixel Clock Signal Polarity, 0: High Active, 1: Low Active
+ */
+#define BOARD_PANEL_TIMEING_PARA_HSPW_INDEX 0
+#define BOARD_PANEL_TIMEING_PARA_HBP_INDEX 1
+#define BOARD_PANEL_TIMEING_PARA_HFP_INDEX 2
+#define BOARD_PANEL_TIMEING_PARA_VSPW_INDEX 3
+#define BOARD_PANEL_TIMEING_PARA_VBP_INDEX 4
+#define BOARD_PANEL_TIMEING_PARA_VFP_INDEX 5
+#define BOARD_PANEL_TIMEING_PARA_HSSP_INDEX 6
+#define BOARD_PANEL_TIMEING_PARA_VSSP_INDEX 7
+#define BOARD_PANEL_TIMEING_PARA_DESP_INDEX 8
+#define BOARD_PANEL_TIMEING_PARA_PDSP_INDEX 9
+#define BOARD_PANEL_TIMEING_PARA_PCSP_INDEX 10
+
+#if defined(PANEL_TM070RDH13)
+
 #ifndef BOARD_LCD_WIDTH
-#define BOARD_LCD_WIDTH (800)
+#define BOARD_LCD_WIDTH 800
 #endif
 #ifndef BOARD_LCD_HEIGHT
-#define BOARD_LCD_HEIGHT (480)
+#define BOARD_LCD_HEIGHT 480
+#endif
+#ifndef BOARD_PANEL_TIMING_PARA
+#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0}
+#endif
+
+#else
+
+#ifndef BOARD_LCD_WIDTH
+#define BOARD_LCD_WIDTH 800
+#endif
+#ifndef BOARD_LCD_HEIGHT
+#define BOARD_LCD_HEIGHT 480
+#endif
+#ifndef BOARD_PANEL_TIMING_PARA
+#define BOARD_PANEL_TIMING_PARA {10, 46, 50, 3, 23, 10, 0, 0, 0, 0, 0}
+#endif
+
 #endif

 /* pdma section */
@@ -222,19 +270,33 @@
 #define BOARD_ENET0_RST_GPIO       HPM_GPIO0
 #define BOARD_ENET0_RST_GPIO_INDEX GPIO_DO_GPIOF
 #define BOARD_ENET0_RST_GPIO_PIN   (0U)
-#define BOARD_ENET0_INF            enet_inf_rgmii
-#define BOARD_ENET0                HPM_ENET0
-#define BOARD_ENET0_TX_DLY         (0U)
-#define BOARD_ENET0_RX_DLY         (21U)
-#define BOARD_ENET0_PTP_CLOCK      (clock_ptp0)
+#define BOARD_ENET0_INF             (1U)  /* 0: RMII, 1: RGMII */
+#define BOARD_ENET0_INT_REF_CLK     (0U)
+#define BOARD_ENET0_PHY_RST_TIME    (30)
+#if BOARD_ENET0_INF
+#define BOARD_ENET0_TX_DLY          (0U)
+#define BOARD_ENET0_RX_DLY          (21U)
+#endif
+#if __USE_ENET_PTP
+#define BOARD_ENET0_PTP_CLOCK       (clock_ptp0)
+#endif

 #define BOARD_ENET1_RST_GPIO        HPM_GPIO0
 #define BOARD_ENET1_RST_GPIO_INDEX  GPIO_DO_GPIOE
 #define BOARD_ENET1_RST_GPIO_PIN    (26U)
-#define BOARD_ENET1_INF             enet_inf_rmii
-#define BOARD_ENET1                 HPM_ENET1
+
+#define BOARD_ENET1_INF             (0U)  /* 0: RMII, 1: RGMII */
 #define BOARD_ENET1_INT_REF_CLK     (1U)
+#define BOARD_ENET1_PHY_RST_TIME    (30)
+
+#if BOARD_ENET1_INF
+#define BOARD_ENET1_TX_DLY          (0U)
+#define BOARD_ENET1_RX_DLY          (0U)
+#endif
+
+#if __USE_ENET_PTP
 #define BOARD_ENET1_PTP_CLOCK       (clock_ptp1)
+#endif

 /* ADC section */
 #define BOARD_APP_ADC12_NAME "ADC0"
@@ -429,10 +491,10 @@ void board_init_console(void);
 void board_init_uart(UART_Type *ptr);
 void board_init_i2c(I2C_Type *ptr);
 void board_init_lcd(void);
-
+void board_panel_para_to_lcdc(lcdc_config_t *config);
 void board_init_can(CAN_Type *ptr);

-uint32_t board_init_dram_clock(void);
+uint32_t board_init_femc_clock(void);

 void board_init_sdram_pins(void);
 void board_init_gpio_pins(void);
@@ -478,6 +540,7 @@ void board_init_sd_pins(SDXC_Type *ptr);
 uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq);
 void board_sd_switch_pins_to_1v8(SDXC_Type *ptr);
 bool board_sd_detect_card(SDXC_Type *ptr);
+void board_sd_power_switch(SDXC_Type *ptr, bool on_off);

 void board_init_adc12_pins(void);
 void board_init_adc16_pins(void);
@@ -485,8 +548,10 @@ void board_init_adc16_pins(void);
 void board_init_usb_pins(void);
 void board_usb_vbus_ctrl(uint8_t usb_index, uint8_t level);

+uint8_t    board_enet_get_dma_pbl(ENET_Type *ptr);
 hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_reset_enet_phy(ENET_Type *ptr);
+hpm_stat_t board_init_enet_pins(ENET_Type *ptr);
 hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal);

 hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr);
@@ -1 +1,50 @@
-riscv expose_csrs 262,774,1984-2005,2015-2017,2048,2057,2059,2060,2500-2505,2509,2511,2513-2516,2528,2531-2534
+riscv expose_csrs 262=scounteren
+riscv expose_csrs 800=mcountinhibit
+riscv expose_csrs 1984=milmb
+riscv expose_csrs 1985=mdlmb
+riscv expose_csrs 1986=mecc_code
+riscv expose_csrs 1987=mnvec
+riscv expose_csrs 1988=mxstatus
+riscv expose_csrs 1989=mpft_ctl
+riscv expose_csrs 1990=mhsp_ctl
+riscv expose_csrs 1991=msp_bound
+riscv expose_csrs 1992=msp_base
+riscv expose_csrs 1993=mdcause
+riscv expose_csrs 1994=mcache_ctl
+riscv expose_csrs 1995=mcctlbeginaddr
+riscv expose_csrs 1996=mcctlcommand
+riscv expose_csrs 1997=mcctldata
+riscv expose_csrs 1998=mcounterwen
+riscv expose_csrs 1999=mcounterinten
+riscv expose_csrs 2000=mmisc_ctl
+riscv expose_csrs 2001=mcountermask_m
+riscv expose_csrs 2002=mcountermask_s
+riscv expose_csrs 2003=mcountermask_u
+riscv expose_csrs 2004=mcounterovf
+riscv expose_csrs 2005=mslideleg
+riscv expose_csrs 2015=mclk_ctl
+riscv expose_csrs 2016=dexc2dbg
+riscv expose_csrs 2017=ddcause
+riscv expose_csrs 2048=uitb
+riscv expose_csrs 2049=ucode
+riscv expose_csrs 2057=udcause
+riscv expose_csrs 2059=ucctlbeginaddr
+riscv expose_csrs 2060=ucctlcommand
+riscv expose_csrs 2500=slie
+riscv expose_csrs 2501=slip
+riscv expose_csrs 2505=sdcause
+riscv expose_csrs 2509=scctldata
+riscv expose_csrs 2511=scounterinten
+riscv expose_csrs 2513=scountermask_m
+riscv expose_csrs 2514=scountermask_s
+riscv expose_csrs 2515=scountermask_u
+riscv expose_csrs 2516=scounterovf
+riscv expose_csrs 2528=scountinhibit
+riscv expose_csrs 2531=shpmevent3
+riscv expose_csrs 2532=shpmevent4
+riscv expose_csrs 2533=shpmevent5
+riscv expose_csrs 2534=shpmevent6
+riscv expose_csrs 4032=micm_cfg
+riscv expose_csrs 4033=mdcm_cfg
+riscv expose_csrs 4034=mmsc_cfg
+riscv expose_csrs 4035=mmsc_cfg2
@@ -1,5 +1,7 @@
 # Copyright 2021 hpmicro
 # SPDX-License-Identifier: BSD-3-Clause
+#
+

 set _CHIP hpm6750
 set _CPUTAPID 0x1000563D
@@ -12,27 +14,48 @@ $_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-are

 targets $_TARGET0

-set _TARGET1 $_CHIP.cpu1
-target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+proc dmi_write {reg value} {
+    $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc dmi_read {reg} {
+    set v [$::_TARGET0 riscv dmi_read ${reg}]
+    return ${v}
+}
+proc dmi_write_memory {addr value} {
+    dmi_write 0x39 ${addr}
+    dmi_write 0x3C ${value}
+}
+
+proc dmi_read_memory {addr} {
+    set sbcs [expr 0x100000 | [dmi_read 0x38]]
+    dmi_write 0x38 ${sbcs}
+    dmi_write 0x39 ${addr}
+    set value [dmi_read 0x3C]
+    return ${value}
+}

 proc release_core1 {} {
    # set start point for core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C08
-    $::_TARGET0 riscv dmi_write 0x3C 0x20016284
+    dmi_write_memory 0xF4002C08 0x20016284

    # set boot flag for core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C0C
-    $::_TARGET0 riscv dmi_write 0x3C 0xC1BEF1A9
+    dmi_write_memory 0xF4002C0C 0xC1BEF1A9

    # release core1
-    $::_TARGET0 riscv dmi_write 0x39 0xF4002C00
-    $::_TARGET0 riscv dmi_write 0x3C 0x1000
+    dmi_write_memory 0xF4002C00 0x1000
 }

-$_TARGET1 configure -event reset-deassert-pre release_core1
-$_TARGET1 configure -event examine-start release_core1
-$_TARGET1 configure -event examine-end {
-    $::_TARGET1 arp_examine
+$_TARGET0 configure -event examine-end {
+    release_core1
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+$_TARGET1 configure -event reset-deassert-pre {
+    $::_TARGET1 arp_poll
+    release_core1
 }

-$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x04000 -work-area-backup 0
@@ -101,14 +101,14 @@ static rt_phy_status phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t sr
    return PHY_STATUS_OK;
 }

-static rt_ssize_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+static rt_size_t phy_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
 {
    *(uint16_t *)data = enet_read_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg);

    return size;
 }

-static rt_ssize_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
+static rt_size_t phy_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
 {
    enet_write_phy(((struct rt_mdio_bus *)bus)->hw_obj, addr, reg,  *(uint16_t *)data);

@@ -170,13 +170,14 @@ static void phy_poll_status(void *parameter)
 {
    int ret;
    phy_info_t phy_info;
-    rt_uint32_t status;
+    rt_bool_t status;
    rt_device_t dev;
    rt_phy_msg_t msg;
    rt_uint32_t speed, duplex;
    phy_device_t *phy_dev;
    struct eth_device* eth_dev;
    char const *ps[] = {"10Mbps", "100Mbps", "1000Mbps"};
+    enet_line_speed_t line_speed[] = {enet_line_speed_10mbps, enet_line_speed_100mbps, enet_line_speed_1000mbps};

    eth_phy_monitor_handle_t *phy_monitor_handle = (eth_phy_monitor_handle_t *)parameter;

@@ -207,6 +208,8 @@ static void phy_poll_status(void *parameter)
            {
                LOG_I("PHY Speed: %s", ps[phy_dev->phy_info.phy_speed]);
                LOG_I("PHY Duplex: %s\n", phy_dev->phy_info.phy_duplex & PHY_FULL_DUPLEX ? "full duplex" : "half duplex");
+                enet_set_line_speed(phy_monitor_handle->phy_handle[i]->instance, line_speed[phy_dev->phy_info.phy_speed]);
+                enet_set_duplex_mode(phy_monitor_handle->phy_handle[i]->instance, phy_dev->phy_info.phy_duplex);
            }
        }
    }
@@ -272,7 +275,7 @@ static void phy_monitor_thread_entry(void *args)

 int phy_device_register(void)
 {
-    rt_err_t err = -RT_ERROR;
+    rt_err_t err = RT_ERROR;
    rt_thread_t thread_phy_monitor;

    /* Set ops for PHY */
@@ -308,7 +311,7 @@ int phy_device_register(void)
    }
    else
    {
-        err = -RT_ERROR;
+        err = RT_ERROR;
    }

    return err;
@@ -156,6 +156,3 @@ typedef struct {
 #endif
 #endif

-
-
-
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -32,7 +32,8 @@ extern struct fal_flash_dev nor_flash0;
 {                                                                                    \
    {FAL_PART_MAGIC_WORD,       "app", NOR_FLASH_DEV_NAME,         0,           4*1024*1024,    0}, \
    {FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME,         4*1024*1024, 3*1024*1024,    0}, \
-    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 9*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,  "download", NOR_FLASH_DEV_NAME,         7*1024*1024, 8*1024*1024,    0}, \
+    {FAL_PART_MAGIC_WORD,   "flashdb", NOR_FLASH_DEV_NAME,        15*1024*1024, 1*1024*1024,    0}, \
 }
 #endif /* FAL_PART_HAS_TABLE_CFG */
 #endif /* RT_USING_FAL */
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 hpmicro
+ * Copyright (c) 2022-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
@@ -20,18 +20,19 @@

 #if defined(FLASH_XIP) && (FLASH_XIP == 1)

+static rt_base_t s_interrupt_level;
 #define FAL_ENTER_CRITICAL() do {\
        rt_enter_critical();\
-        disable_irq_from_intc();\
        fencei();\
-    }while(0)
+        s_interrupt_level = rt_hw_interrupt_disable();\
+    } while(0)

 #define FAL_EXIT_CRITICAL() do {\
        ROM_API_TABLE_ROOT->xpi_driver_if->software_reset(BOARD_APP_XPI_NOR_XPI_BASE);\
        fencei();\
        rt_exit_critical();\
-        enable_irq_from_intc();\
-    }while(0)
+        rt_hw_interrupt_enable(s_interrupt_level);\
+    } while(0)

 #define FAL_RAMFUNC __attribute__((section(".isr_vector")))

@@ -1,10 +1,18 @@
 /*
- * Copyright (c) 2021 hpmicro
+ * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */

+/*
+ * Note:
+ *   PY and PZ IOs: if any SOC pin function needs to be routed to these IOs,
+ *  besides of IOC, PIOC/BIOC needs to be configured SOC_GPIO_X_xx, so that
+ *  expected SoC function can be enabled on these IOs.
+ *
+ */
+
 #include "board.h"

 void init_uart_pins(UART_Type *ptr)
@@ -12,14 +20,16 @@ void init_uart_pins(UART_Type *ptr)
    if (ptr == HPM_UART0) {
        HPM_IOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_UART0_RXD;
        HPM_IOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_UART0_TXD;
-        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
-        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+        /* PY port IO needs to configure PIOC as well */
+        HPM_PIOC->PAD[IOC_PAD_PY07].FUNC_CTL = IOC_PY07_FUNC_CTL_SOC_PY_07;
+        HPM_PIOC->PAD[IOC_PAD_PY06].FUNC_CTL = IOC_PY06_FUNC_CTL_SOC_PY_06;
    } else if (ptr == HPM_UART2) {
        HPM_IOC->PAD[IOC_PAD_PE16].FUNC_CTL = IOC_PE16_FUNC_CTL_UART2_TXD;
        HPM_IOC->PAD[IOC_PAD_PE21].FUNC_CTL = IOC_PE21_FUNC_CTL_UART2_RXD;
    } else if (ptr == HPM_UART13) {
        HPM_IOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_UART13_RXD;
        HPM_IOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_UART13_TXD;
+        /* PZ port IO needs to configure BIOC as well */
        HPM_BIOC->PAD[IOC_PAD_PZ08].FUNC_CTL = IOC_PZ08_FUNC_CTL_SOC_PZ_08;
        HPM_BIOC->PAD[IOC_PAD_PZ09].FUNC_CTL = IOC_PZ09_FUNC_CTL_SOC_PZ_09;
    }
@@ -83,11 +93,13 @@ void init_i2c_pins_as_gpio(I2C_Type *ptr)
    if (ptr == HPM_I2C0) {
        /* I2C0 */
        HPM_IOC->PAD[IOC_PAD_PZ11].FUNC_CTL = IOC_PZ11_FUNC_CTL_GPIO_Z_11;
-        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
        HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PZ10_FUNC_CTL_GPIO_Z_10;
+        /* PZ port IO needs to configure BIOC as well */
+        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
        HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
    } else {
-        while(1);
+        while (1) {
+        }
    }
 }

@@ -98,12 +110,14 @@ void init_i2c_pins(I2C_Type *ptr)
                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
        HPM_IOC->PAD[IOC_PAD_PZ10].FUNC_CTL = IOC_PB10_FUNC_CTL_I2C0_SDA
                                            | IOC_PAD_FUNC_CTL_LOOP_BACK_MASK;
+        /* PZ port IO needs to configure BIOC as well */
        HPM_BIOC->PAD[IOC_PAD_PZ11].FUNC_CTL = 3;
        HPM_BIOC->PAD[IOC_PAD_PZ10].FUNC_CTL = 3;
        HPM_IOC->PAD[IOC_PAD_PZ11].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
        HPM_IOC->PAD[IOC_PAD_PZ10].PAD_CTL = IOC_PAD_PAD_CTL_OD_MASK;
    } else {
-        while(1);
+        while (1) {
+        }
    }
 }

@@ -239,16 +253,18 @@ void init_i2s_pins(I2S_Type *ptr)
 void init_dao_pins(void)
 {
    HPM_IOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_DAOR_P;
-    HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08;
    HPM_IOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_DAOR_N;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY08].FUNC_CTL = IOC_PY08_FUNC_CTL_SOC_PY_08;
    HPM_PIOC->PAD[IOC_PAD_PY09].FUNC_CTL = IOC_PY09_FUNC_CTL_SOC_PY_09;
 }

 void init_pdm_pins(void)
 {
    HPM_IOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_PDM0_CLK;
-    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
    HPM_IOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_PDM0_D_0;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY10].FUNC_CTL = IOC_PY10_FUNC_CTL_SOC_PY_10;
    HPM_PIOC->PAD[IOC_PAD_PY11].FUNC_CTL = IOC_PY11_FUNC_CTL_SOC_PY_11;
 }

@@ -260,10 +276,10 @@ void init_vad_pins(void)

 void init_cam_pins(void)
 {
-#ifdef CAMREA_RESET_PWDN_CONFIGURABLE
-    HPM_IOC->PAD[IOC_PAD_PX08].FUNC_CTL = IOC_PX08_FUNC_CTL_GPIO_X_08;
-    HPM_IOC->PAD[IOC_PAD_PX09].FUNC_CTL = IOC_PX09_FUNC_CTL_GPIO_X_09;
-#endif
+    /* configure rst pin function */
+    HPM_IOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_GPIO_Y_05;
+    /* PY port IO needs to configure PIOC */
+    HPM_PIOC->PAD[IOC_PAD_PY05].FUNC_CTL = IOC_PY05_FUNC_CTL_SOC_PY_05;

    HPM_IOC->PAD[IOC_PAD_PA10].FUNC_CTL = IOC_PA10_FUNC_CTL_CAM0_XCLK;
    HPM_IOC->PAD[IOC_PAD_PA11].FUNC_CTL = IOC_PA11_FUNC_CTL_CAM0_PIXCLK;
@@ -401,9 +417,9 @@ void init_can_pins(CAN_Type *ptr)
    }
 }

-void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8)
+void init_sdxc_pins(SDXC_Type *ptr, bool use_1v8)
 {
-    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);;
+    uint32_t cmd_func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17) | IOC_PAD_FUNC_CTL_LOOP_BACK_SET(1);
    uint32_t func_ctl = IOC_PAD_FUNC_CTL_ALT_SELECT_SET(17);
    uint32_t pad_ctl = IOC_PAD_PAD_CTL_MS_SET(use_1v8) | IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) |
                       IOC_PAD_PAD_CTL_PS_SET(1);
@@ -435,10 +451,27 @@ void init_sdxc_pins(SDXC_Type * ptr, bool use_1v8)
        HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
        HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = pad_ctl;
        HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN;
-
    }
 }

+void init_sdxc_power_pin(SDXC_Type *ptr)
+{
+    /* Not supported by current board */
+}
+void init_sdxc_vsel_pin(SDXC_Type *ptr)
+{
+    /* Not suppored by current board */
+}
+
+void init_sdxc_card_detection_pin(SDXC_Type *ptr)
+{
+    /* CDN */
+    HPM_IOC->PAD[IOC_PAD_PD15].FUNC_CTL = IOC_PD15_FUNC_CTL_GPIO_D_15;
+    HPM_IOC->PAD[IOC_PAD_PD15].PAD_CTL = IOC_PAD_PAD_CTL_DS_SET(7) | IOC_PAD_PAD_CTL_PE_SET(1) |
+                       IOC_PAD_PAD_CTL_PS_SET(1);
+    HPM_GPIO0->OE[GPIO_OE_GPIOD].CLEAR = 1UL << BOARD_APP_SDCARD_CDN_GPIO_PIN;
+}
+
 void init_clk_obs_pins(void)
 {
    HPM_IOC->PAD[IOC_PAD_PB02].FUNC_CTL = IOC_PB02_FUNC_CTL_SYSCTL_CLK_OBS_0;
--- a/Show More
+++ b/Show More